Making Plural Separate Devices Patents (Class 438/110)
  • Patent number: 10971467
    Abstract: A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without bumps, a first dielectric layer formed on a surface of the second chip and through-holes fabricated in the first dielectric layer; a plastic package material; a second dielectric layer; a metal redistribution layer for interconnecting within and between the first chip and the second chip; under bump metallization layers and micro-bumps. By fabricating the dielectric layers with the through-holes on the surfaces of the first chip and the second chip, exposing the bumps of the first chip and metal pads of the second chip and subsequently fabricating the metal redistribution layer, the interconnections within and between the first chip and the second chip are achieved and thereby the integrated package of the first chip and the second chip is achieved.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: April 6, 2021
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yuedong Qiu, ChengChung Lin
  • Patent number: 10937767
    Abstract: Disclosed herein are a chip packaging method and a device with packaged chips. The method includes: providing a support plate attached thereon with a first bonding layer; placing a plurality of chips onto the first bonding layer at intervals; performing a plastic packaging process to form a plastic packaging layer filling the gaps between the chips over the support plate, so that the plastic packaged chips are formed; removing the support plate and the first bonding layer to form the plastic packaged chips; forming an insulating layer over the plastic packaged chips, forming openings in the insulating layer and depositing metal in the openings to form a metal conducting layer and an interconnect circuitry; dicing the plastic packaged chips into a plurality of modules. The method reduces the distances between the chips, reduces the size of terminal products, and facilitates the miniaturization of the terminal products.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: March 2, 2021
    Assignee: INNO-PACH TECHNOLOGY PTE LTD
    Inventors: Wanning Zhang, Deze Yu
  • Patent number: 10867930
    Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Ping Pu, Hsiao-Wen Lee
  • Patent number: 10854763
    Abstract: Monolithic multi-dimensional integrated circuits and memory architecture are provided. Exemplary integrated circuits comprise an electronic board having a first side and a second side, a multi-dimensional electronic package having multiple planes, and one or more semiconductor wafers mounted on the first side and the second side of the electronic board and on the multiple planes of the electronic package. Exemplary monolithic multi-dimensional memory architecture comprises one or more tiers, one or more monolithic inter-tier vias spanning the one or more tiers, at least one multiplexer disposed in one of the tiers, and control logic determining whether memory cells are active and which memory cells are active and controlling usage of the memory cells based on such determination. Each tier has a memory cell, and the inter-tier vias act as crossbars in multiple directions. The multiplexer is communicatively coupled to the memory cell in the respective tier.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: December 1, 2020
    Assignee: GBT TECHNOLOGIES INC.
    Inventors: Danny Rittman, Aliza Schnapp
  • Patent number: 10825761
    Abstract: An electronic device includes a substrate, a structure over the substrate having an edge wall defining at least a portion of an opening exposing a surface of the substrate, and a dielectric material adjacent and in contact with the edge wall and an adjacent portion of the surface of the substrate. The dielectric material has a profile tapering downward from adjacent the edge wall toward the substrate. Other electronic devices include a substrate and a solder mask over the substrate. The solder mask defines an opening therethrough. A supplemental mask is within the opening of the solder mask, and has a sidewall that slopes away from the solder mask. A conductive structure is adjacent and in contact with at least one of the solder mask or the supplemental mask.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, Jack E. Murray
  • Patent number: 10815120
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor structure having a bottom substrate, a sacrificial layer on the bottom substrate, and a top substrate on the sacrificial layer. The sacrificial layer has a first opening exposing a first portion of the bottom substrate and a second opening exposing a second portion of the bottom substrate. The method further includes forming a first metal layer on the top substrate and/or on the exposed first portion of the bottom substrate, forming an adhesive layer on the first metal layer, and forming a second metal layer on the adhesive layer defining one or more pads.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: October 27, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Chao Zheng, Wei Wang
  • Patent number: 10804130
    Abstract: A structure with micro device including a substrate, at least one micro device, and at least one holding structure is provided. The micro device having a top surface is disposed on the substrate, and the top surface is away from the substrate. The holding structure including at least one connecting portion and at least one holding portion is disposed on the substrate. The connecting portion is disposed on at least one edge of the micro device. The holding portion connects the connecting portion and extends to the substrate. From a top view direction, a width of the connecting portion gradually increases from the edge of the micro device to the holding portion.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: October 13, 2020
    Assignee: PlayNitride Inc.
    Inventors: Chih-Ling Wu, Yi-Min Su, Yu-Yun Lo
  • Patent number: 10797029
    Abstract: A structure with micro device includes a substrate, a plurality of micro devices, and a plurality of holding structures. The micro devices are disposed on the substrate and arranged in multiple rows. Each of the micro devices has a top surface. The holding structures are respectively disposed on the top surface of each of the micro devices and extend to the substrate. Distances between the holding structure on the micro devices on any one of the rows and the holding structures on the micro devices on two adjacent rows are different.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: October 6, 2020
    Assignee: PlayNitride Inc.
    Inventors: Chih-Ling Wu, Yi-Min Su, Yu-Yun Lo
  • Patent number: 10689246
    Abstract: A semiconductor device includes a bottom substrate, a sacrificial layer on the bottom substrate and including a first opening exposing a first portion of the bottom substrate and a second opening exposing a second portion of the bottom substrate, a top substrate on the sacrificial layer and on the second opening forming a cavity, a first metal layer on the top substrate and/or on the exposed first portion of the bottom substrate, an adhesive layer on the first metal layer, and a second metal layer on the adhesive layer defining one or more pads. The pad includes a stack-layered structure of a first metal layer on the bottom substrate, an adhesive layer on the first metal layer, and a second metal layer on the adhesive layer. The thus formed structure reduces the pad contact resistance.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: June 23, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Chao Zheng, Wei Wang
  • Patent number: 10607861
    Abstract: A method for wafer dicing and removing separated integrated circuit (IC) dies from a carrier substrate includes mounting a wafer on a substrate using an adhesive layer, laser scribing the adhesive layer to create defect regions in the adhesive layer, and performing a breaking step to separate the laser-scribed adhesive layer into separated adhesive portions corresponding to the IC dies. For a stealth-dicing (SD) technique, defect regions also are created in the wafer using a laser and the breaking step is an expansion step that simultaneously separates the dies and corresponding portions of adhesive. For a dice-before-grind (DBG) technique, the dies are separated by backside grinding before the breaking step. Efficient adhesive-layer separation is achieved with reduced backside chipping associated with conventional blade dicing.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: March 31, 2020
    Assignee: NXP B.V.
    Inventors: Siriluck Wongratanaporngoorn, Yao Jung Chang, Ekapong Tangpattanasaeree, Paradee Jitrungruang, Pitak Seantumpol
  • Patent number: 10559525
    Abstract: An embedded silicon substrate fan-out type 3D packaging structure, comprising: a silicon substrate; and at least one functional chip, wherein the silicon substrate includes at least one groove, the at least one functional chip is embedded in the at least one groove with a pad surface facing upward, the at least one functional chip is bonded with the at least one groove through a polymer; a front surface of the silicon substrate, the pad surface of the at least one functional chip, and at least one gap between the at least one chip and the at least one groove are covered with a polymer material, and the polymer on pads on the at least one functional chip is opened; at least one conductive through hole is formed on the silicon substrate; and the silicon substrate further includes electrical interconnect structures, a first metal re-wiring and a second metal re-wiring.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 11, 2020
    Assignee: HUATIAN TECHNOLOGY (KUNSHAN) ELECTRONICS CO., LTD.
    Inventor: Daquan Yu
  • Patent number: 10483184
    Abstract: A recursive metal-embedded chip assembly (R-MECA) process and method is described for heterogeneous integration of multiple die from diverse device technologies. The recursive aspect of this integration technology enables integration of increasingly-complex subsystems while bridging different scales for devices, interconnects and components. Additionally, the proposed concepts include high thermal management performance that is maintained through the multiple recursive levels of R-MECA, which is a key requirement for high-performance heterogeneous integration of digital, analog mixed signal and RF subsystems. At the wafer-scale, chips from diverse technologies and different thicknesses are initially embedded in a metal heat spreader surrounded by a mesh wafer host. An embodiment uses metal embedding on the backside of the chips as a key differentiator for high-density integration, and built-in thermal management.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 19, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: Florian G. Herrault, Miroslav Micovic
  • Patent number: 10475972
    Abstract: A light-emitting diode (LED) package includes: a reflective structure including a cavity, a bottom portion having a through hole, and a sidewall portion surrounding the cavity and the bottom portion and having an inclined inner side surface; an electrode pad inserted into the through hole; an LED on the bottom portion in the cavity, the LED including a light-emitting structure electrically connected to the electrode pad and a phosphor formed on the light-emitting structure; and a lens structure filling the cavity and formed on the reflective structure.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-sub Lee, Yong-il Kim, Han-kyu Seong, Young-jin Choi
  • Patent number: 10453989
    Abstract: Disclosed is a method for producing a plurality of semiconductor chips (10). A composite (1), which comprises a carrier (4) and a semiconductor layer sequence (2, 3), is provided. Separating trenches (17) are formed in the semiconductor layer sequence (2, 3) along an isolation pattern (16). A filling layer (11) limiting the semiconductor layer sequence (2, 3) toward the separating trenches (17) is applied to a side of the semiconductor layer sequence (2, 3) facing away from the carrier (4). Furthermore, a metal layer (10) adjacent to the filling layer (11) is applied in the separating trenches (17). The semiconductor chips (20) are isolated by removing the metal layer (10) adjacent to the filling layer (11) in the separating trenches (17). Each isolated semiconductor chip (20) has one part of the semiconductor layer sequence (2, 3), and of the filling layer (11). Also disclosed is a semiconductor chip (10).
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: October 22, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Lutz Hoeppel, Alexander F. Pfeuffer, Dominik Scholz, Isabel Otto, Norwin Von Malm, Stefan Illek
  • Patent number: 10431487
    Abstract: In certain embodiments, a method of making a semiconductor structure suitable for transfer printing (e.g., micro-transfer printing) includes providing a support substrate and disposing and processing one or more semiconductor layers on the support substrate to make a completed semiconductor device. A patterned release layer and, optionally, a capping layer are disposed on or over the completed semiconductor device and the patterned release layer or capping layer, if present, are bonded to a handle substrate with a bonding layer. The support substrate is removed to expose the completed semiconductor device and, in some embodiments, a portion of the patterned release layer. In some embodiments, an entry path is formed to expose a portion of the patterned release layer. In some embodiments, the release layer is etched and the completed semiconductor devices transfer printed (e.g., micro-transfer printed) from the handle substrate to a destination substrate.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: October 1, 2019
    Assignee: X-Celeprint Limited
    Inventors: Christopher Bower, Matthew Meitl, António José Marques Trindade, Ronald S. Cok, Brook Raymond, Carl Prevatte
  • Patent number: 10431554
    Abstract: A semiconductor device package includes: (1) a carrier; (2) an electronic component disposed over a top surface of the carrier; (3) a package body disposed over the top surface of the carrier and covering the electronic component; and (4) a shield layer, including a first magnetically permeable layer disposed over the package body, a first electrically conductive layer disposed over the first magnetically permeable layer, and a second magnetically permeable layer disposed over the first electrically conductive layer. The first electrically conductive layer is interposed between the first magnetically permeable layer and the second magnetically permeable layer. A permeability of the first electrically conductive layer is different from a permeability of the first magnetically permeable layer and a permeability of the second magnetically permeable layer.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: October 1, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: I-Chia Lin, Chieh-Chen Fu, Kuo Hsien Liao, Cheng-Nan Lin
  • Patent number: 10395966
    Abstract: In certain embodiments, a method of making a semiconductor structure suitable for transfer printing (e.g., micro-transfer printing) includes providing a support substrate and disposing and processing one or more semiconductor layers on the support substrate to make a completed semiconductor device. A patterned release layer and, optionally, a capping layer are disposed on or over the completed semiconductor device and the patterned release layer or capping layer, if present, are bonded to a handle substrate with a bonding layer. The support substrate is removed to expose the completed semiconductor device and, in some embodiments, a portion of the patterned release layer. In some embodiments, an entry path is formed to expose a portion of the patterned release layer. In some embodiments, the release layer is etched and the completed semiconductor devices transfer printed (e.g., micro-transfer printed) from the handle substrate to a destination substrate.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: August 27, 2019
    Assignee: X-Celeprint Limited
    Inventors: Christopher Bower, Matthew Meitl, António José Marques Trindade, Ronald S. Cok, Brook Raymond, Carl Prevatte
  • Patent number: 10242967
    Abstract: Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 26, 2019
    Assignee: Raytheon Company
    Inventors: John J. Drab, Jason G. Milne
  • Patent number: 10224231
    Abstract: In certain embodiments, a method of making a semiconductor structure suitable for transfer printing (e.g., micro-transfer printing) includes providing a support substrate and disposing and processing one or more semiconductor layers on the support substrate to make a completed semiconductor device. A patterned release layer and, optionally, a capping layer are disposed on or over the completed semiconductor device and the patterned release layer or capping layer, if present, are bonded to a handle substrate with a bonding layer. The support substrate is removed to expose the completed semiconductor device and, in some embodiments, a portion of the patterned release layer. In some embodiments, an entry path is formed to expose a portion of the patterned release layer. In some embodiments, the release layer is etched and the completed semiconductor devices transfer printed (e.g., micro-transfer printed) from the handle substrate to a destination substrate.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: March 5, 2019
    Assignee: X-Celeprint Limited
    Inventors: Christopher Bower, Matthew Meitl, António José Marques Trindade, Ronald S. Cok, Brook Raymond, Carl Prevatte
  • Patent number: 10121696
    Abstract: An electronic device package and a manufacturing method thereof are provided. The electronic device package includes a flexible substrate, a first wiring structure, a first electronic device and a thermoplastic film having a second wiring structure. The first wiring structure is disposed on the flexible substrate. The first electronic device is disposed on the flexible substrate. The first electronic device and the first wiring structure are separated from each other. The thermoplastic film is welded to the flexible substrate and seals the first electronic device. The second wiring structure electrically connects the first wiring structure to the first electronic device. The electronic device package can be manufactured with a production cost.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: November 6, 2018
    Assignee: Winbond Electronics Corp.
    Inventor: Yu-Hsuan Ho
  • Patent number: 9865468
    Abstract: Provided is a method for manufacturing a semiconductor chip including forming a groove on a front surface side along a cut area of a substrate, and a concave portion deeper than the groove on the front surface side as a positioning mark for a cutting member that performs cutting from a back surface of the substrate along the groove on the front surface side, thinning the substrate so as to reach the concave portion and not reach the groove on the front surface side, in the back surface of the substrate, positioning the cutting member from the back surface of the substrate by using the concave portion exposed on the back surface of the substrate as the positioning mark, and performing cutting from the back surface side of the substrate toward the groove on the front surface side of the substrate by using the positioned cutting member.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: January 9, 2018
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Kenichi Ono, Michiaki Murata, Tsutomu Otsuka
  • Patent number: 9780041
    Abstract: A method for making EMI shielding layer on a package is disclosed to include the steps of: a) disposing a UV curable adhesive which can be thermally released on a light-transmissive substrate; b) placing the package on the UV curable adhesive in such a way that the UV curable adhesive adheres to and cover a surface of the package having solder pads; c) irradiating UV light toward the light-transmissive substrate to cure the UV curable adhesive; d) forming an EMI shielding layer on the package; and e) thermally releasing the UV curable adhesive.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: October 3, 2017
    Assignee: Universal Scientific Industrial (Shanghai) Co., Ltd.
    Inventor: Pioneer Chien
  • Patent number: 9653407
    Abstract: The present disclosure relates to a semiconductor device package and a method for manufacturing the semiconductor device package. The semiconductor device package includes a substrate, a grounding element, a component, a package body and a conductive layer. The grounding element is disposed in the substrate and includes a connection surface exposed at a second portion of a lateral surface of the substrate. The component is disposed on a top surface of the substrate. The package body covers the component and the top surface of the substrate. A lateral surface of the package body is aligned with the lateral surface of the substrate. The conductive layer covers a top surface and the lateral surface of the package body, and further covers the second portion of the lateral surface of the substrate. A first portion of the lateral surface of the substrate is exposed from the conductive layer.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: May 16, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shih-Ren Chen, Cheng-Nan Lin
  • Patent number: 9647171
    Abstract: Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are useful for assembling electronic devices where one or more device components are embedded in a polymer which is patterned during the embedding process with trenches for electrical interconnects between device components. Some methods described herein are useful for assembling electronic devices by printing methods, such as by dry transfer contact printing methods. Also described herein are GaN light emitting diodes and methods for making and arranging GaN light emitting diodes, for example for display or lighting systems.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: May 9, 2017
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: John A. Rogers, Ralph Nuzzo, Hoon-sik Kim, Eric Brueckner, Sang Il Park, Rak Hwan Kim
  • Patent number: 9570406
    Abstract: The present disclosure integrates electromagnetic shielding into a wafer level fan-out packaging process. First, a mold wafer having multiple modules is provided. Each module includes a die with an I/O port and is surrounded by an inter-module area. A redistribution structure that includes a shield connected element coupled to the I/O port of each module is formed over a bottom surface of the mold wafer. The shield connected element extends laterally from the I/O port into the inter-module area for each module. Next, the mold wafer is sub-diced at each inter-module area to create a cavity. A portion of the shield connected element is then exposed through the bottom of each cavity. A shielding structure is formed over a top surface of the mold wafer and exposed faces of each cavity. The shielding structure is in contact with the shield connected element.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: February 14, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Thong Dang, Dan Carey, Ma Shirley Asoy
  • Patent number: 9426887
    Abstract: A wiring board according to the present invention includes an insulating board; a first pad provided inwardly from a surface of the insulating board and electrically connected to an electrode of an electronic component; a second pad provided on the surface of the insulating board and electrically connected to a lead terminal. The first pad and the second pad include a first layer region made of copper and a second layer region arranged on the first layer region and made of nickel, and a thickness of the second layer region of the second pad is larger than a thickness of the second layer region of the first pad.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: August 23, 2016
    Assignee: Kyocera Corporation
    Inventors: Yoshihiro Hosoi, Takayuki Taguchi, Hidetoshi Yugawa
  • Patent number: 9397031
    Abstract: Method of and devices for protecting semiconductor packages are provided. The methods and devices comprise loading a leadframe containing multiple semiconductor packages into a molding device, adding a molding material on a surface of the leadframe, molding the molding material, such that the molding material covers the entire surface of the semiconductor packages except conducting terminals, and singulating the semiconductor packages from the leadframe after molding the molding material.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: July 19, 2016
    Assignee: UTAC THAI LIMITED
    Inventor: Saravuth Sirinorakul
  • Patent number: 9287248
    Abstract: Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: March 15, 2016
    Assignee: INTEL CORPORATION
    Inventors: John S. Guzek, Debendra Mallik, Sasha N. Oster, Timothy E. McIntosh
  • Patent number: 9252065
    Abstract: In accordance with some embodiments, a package structure and a method for forming a package structure are provided. The package structure includes a semiconductor die and a molding compound partially or completely encapsulating the semiconductor die. The package structure also includes a through package via in the molding compound. The package structure further includes an interfacial layer between the through package via and the molding compound. The interfacial layer includes an insulating material and is in direct contact with the molding compound.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: February 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 9230924
    Abstract: In order to securely ground an exterior shield and reduce burden imposed on a dicing blade and the exterior shield, a method of producing a semiconductor module comprises a hole-forming step of forming a hole 30 extending from a top surface of a sealing resin layer 3 to a ground wiring 111 (112) provided at a collective substrate 100, a film-forming step of forming an electrically conductive film made of an electrically conductive material so as to cover at least the top surface of the sealing resin layer 3, an internal surface of the hole 20, and the ground wiring 111 (112), and a separation step of separating from each other a plurality of individual module sections which the individual module section comprises.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: January 5, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takae Sakai, Masahiro Murakami, Masahiko Kushino, Yoshihisa Amano, Shinichi Tokuno
  • Patent number: 9224672
    Abstract: An electronic device comprises a multi-layer printed circuit board. On the printed circuit board there is installed electronic components and a metal frame that encloses at least part of the electronic components. A layer of bonded anisotropic conductive film is disposed on the frame and the electronic components. The layer connects thermally a sheet of metal foil on the frame and on the electronic components. The sheet of metal foil covers the electronic component and the metal frame.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: December 29, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Lasse Pykäri, Ilkka J. Saarinen, Matti T. Koskinen
  • Patent number: 9214439
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: December 15, 2015
    Assignee: Intel Corporation
    Inventors: Ravi K. Nalla, Mathew J. Manusharow
  • Patent number: 9177862
    Abstract: A fabrication method of a semiconductor stack structure mainly includes: singulating a wafer of a first specification into a plurality of chips; rearranging the chips into a second specification of a wafer so as to stack the chips on a substrate of the second specification through a plurality of blocks; forming a redistribution layer on the chips; and performing a cutting process to obtain a plurality of semiconductor stack structures. Therefore, the present invention allows a wafer of a new specification to be processed by using conventional equipment without the need of new factory buildings or equipment. As such, chip packages can be timely supplied to meet the replacement speed of electronic products.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 3, 2015
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Hsin Kuan, Long-Sheng Yeou, Tsang-Yu Liu, Chia-Ming Cheng
  • Patent number: 9170274
    Abstract: A wiring board for an electronic parts inspecting device that can be designed and produced relatively quickly, inexpensively, and with few jigs is provided. In certain embodiments the wiring board includes a base board made of an insulating material having a front surface and a back surface, the base board including a plurality of first via conductors as well as first terminals on the front surface and outer terminals on the back surface that are connected to the ends of the first via conductors, and a mounting board on the front surface of the base board having a front side that includes, a plurality of probe pads, a plurality of second terminals that are electrically connected to the first terminals of the base board, and front surface wirings that connect the probe pads to the second terminals. Lastly, a method of manufacturing the same is provided.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: October 27, 2015
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Tomoyoshi Ono, Kazushige Akita, Toshihisa Nomura
  • Patent number: 9147668
    Abstract: A method for fabricating a semiconductor structure is disclosed. First, an interposer is disposed on a carrier. The carrier has a base body and a bonding layer bonded to the base body. The interposer has opposite first and second sides and the first side has a plurality of conductive elements. The interposer is disposed on the carrier with the first side bonded to the bonding layer and the conductive elements embedded in the bonding layer. Then, at least a semiconductor element is disposed on the second side of the interposer. As such, the semiconductor element and the interposer form a semiconductor structure. Since the conductive elements are embedded in the bonding layer instead of the base body, the present invention eliminates the need to form concave portions in the base body for receiving the conductive elements. Therefore, the method of the present invention is applicable to interposers of different specifications.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: September 29, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Tung Yeh, Chun-Tang Lin
  • Patent number: 9137934
    Abstract: Embodiments include devices and methods for manufacturing a module having a first shielded compartment and a second shielded compartment, wherein the first shielded compartment is electrically isolated from the second shielded compartment. Electrical conductivity is controlled in a manner in which current flow between shielded circuits is directed to reduce or eliminate energy from being coupled between one or more shielded compartments on the same module. Each module may have a plurality of individual shielded compartments, where each compartment has a dedicated ground plane. The shields for each compartment may be tied to the dedicated ground plane of the compartment. Because the dedicated ground planes are not tied together, each of the shielded compartments on the modules remains isolated from all the other shielded compartments on the modules. In some embodiments having a plurality of shielded compartments, there is at least one isolated shielded compartment depending upon the design needs of the module.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: September 15, 2015
    Assignee: RF Micro Devices, Inc.
    Inventors: Thomas Scott Morris, Ulrik Riis Madsen, Brian D. Sawyer, Milind Shah, John Robert Siomkos, Mark Alan Crandall, Dan Carey
  • Patent number: 9117682
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: August 25, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • Patent number: 9117898
    Abstract: A processing method for a package substrate composed of a substrate, a plurality of device chips mounted on the substrate in a plurality of separate device regions defined by a plurality of crossing division lines, and a sealing layer for sealing the device chips. The processing method includes a cut mark forming step of moving a cutting blade to cut into the package substrate from the side of the substrate in the regions other than the device regions to the depth passing through the sealing layer, thereby forming a cut mark having a predetermined positional relation to the division lines, and a cutting step of cutting the package substrate from the side of the sealing layer along the division lines by using the cutting blade according to the cut mark after performing the cut mark forming step.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: August 25, 2015
    Assignee: Disco Corporation
    Inventor: Kenichi Iwasaki
  • Patent number: 9099317
    Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: August 4, 2015
    Assignee: UTAC Thai Limited
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul
  • Publication number: 20150147849
    Abstract: Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip.
    Type: Application
    Filed: October 29, 2014
    Publication date: May 28, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yee Na SHIN, Young Nam Hwang, Hyun Bok Kwon, Seung Wan Woo
  • Patent number: 9040350
    Abstract: A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Juin Liu, Chita Chuang, Ching-Wen Hsiao, Chen-Shien Chen, Chen-Cheng Kuo, Chih-Hua Chen
  • Publication number: 20150140738
    Abstract: Provided are a circuit connecting material able to provide good bonding with an opposing electrode, and a semiconductor device manufacturing method using the same. The present invention uses a circuit connecting material, in which a first adhesive layer to be adhered to the semiconductor chip side, and a second adhesive layer having a lowest melting viscosity attainment temperature higher than that of the first adhesive layer are laminated. When the semiconductor chip on which the circuit connecting material is stuck is mounted on a circuit board, a thickness of the first adhesive layer is within a range satisfying formula (1), thereby providing good bonding with the opposing electrode.
    Type: Application
    Filed: March 6, 2013
    Publication date: May 21, 2015
    Inventor: Hironobu Moriyama
  • Patent number: 9029239
    Abstract: A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: May 12, 2015
    Assignee: Sandia Corporation
    Inventors: Anna Tauke-Pedretti, Gregory N. Nielson, Jeffrey G. Cederberg, Jose Luis Cruz-Campa
  • Patent number: 9029194
    Abstract: A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of flipchip dies are mounted on the top leadframe strip with solder bumps of each flipchip bonded to predetermined pad portions on each of the top leadframes. The top leadframe strip is attached to a bottom leadframe strip. The bottom leadframe strip has a plurality of integrally connected bottom leadframes each having a central die attach pad (DAP) portion and a peripheral frame portion. A back face of each flipchip die contacts the DAP portion of each bottom leadframe. Lead portions of each top leadframe are attached to the peripheral frame portion of each bottom leadframe. The top leadframe strip is attached to the bottom leadframe strip with a back face of each flipchip die contacting the DAP portion of each bottom leadframe and with lead portions of each top leadframe attached to the peripheral frame portion of each bottom leadframe.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 12, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Lee Han Meng@Eugene Lee, Anis Fauzi bin Abdul Aziz, Susan Goh Geok Ling, Ng Swee Tiang
  • Patent number: 9029195
    Abstract: A method of manufacturing a semiconductor device includes mounting at least one of a first semiconductor chip and a second semiconductor chip over a die pad of a leadframe, and inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, wherein the leadframe includes first mark formed to the die pad, for indicating a first mounting region for the first semiconductor chip, and second mark formed to the die pad, for indicating a second mounting region for the second semiconductor chip, the first mark is different from the second mark, in at least either one of size and geometry, wherein, in the inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, a mounting position of the first semiconductor chip is inspected when the first semiconductor chip is mounted.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Kenji Nishikawa
  • Publication number: 20150115456
    Abstract: A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer.
    Type: Application
    Filed: December 29, 2014
    Publication date: April 30, 2015
    Inventor: Christopher M. Scanlan
  • Patent number: 9012267
    Abstract: Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: April 21, 2015
    Assignee: Intersil Americas LLC
    Inventors: Jian Yin, Nikhil Vishwanath Kelkar, Loyde Milton Carpenter, Jr.
  • Patent number: 9006031
    Abstract: A semiconductor device has a carrier with a die attach area. Recesses are formed partially through the carrier outside the die attach area. A first conductive layer is conformally applied over a surface of the carrier and into the recesses. A semiconductor die is mounted to the die attach area of the carrier. An encapsulant is deposited over the carrier and semiconductor die. The encapsulant extends into the recesses over the first conductive layer to form encapsulant bumps. The carrier is removed to expose the first conductive layer over the encapsulant bumps. A first insulating layer is formed over the semiconductor die with openings to expose contact pads of the semiconductor die. A second conductive layer is formed between the first conductive layer and the contact pads on the semiconductor die. A second insulating layer is formed over the second conductive layer and semiconductor die.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: April 14, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Henry D. Bathan, Emmanuel A. Espiritu
  • Patent number: 8999810
    Abstract: A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: April 7, 2015
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Vage Oganesian
  • Patent number: 8999756
    Abstract: Method and apparatus for semiconductor device fabrication using a reconstituted wafer is described. In one embodiment, diced semiconductor chips are placed within openings on a frame. A reconstituted wafer is formed by filling a mold compound into the openings. The mold compound is formed around the chips. Finished dies are formed within the reconstituted wafer. The finished dies are separated from the frame.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Matthias Hierlemann