Abstract: A method of making a semiconductor device may include providing a carrier and forming a first photoresist over the carrier with first openings through the first photoresist. A non-planar conductive seed layer may be formed over the first photoresist and conformally extend into the first openings through the first photoresist. A second photoresist may be formed over the first photoresist and over the non-planar conductive seed layer. The second photoresist layer may be patterned to form second openings through the second photoresist that extend to the non-planar conductive seed layer. Conductive posts may be plated over the non-planar conductive seed layer and within the second openings. The second photoresist may be removed while leaving in place the first photoresist. A semiconductor die may be coupled to the carrier. The semiconductor die, the conductive posts, and the first photoresist may be encapsulated with mold compound.

Abstract: Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.

Abstract: A method for separating semiconductor dies of a semiconductor die assembly comprises depositing a first coating on a first surface of the assembly. The assembly comprises a die wafer having a plurality of semiconductor dies and first and second surfaces. A first portion of the die wafer and the first coating is removed between adjacent semiconductor dies to form trenches having an intermediate depth in the die wafer between first and second surfaces such that die corners are formed on either side of the trenches. A protective coating is deposited on the first surface of the die assembly to cover the die corners, trenches and at least a portion of the first coating. The first coating is selectively removed such that portions of the protective coating covering die corners and trenches remain on the die wafer. Adjacent semiconductor dies are separated and the protective coating remains covering the die corners.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a redistribution layer (RDL) having a conductive layer in a first dielectric layer, and a second dielectric layer over the conductive and first dielectric layers. The RDL comprises an extended portion having a first thickness that vertically extends from a bottom surface of the first dielectric layer to a topmost surface of the second dielectric layer. The electronic package comprises a die on the RDL, where the die has sidewall surfaces, a top surface, and a bottom surface that is opposite from the top surface, and an active region on the bottom surface of the die. The first thickness is greater than a second thickness of the RDL that vertically extends from the bottom surface of the first dielectric layer to the bottom surface of the die. The extended portion is over and around the sidewall surfaces.

Abstract: A process can be used to allow processing of thin layers of a workpiece including dies. The workpiece can include a base substrate and a plurality of layers overlying the base substrate. The process can include forming a polymer support layer over the plurality of layers; thinning or removing the base substrate within a component region of the workpiece, wherein the component region includes an electronic device; and singulating the workpiece into a plurality of dies after thinning or removing the base substrate. In another aspect, an electronic device can be formed using such process. In an embodiment, the workpiece may have a size corresponding to a semiconductor wafer to allow wafer-level, as opposed to die-level, processing.

Abstract: A method for manufacturing an SiC wafer from an SiC ingot includes a verifying step of applying a test laser beam to the SiC ingot in a predetermined area with the focal point of the test laser beam set inside the SiC ingot at a predetermined depth from the end surface of the SiC ingot. The test laser beam has a transmission wavelength to SiC, thereby forming a test separation layer inside the SiC ingot at the predetermined depth. The test separation layer has a test modified portion where SiC is decomposed into Si and C and test cracks extend from the test modified portion along a c-plane in the SiC ingot. Whether or not the test cracks have been properly formed is verified. When verifying, the power of the test laser beam is changed to set a proper power at which the test cracks are properly formed.

Abstract: A thin semiconductor device with enhanced edge protection, and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a thin semiconductor device comprising a substrate with an edge-protection region, and a method of manufacturing thereof.

Abstract: A semiconductor device includes a semiconductor chip, a plurality of leads that each includes a lead body portion which has a mounting portion which includes an upper surface whereon a semiconductor chip is bonded, and a lead connecting portion for external connection which projects downward from a lower surface of the lead body portion, a first sealing resin that seals a space that is defined by each lead body portion and each lead connecting portion of the plurality of leads in a region below the upper surface of each lead body portion of the plurality of leads, and a second sealing resin that seals the semiconductor chip in a region above the upper surface of each lead body portion of the plurality of leads.

Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.

Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device comprising at least one first thermally conductive structure proximate at least one of the first integrated circuit device, the second integrated circuit device, and the substrate; and a second thermally conductive structure disposed over the first thermally conductive structure(s), the first integrated circuit device, and the second integrated circuit device, wherein the first thermally conductive structure(s) have a lower electrical conductivity than an electrical conductivity of the second thermally conductive structure. The first thermally conductive structure(s) may be formed by an additive process or may be pre-formed and attached to at least one of the first integrated circuit device, the second integrated circuit device, and the substrate.

Abstract: A semiconductor device includes a semiconductor element, which has a protective film having an opening that exposes a part of a source electrode and disposed/provided to position an end portion thereof on the source electrode. A rewiring layer has wiring that is connected to the source electrode and to a conductive connecting member, and an insulator that covers a part of the source wiring. The insulator includes: an insulating film having (a) an opening for exposing a part of the source wiring, and (b) an end portion of the opening provided in a facing region of the opening; and an insulating film having (c) (i) an opening for exposing a part of the source wiring having a solder arranged therein and (ii) a connecting member arranged therein.

Abstract: A semiconductor device includes a semiconductor chip, a plurality of leads that each includes a lead body portion which has a mounting portion which includes an upper surface whereon a semiconductor chip is bonded, and a lead connecting portion for external connection which projects downward from a lower surface of the lead body portion, a first sealing resin that seals a space that is defined by each lead body portion and each lead connecting portion of the plurality of leads in a region below the upper surface of each lead body portion of the plurality of leads, and a second sealing resin that seals the semiconductor chip in a region above the upper surface of each lead body portion of the plurality of leads.

Abstract: An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.

Abstract: In a method of manufacture, a displacement sensor is provided over a conditioner disk. The conditioner disk is rotated to perform a conditioning process on a polishing surface of a polishing pad. A displacement of the rotating conditioner disk is detected using the displacement sensor during the conditioning process. A height of the conditioner disk is calculated from the detected displacement. An end point of the conditioning process is determined on the polishing surface based on the calculated height.

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.

Abstract: A wafer level chip scale semiconductor package comprises a device semiconductor layer, a backside metallization layer, a film laminate layer, and a metal layer. The device semiconductor layer comprises a plurality of metal electrodes disposed on a front surface of the device semiconductor. Each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer. Each side surface of the metal layer is coplanar with a corresponding side surface of the film laminate layer. A surface area of a back surface of the backside metallization layer is smaller than a surface area of a front surface of the metal layer.

Abstract: Provided is a semiconductor chip mounting tape. The semiconductor chip mounting tape comprises a tape base film including first and second surfaces opposite to each other; and an adhesive film including a third surface facing the first surface of the tape base film, and a fourth surface opposite to the third surface, wherein the adhesive film includes a plurality of voids therein, and the fourth surface of the adhesive film may be adhered to a semiconductor chip.

Abstract: The present disclosure provides a fan-out wafer-level packaging structure and a method for packaging the same. The structure includes: two or more semiconductor chips with a bonding pad, the semiconductor chips are arranged in a fan-out wafer array, and each of the semiconductor chips has an initial position, respectively; a plastic packaging layer, covering surfaces of the semiconductor chips and between the semiconductor chips, each of the semiconductor chips has an offset position, respectively, and the offset position has an offset distance relative to the initial position; a redistribution layer formed on the semiconductor chips, to realize interconnection between the semiconductor chips, the redistribution layer includes at least one first redistribution layer, the first redistribution layer is formed on a surface of the semiconductor chips and is aligned and in contact with the bonding pad of the semiconductor chips; and a metal bump formed on the redistribution layer.

Abstract: The present disclosure provides a package structure and a packaging method. The package structure provided by the present disclosure includes: a package base and a redistribution layer disposed on the package base; where the package base includes a plurality of device areas; and a channel set is provided in the device area, where the channel set is used to connect an electronic device, and the redistribution layer is used to lead a subset of to-be-protected channels that needs electrostatic protection in the channel set out to a preset area on the package base, so that all or part of channels in the subset of to-be-protected channels form a series circuit in the preset area, and the series circuit is used to connect with an electrostatic discharge end. The package structure of the present disclosure can provide electrostatic protection for the channel that needs to be protected during a packaging process.

Abstract: A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.

Abstract: A chip package including an integrated circuit component, a thermal conductive layer, an insulating encapsulant and a redistribution circuit structure is provided. The integrated circuit component includes an amorphous semiconductor portion located at a back surface thereof. The thermal conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein thermal conductivity of the thermal conductive layer is greater than or substantially equal to 10 W/mK. The insulating encapsulant laterally encapsulates the integrated circuit component and the thermal conductive layer. The redistribution circuit structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.

Abstract: A packaged electronic device includes a multilayer lead frame with first and second trace levels, a via level, an insulator, a conductive landing pad and a conductive crack arrest structure, the conductive landing pad has a straight profile that extends along a first direction along a side of the multilayer lead frame, the conductive crack arrest structure has a straight profile along the first direction and the conductive crack arrest structure is spaced from the conductive landing pad along an orthogonal second direction.

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

Abstract: A semiconductor memory device includes a plurality of first sub-blocks defined in a first memory chip; and a plurality of second sub-blocks defined in a second memory chip that is stacked on the first memory chip in a stack direction. Each of a plurality of memory blocks includes one of the plurality of first sub-blocks and one of the plurality of second sub-blocks, and wherein an erase voltage is separately applied to the first memory chip and the second memory chip in an erase operation, and the erase operation is performed in a sub-block.

Abstract: A method for manufacturing a semiconductor device according to the present invention includes at least the following three steps: (A) a step of preparing a first structure (100) including an adhesive laminate film (50) having a heat-resistant resin layer (10), a flexible resin layer (20) and an adhesive resin layer (30) in this order, and a first semiconductor component (60) adhered to the adhesive resin layer (30) and having a first terminal (65); (B) a step of performing solder reflow processing on the first structure (100) in a state where the first semiconductor component (60) is adhered to the adhesive resin layer (30); and (C) a step of, after the step (B), peeling the heat-resistant resin layer (10) from the adhesive laminate film (50).

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Abstract: Electromagnetic shields for sub-modules of electronic modules are disclosed. Electronic modules may include multiple sub-modules arranged on a substrate with an electromagnetic shield arranged to conformally cover the sub-modules as well as portions of the substrate that are uncovered by the sub-modules. Electromagnetic shields are disclosed that are configured to extend between sub-modules to form one or more divider walls. The one or more divider walls may be configured to extend below mounting surfaces of electronic components in the sub-modules to provide improved reduction of electromagnetic interference (EMI) or crosstalk between various sub-modules. Electromagnetic shields are also disclosed that form perimeter sidewalls that extend below mounting surfaces of electronic components of sub-modules to provide improved reduction of EMI from other modules or other external sources.

Abstract: A method includes forming an interposer, which includes a semiconductor substrate, and an interconnect structure over the semiconductor substrate. The method further includes bonding a device die to the interposer, so that a first metal pad in the interposer is bonded to a second metal pad in the device die, and a first surface dielectric layer in the interposer is bonded to a second surface dielectric layer in the device die. The method further includes encapsulating the device die in an encapsulating material, forming conductive features over and electrically coupling to the device die, and removing the semiconductor substrate. A part of the interposer, the device die, and portions of the conductive features in combination form a package.

Abstract: Provided is a plasma dicing method. The plasma dicing method includes: performing plasma etching on a first surface of a substrate exposed between a plurality of membrane structures; forming a passivation layer on a semiconductor wafer to cover the plurality of membrane structures and at least one trench; performing plasma etching on a second surface of the substrate such that a through hole exposing a portion of the plurality of membrane structures and a dicing lane connected to the trench and having a width less than a width of the through hole are formed at the substrate; and removing the passivation layer and singulating the semiconductor wafer into a plurality of devices including a membrane partially exposed by the through hole.

Abstract: The present disclosure provides a photosensitive assembly and formation method thereof, a lens module, and an electronic device. The method for forming the photosensitive assembly includes providing a transparent cover plate; providing a photosensitive chip, including a photosensitive region and a peripheral region surrounding the photosensitive region; bonding the transparent cover plate to the photosensitive chip through a bonding layer, the bonding layer located in the peripheral region of the photosensitive chip, and the transparent cover plate, the bonding layer, and the photosensitive chip enclosing a cavity that accommodates the photosensitive region; and forming a sealing layer to at least cover the sidewall of the bonding layer and the sidewall of the transparent cover plate. According to the present disclosure, a sealing layer is formed on the sidewall of the bonding layer and the sidewall of the transparent cover plate to increase the effect for sealing the cavity.

Abstract: A wafer processing method includes: a wafer providing step of providing a wafer by placing a thermoplastic polymer sheet on an upper surface of a substrate on which the wafer is supported and positioning a back surface of the wafer on an upper surface of the polymer sheet; a sheet thermocompression bonding step of evacuating an enclosing environment in which the wafer is provided through the polymer sheet on the substrate, heating the polymer sheet, and pressing the wafer toward the polymer sheet to pressure-bond the wafer through the polymer sheet to the substrate; and a dividing step of positioning a cutting blade on the front surface of the wafer and cutting the wafer along the division lines to divide the wafer into individual device chips.

Abstract: An antenna structure, a manufacturing method thereof, and a communication device are disclosed. The antenna structure includes a first substrate, a second substrate, a dielectric layer, a plurality of first electrodes and a plurality of second electrodes. The dielectric layer is disposed between the first substrate and the second substrate; the plurality of first electrodes are disposed at intervals on a side of the first substrate adjacent to the dielectric layer; the plurality of second electrodes are disposed at intervals on a side of the second substrate adjacent to the dielectric layer; a side of the first substrate facing the second substrate includes a plurality of first recess portions each including a first concaved surface which is dented into the first substrate; the dielectric layer is at least partly disposed in the plurality of first recess portions.

Abstract: Methods for bonding and de-bonding a thin substrate film to a carrier plate are provided herein. In some embodiments, a method of processing a semiconductor substrate includes applying a polymer layer that is non-adhesive to a carrier plate formed of a dielectric material. A second layer is then applied to the polymer layer. One or more redistribution layers are then formed on the second layer. The second layer is then separated from the carrier plate via at least one of magnetic induction heating, infrared exposure, or electrostatic repulsion.

Abstract: A solar cell comprising an epitaxial sequence of layers of semiconductor material forming a solar cell deposited using an MOCVD reactor; a metal layer disposed on top of the sequence of layers of semiconductor material, the metal layer including a top surface layer composed of gold or silver; a polymer film; depositing a first metallic adhesion layer disposed on the polymer film that has a coefficient of thermal expansion substantially different from that of the top surface layer on one surface of the polymer film; a second metallic adhesion layer deposited over the first metallic adhesion layer and having a different composition from the first metallic adhesion layer and having no chemical elements in common; and the second metallic adhesion layer of the polymer film being permanently bonded to the metal layer of the sequence of layers of semiconductor material by a thermocompressive diffusion bonding technique.

Abstract: A method of manufacturing a semiconductor package that includes: disposing a semiconductor chip on a support board; sealing the semiconductor chips with a sealant to form a sealed body on the support board, thereby forming sealed semiconductor chips; and forming a rewiring layer and bumps on a side where the semiconductor chip is disposed, after the support board is removed from the sealed body The method also includes an individualizing step of cutting the sealed body along regions corresponding to division lines on the support board, to perform individualization in such a manner that the sealed semiconductor chips each have an upper surface and a lower surface larger than the upper surface, with a side wall inclined from the upper surface toward the lower surface; and a step of forming a conductive shield layer on the upper surfaces and the side walls of the plurality of sealed semiconductor chips.

Abstract: A method of manufacturing a semiconductor package includes: bonding a plurality of semiconductor chips to a plurality of mounting regions on a wiring board partitioned by crossing streets; supplying a liquid resin to a front surface side of the wiring board onto which the plurality of semiconductor chips have been bonded, to seal the plurality of semiconductor chips in a collective manner, thereby forming a sealed board; cutting the sealed board along the regions corresponding to the streets, to individualize the sealed chips in such a manner that the sealed chips each have an upper surface and a lower surface larger than the upper surface, with a side surface inclined from the upper surface toward the lower surface; and forming a conductive shield layer on the upper surfaces and the side surfaces of the plurality of sealed chips.

Abstract: A method of manufacturing a package structure is provided with the following steps, providing a first die, a second die and a third die; forming a first redistribution layer located on and electrically coupled to the first die, the second die and the third die; and forming an antenna located on and electrically coupled to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna.

Abstract: In a processing method, a surface protective tape peeling step of peeling a surface protective tape off the top surface of a wafer is performed in a state in which an expanding sheet is expanded while a preliminary expanding step of expanding the expanding sheet is performed after an affixing step is performed. Therefore, the surface protective tape can be peeled off the top surface of the wafer while a tension is applied to the expanding sheet. It is thereby possible to prevent chips from coming into contact with each other and being damaged. When an expanding step is thereafter performed, the expanding sheet is expanded by an amount of expansion which amount is a value larger than an amount of expansion of the expanding sheet in the preliminary expanding step. Thus, sufficient intervals can be formed between the chips, and the chips can be transported smoothly.

Abstract: Methods of forming vias in substrates having at least one damage region extending from a first surface etching the at least one damage region of the substrate to form a via in the substrate, wherein the via extends through the thickness T of the substrate while the first surface of the substrate is masked. The mask is removed from the first surface of the substrate after etching and upon removal of the mask the first surface of the substrate has a surface roughness (Rq) of about less than 1.0 nm.

Abstract: According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor arranged in the front surface of the substrate and having an intrinsic source, and a through substrate via. A first conductive layer lines sidewalls of the through substrate via and extends from the through substrate via onto the front surface of the semiconductor substrate and is electrically coupled with the intrinsic source.

Abstract: A method of manufacturing a semiconductor device includes disposing a peel-off layer on the second surface of the first substrate, wherein the second surface of the first substrate comprises semiconductor integrated circuits, and the peel-off layer does not extend to an outer peripheral portion of the first substrate, bonding a second substrate to the peel-off layer via a bonding layer, attaching a tape onto the first surface of the first substrate, wherein the tape comprises an adhesive agent having an adhesive strength capable of being lowered by UV irradiation, irradiating a portion of the adhesive agent provided at the outer peripheral portion with UV rays directed toward the first surface, and separating the first substrate from the second substrate at the adhesive agent portion and the peel-off layer portion.

Abstract: The present invention is to provide a dicing-tape integrated film for the backside of a semiconductor that is capable of suppressing the increase of the peel strength between the dicing tape and the film for the backside of a flip-chip semiconductor due to heating. The dicing-tape integrated film for the backside of a semiconductor has a dicing tape having a substrate and a pressure-sensitive adhesive layer formed on the substrate and a film for the backside of a flip-chip semiconductor formed on the pressure-sensitive adhesive layer of the dicing tape, in which the difference (?2??1) of the surface free energy ?2 and the surface free energy ?1 is 10 mJ/m2 or more, where ?1 represents the surface free energy of the pressure-sensitive adhesive layer and ?2 represents the surface free energy of the film for the backside of a flip-chip semiconductor.

Abstract: A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The first die, the second die and the third die are molded in a molding compound. The first redistribution layer is disposed on the molding compound and is electrically connected to the first die, the second die and the third die. The antenna is located on the molding compound and electrically connected to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna. The conductive elements are connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound.

Abstract: A chip spacing maintaining apparatus for maintaining the spacing between any adjacent ones of a plurality of chips obtained by dividing a workpiece attached to an expand sheet, the expand sheet being supported at its peripheral portion to an annular frame is provided. The chip spacing maintaining apparatus includes a far-infrared radiation applying unit for applying far-infrared radiation toward the expand sheet expanded in a target area between the outer circumference of the workpiece and the inner circumference of the annular frame, thereby shrinking the expand sheet in the target area, and an air layer forming unit provided adjacent to the far-infrared radiation applying unit, the air layer forming unit having a nozzle hole for discharging a gas toward the workpiece in applying the far-infrared radiation from the far-infrared radiation applying unit toward the expand sheet, thereby forming an air layer above the workpiece.

Abstract: A highly reliable semiconductor device capable of heavy current conduction and high temperature operation has a module structure in which a semiconductor chip and a circuit pattern are electrically connected via a wire. A front surface metal film is formed on a front surface electrode of the chip, and the wire is bonded to the front surface metal film by wire bonding. The chip has a front surface electrode on the front surface of an Si substrate or an SiC substrate, and has a rear surface substrate on the rear surface thereof. The front surface metal film is a Ni film or a Ni alloy film of having a thickness ranging from 3 ?m to 7 ?m. The wire is an Al wire having an increased recrystallizing temperature and improved strength due to controlling the crystal grain sizes before wire bonding to a range of 1 ?m to 20 ?m.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the semiconductor chip; and a second interconnection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip through vias, wherein the side surface of the semiconductor chip has a step portion.

Abstract: The film for back surface of flip-chip semiconductor according to the present invention is a film for back surface of flip-chip semiconductor to be formed on a back surface of a semiconductor element having been flip-chip connected onto an adherend, wherein a tensile storage elastic modulus at 23° C. after thermal curing is 10 GPa or more and not more than 50 GPa. According to the film for back surface of flip-chip semiconductor of the present invention, since it is formed on the back surface of a semiconductor element having been flip-chip connected onto an adherend, it fulfills a function to protect the semiconductor element. In addition, since the film for back surface of flip-chip semiconductor according to the present invention has a tensile storage elastic modulus at 23° C. after thermal curing of 10 GPa or more, a warp of the semiconductor element generated at the time of flip-chip connection of a semiconductor element onto an adherend can be effectively suppressed or prevented.

Abstract: High field-effect mobility is provided for a transistor including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a bottom-gate transistor including an oxide semiconductor layer, an oxide semiconductor layer functioning as a current path (channel) of the transistor is sandwiched between oxide semiconductor layers having lower carrier densities than the oxide semiconductor layer. In such a structure, the channel is formed away from the interface of the oxide semiconductor stacked layer with an insulating layer in contact with the oxide semiconductor stacked layer, i.e., a buried channel is formed.

Abstract: A package substrate machining method is provided. The package substrate includes a ceramic substrate, a plurality of device chips arranged on one face of the ceramic substrate, and a coating layer made of a resin that covers the entire one face of the ceramic substrate. The package substrate machining method includes a first laser-machined groove formation step adapted to form, in the coating layer, first laser-machined grooves along scheduled division lines set up on the package substrate by irradiating a laser beam at a wavelength absorbable by the coating layer from the coating layer side of the package substrate; and a second laser-machined groove formation step adapted to form, in the ceramic substrate and after the first laser-machined groove formation step, second laser-machined grooves along the scheduled division lines by irradiating a laser beam from the ceramic substrate side of the package substrate.