Utilizing A Coating To Perfect The Dicing Patents (Class 438/114)
  • Patent number: 10475676
    Abstract: In a processing method, a surface protective tape peeling step of peeling a surface protective tape off the top surface of a wafer is performed in a state in which an expanding sheet is expanded while a preliminary expanding step of expanding the expanding sheet is performed after an affixing step is performed. Therefore, the surface protective tape can be peeled off the top surface of the wafer while a tension is applied to the expanding sheet. It is thereby possible to prevent chips from coming into contact with each other and being damaged. When an expanding step is thereafter performed, the expanding sheet is expanded by an amount of expansion which amount is a value larger than an amount of expansion of the expanding sheet in the preliminary expanding step. Thus, sufficient intervals can be formed between the chips, and the chips can be transported smoothly.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: November 12, 2019
    Assignee: DISCO CORPORATION
    Inventors: Karl Heinz Priewasser, Akiko Kigawa
  • Patent number: 10410883
    Abstract: Methods of forming vias in substrates having at least one damage region extending from a first surface etching the at least one damage region of the substrate to form a via in the substrate, wherein the via extends through the thickness T of the substrate while the first surface of the substrate is masked. The mask is removed from the first surface of the substrate after etching and upon removal of the mask the first surface of the substrate has a surface roughness (Rq) of about less than 1.0 nm.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: September 10, 2019
    Assignee: Corning Incorporated
    Inventors: Robert Alan Bellman, Shiwen Liu
  • Patent number: 10373868
    Abstract: According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: August 6, 2019
    Assignees: INFINEON TECHNOLOGIES AUSTRIA AG, TECHNISCHE UNIVERSITAET GRAZ
    Inventors: Martin Mischitz, Markus Heinrici, Michael Roesner, Oliver Hellmund, Caterina Travan, Manfred Schneegans, Peter Irsigler, Friedrich Kroener
  • Patent number: 10242932
    Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor arranged in the front surface of the substrate and having an intrinsic source, and a through substrate via. A first conductive layer lines sidewalls of the through substrate via and extends from the through substrate via onto the front surface of the semiconductor substrate and is electrically coupled with the intrinsic source.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech, Matthias Zigldrum
  • Patent number: 10199253
    Abstract: A method of manufacturing a semiconductor device includes disposing a peel-off layer on the second surface of the first substrate, wherein the second surface of the first substrate comprises semiconductor integrated circuits, and the peel-off layer does not extend to an outer peripheral portion of the first substrate, bonding a second substrate to the peel-off layer via a bonding layer, attaching a tape onto the first surface of the first substrate, wherein the tape comprises an adhesive agent having an adhesive strength capable of being lowered by UV irradiation, irradiating a portion of the adhesive agent provided at the outer peripheral portion with UV rays directed toward the first surface, and separating the first substrate from the second substrate at the adhesive agent portion and the peel-off layer portion.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: February 5, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masaya Shima, Kenji Takahashi
  • Patent number: 10141217
    Abstract: The present invention is to provide a dicing-tape integrated film for the backside of a semiconductor that is capable of suppressing the increase of the peel strength between the dicing tape and the film for the backside of a flip-chip semiconductor due to heating. The dicing-tape integrated film for the backside of a semiconductor has a dicing tape having a substrate and a pressure-sensitive adhesive layer formed on the substrate and a film for the backside of a flip-chip semiconductor formed on the pressure-sensitive adhesive layer of the dicing tape, in which the difference (?2??1) of the surface free energy ?2 and the surface free energy ?1 is 10 mJ/m2 or more, where ?1 represents the surface free energy of the pressure-sensitive adhesive layer and ?2 represents the surface free energy of the film for the backside of a flip-chip semiconductor.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: November 27, 2018
    Assignee: NITTO DENKO CORPORATION
    Inventors: Naohide Takamoto, Hiroyuki Hanazono, Akihiro Fukui
  • Patent number: 10032722
    Abstract: A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The first die, the second die and the third die are molded in a molding compound. The first redistribution layer is disposed on the molding compound and is electrically connected to the first die, the second die and the third die. The antenna is located on the molding compound and electrically connected to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna. The conductive elements are connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 9991151
    Abstract: A chip spacing maintaining apparatus for maintaining the spacing between any adjacent ones of a plurality of chips obtained by dividing a workpiece attached to an expand sheet, the expand sheet being supported at its peripheral portion to an annular frame is provided. The chip spacing maintaining apparatus includes a far-infrared radiation applying unit for applying far-infrared radiation toward the expand sheet expanded in a target area between the outer circumference of the workpiece and the inner circumference of the annular frame, thereby shrinking the expand sheet in the target area, and an air layer forming unit provided adjacent to the far-infrared radiation applying unit, the air layer forming unit having a nozzle hole for discharging a gas toward the workpiece in applying the far-infrared radiation from the far-infrared radiation applying unit toward the expand sheet, thereby forming an air layer above the workpiece.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: June 5, 2018
    Assignee: DISCO CORPORATION
    Inventors: Atsushi Hattori, Atsushi Ueki
  • Patent number: 9978701
    Abstract: A highly reliable semiconductor device capable of heavy current conduction and high temperature operation has a module structure in which a semiconductor chip and a circuit pattern are electrically connected via a wire. A front surface metal film is formed on a front surface electrode of the chip, and the wire is bonded to the front surface metal film by wire bonding. The chip has a front surface electrode on the front surface of an Si substrate or an SiC substrate, and has a rear surface substrate on the rear surface thereof. The front surface metal film is a Ni film or a Ni alloy film of having a thickness ranging from 3 ?m to 7 ?m. The wire is an Al wire having an increased recrystallizing temperature and improved strength due to controlling the crystal grain sizes before wire bonding to a range of 1 ?m to 20 ?m.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: May 22, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Saito, Fumihiko Momose, Kazumasa Kido, Yoshitaka Nishimura
  • Patent number: 9929102
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the semiconductor chip; and a second interconnection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip through vias, wherein the side surface of the semiconductor chip has a step portion.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: March 27, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Jin Lee, Dong Hun Lee
  • Patent number: 9911683
    Abstract: The film for back surface of flip-chip semiconductor according to the present invention is a film for back surface of flip-chip semiconductor to be formed on a back surface of a semiconductor element having been flip-chip connected onto an adherend, wherein a tensile storage elastic modulus at 23° C. after thermal curing is 10 GPa or more and not more than 50 GPa. According to the film for back surface of flip-chip semiconductor of the present invention, since it is formed on the back surface of a semiconductor element having been flip-chip connected onto an adherend, it fulfills a function to protect the semiconductor element. In addition, since the film for back surface of flip-chip semiconductor according to the present invention has a tensile storage elastic modulus at 23° C. after thermal curing of 10 GPa or more, a warp of the semiconductor element generated at the time of flip-chip connection of a semiconductor element onto an adherend can be effectively suppressed or prevented.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: March 6, 2018
    Assignee: NITTO DENKO CORPORATION
    Inventors: Naohide Takamoto, Goji Shiga
  • Patent number: 9847430
    Abstract: High field-effect mobility is provided for a transistor including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a bottom-gate transistor including an oxide semiconductor layer, an oxide semiconductor layer functioning as a current path (channel) of the transistor is sandwiched between oxide semiconductor layers having lower carrier densities than the oxide semiconductor layer. In such a structure, the channel is formed away from the interface of the oxide semiconductor stacked layer with an insulating layer in contact with the oxide semiconductor stacked layer, i.e., a buried channel is formed.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: December 19, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9831381
    Abstract: A package substrate machining method is provided. The package substrate includes a ceramic substrate, a plurality of device chips arranged on one face of the ceramic substrate, and a coating layer made of a resin that covers the entire one face of the ceramic substrate. The package substrate machining method includes a first laser-machined groove formation step adapted to form, in the coating layer, first laser-machined grooves along scheduled division lines set up on the package substrate by irradiating a laser beam at a wavelength absorbable by the coating layer from the coating layer side of the package substrate; and a second laser-machined groove formation step adapted to form, in the ceramic substrate and after the first laser-machined groove formation step, second laser-machined grooves along the scheduled division lines by irradiating a laser beam from the ceramic substrate side of the package substrate.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 28, 2017
    Assignee: Disco Corporation
    Inventor: Yuta Yoshida
  • Patent number: 9666437
    Abstract: A method for manufacturing a semiconductor device including a semiconductor chip having a front surface electrode and a rear surface electrode provided on a front surface and a rear surface, respectively, the method includes a front surface electrode layer forming step of forming a front surface electrode layer as the front surface electrode on a front surface of a semiconductor wafer forming the semiconductor chip; a thinning step of grinding a rear surface of the semiconductor wafer to reduce a thickness of the semiconductor wafer after the front surface electrode layer forming step; a plating step of forming an electrode plating film as the front surface electrode on a surface of the front surface electrode layer after the thinning step; and a rear surface electrode forming step of forming the rear surface electrode on the ground rear surface of the semiconductor wafer after the plating step.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: May 30, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi Urano
  • Patent number: 9630837
    Abstract: A structure and a fabrication method thereof are provided. The method includes the following operations. A device substrate having a first surface and a second surface opposite to each other is received. A carrier substrate having a third surface and a fourth surface opposite to each other is received. An intermediate layer is formed between the third surface of the carrier substrate and the second surface of the device substrate. The second surface of the device substrate is attached to the third surface of the carrier substrate. The device substrate is thinned from the first surface. A device is formed over the first surface of the device substrate. The carrier substrate and the device substrate are patterned from the fourth surface to form a cavity in the carrier substrate, the intermediate layer and the device substrate.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 9609793
    Abstract: A electromagnetic shielding film includes a conductive supporting substrate which includes a cured material of a thermosetting resin including a conductive filler; a metal thin film layer which covers one surface of the conductive supporting substrate; a thermosetting adhesive layer which covers a surface of the metal thin film layer; and a peeling substrate which covers the other surface of the conductive supporting substrate.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: March 28, 2017
    Assignee: SHIN-ETSU POLYMER CO., LTD.
    Inventor: Toshiyuki Kawaguchi
  • Patent number: 9583391
    Abstract: There is provided a wafer processing method including a modified layer forming step. In the wafer processing method, the power of a pulse laser beam set in the modified layer forming step is set to a power that forms modified layers and cracks in such a manner that a wafer is allowed to be divided into individual device chips before the thickness of the wafer reaches a finished thickness and, after the wafer is divided into the individual device chips, the time until the thickness of the wafer reaches the finished thickness is such a time that damage due to rubbing of the individual device chips against each other is not caused through grinding under a predetermined grinding condition set in a back surface grinding step.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: February 28, 2017
    Assignee: Disco Corporation
    Inventor: Masaru Nakamura
  • Patent number: 9515237
    Abstract: A method for producing a light emitting device includes a first bonding step including disposing a first bonding member a mounting substrate, placing a light emitting element on the mounting substrate such that the first bonding member is located between a mounting face of the light emitting element and the mounting substrate, and hardening the first bonding member thereby bonding the light emitting element and the mounting substrate such that, in a plan view, an entirety of the first bonding member is contained within an area of the mounting face of the light emitting element; and a second bonding step including disposing a second bonding member on the upper face of the mounting substrate such that, in a plan view, the second bonding member is located at at least a portion of an outer edge of the mounting face of the light emitting element, and hardening the second bonding member.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: December 6, 2016
    Assignee: NICHIA CORPORATION
    Inventor: Hideaki Takeda
  • Patent number: 9408311
    Abstract: A method of manufacturing an electronic component module includes sealing a surface of an aggregate substrate on which a plurality of electronic components are mounted with a sealing resin and cutting boundary portions between electronic component modules from an outer surface of the sealing resin to a position at least partially through the aggregate substrate to form first grooves. A shield layer is formed by coating the outer surface of the sealing resin with a conductive resin and filling the first grooves with the conductive resin, and recesses are formed at positions on the shield layer where the first grooves are formed. The boundary portions between electronic component modules are cut along the corresponding recesses so that second grooves each having a width smaller than the width of a corresponding one of the recesses are formed, and the aggregate substrate is singulated into the individual electronic component modules.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: August 2, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koichi Kanryo, Akio Katsube, Shunsuke Kitamura
  • Patent number: 9368456
    Abstract: A semiconductor package includes a dielectric layer in which a chip is embedded, interconnection parts disposed on a first surface of the dielectric layer, through connectors each of which penetrates a portion of the dielectric layer over the chip to electrically couple the chip to a corresponding one of the interconnection parts, a shielding plate covering a second surface of the dielectric layer that is opposite to the first surface, and a shielding encapsulation part connected to one of the interconnection parts and covering sidewalls of the dielectric layer. The shielding encapsulation part includes a portion contacting the shielding plate.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: June 14, 2016
    Assignee: SK HYNIX INC.
    Inventor: Qwan Ho Chung
  • Patent number: 9299592
    Abstract: A package structure and a packaging method of wafer level chip scale package are provided. The packaging method includes: providing a carrier, and disposing a plurality of chips on the carrier; forming a plurality of adhesive layers on a surface of the corresponding chips; covering a conductive cover plate, bonding the conductive cover plate with the chips through the adhesive layers, and dividing out a plurality of packaging spaces by the conductive cover plate for disposing the chips respectively; and providing an insulation material to fill the packaging spaces through via holes on the conductive cover plate to form a first insulation structure; finally, removing the carrier.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: March 29, 2016
    Assignees: NIKO SEMICONDUCTOR CO., LTD., Super Group Semiconductor Co. LTD.
    Inventors: Chih-Cheng Hsieh, Hsiu-Wen Hsu, Chun-Ying Yeh, Chung-Ming Leng
  • Patent number: 9236429
    Abstract: A semiconductor structure includes a substrate, a dam element, a first isolation layer, a second isolation layer, and a conductive layer. The substrate has a conductive pad, a trench, a sidewall, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the second surface. The trench has a first opening at the first surface, and has a second opening at the second surface. The dam element is located on the second surface and covers the second opening. The dam element has a concave portion that is at the second opening. The first isolation layer is located on a portion of the sidewall. The second isolation layer is located on the first surface and the sidewall that is not covered by the first isolation layer, such that an interface is formed between the first and second isolation layers.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: January 12, 2016
    Assignee: XINTEC INC.
    Inventors: Yu-Lin Yen, Sheng-Hao Chiang, Hung-Chang Chen, Ho-Ku Lan, Chen-Mei Fan
  • Patent number: 9196534
    Abstract: A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices.
    Type: Grant
    Filed: February 24, 2013
    Date of Patent: November 24, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yan Xun Xue, Ping Huang, Hamza Yilmaz, Yueh-Se Ho, Lei Shi, Liang Zhao, Ping Li Wu, Lei Duan, Yuping Gong
  • Patent number: 9177919
    Abstract: A chip package including a first substrate having a first surface and a second surface opposite thereto is provided. The first substrate has a micro-electric element and a plurality of conducting pads adjacent to the first surface. The first substrate has a plurality of openings respectively exposing a portion of each conducting pad. A second substrate is disposed on the first surface. An encapsulation layer is disposed on the first surface and covers the second substrate. A redistribution layer is disposed on the second surface and extends into the openings to electrically connect the conducting pads.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: November 3, 2015
    Assignee: XINTEC INC.
    Inventors: Chien-Hung Liu, Ying-Nan Wen
  • Patent number: 9165895
    Abstract: A method for separating a plurality of dies is provided.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: October 20, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Helmut Brunner, Manfred Engelhardt
  • Patent number: 9153566
    Abstract: A semiconductor device manufacturing method includes forming grooves in a surface of a semiconductor substrate, stacking a plurality of semiconductor chips in each area of the semiconductor substrate surrounded by the grooves to form stacked bodies, forming a first sealing resin layer that covers spaces between the plurality of semiconductor chips and lateral sides of the stacked bodies, separating the semiconductor substrate to singulate the stacked bodies, mounting the stacked bodies on a wiring substrate, forming a second sealing resin layer that seals the stacked bodies on the wiring substrate, separating the wiring substrate to singulate a portion of the wiring substrate with a single stacked body thereon, and grinding a portion of the semiconductor substrate in a thickness direction from a side of the semiconductor substrate opposite to the stacked bodies, after forming the first sealing resin layer and before singulating the wiring substrate.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takao Sato
  • Patent number: 9142457
    Abstract: The present invention provides a dicing die bond film in which yielding and breaking of the dicing film are prevented and in which the die bond film can be suitably broken with a tensile force. In the dicing die bond film of the present invention, the tensile strength of the contact part in which the outer circumference of the push-up jig contacts the dicing film at 25° C. is 15 N or more and 80 N or less and the yield point elongation is 80% or more, the tensile strength of the wafer bonding part of the dicing film at 25° C. is 10 N or more and 70 N or less and the yield point elongation is 30% or more, [(the tensile strength of the contact part)?(the tensile strength of the wafer bonding part)] is 0 N or more and 60 N or less, and the breaking elongation rate of the die bond film at 25° C. is more than 40% and 500% or less.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: September 22, 2015
    Assignee: NITTO DENKO CORPORATION
    Inventors: Shumpei Tanaka, Takeshi Matsumura
  • Patent number: 9130056
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof involves laminating a pre-patterned bi-layer wafer-level underfill material stack on the integrated circuits of the semiconductor wafer. The pre-patterned bi-layer wafer-level underfill material stack has regions corresponding to the integrated circuits and gaps corresponding to dicing streets between the integrated circuits. The method also involves plasma etching to form trenches in the semiconductor wafer in alignment with the dicing streets to singulate the integrated circuits. An upper layer of the pre-patterned bi-layer wafer-level underfill material stack protects the integrated circuits during the plasma etching.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: September 8, 2015
    Assignee: Applied Materials, Inc.
    Inventors: James M. Holden, James S. Papanu, Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Patent number: 9087764
    Abstract: A method and structure for forming an array of micro devices is disclosed. An array of micro devices is formed over an array of stabilization posts included in a stabilization layer. The stabilization layer is bonded to a spacer side of a carrier substrate. The spacer side of the carrier substrate includes raised spacers extending from a spacer-side surface of the carrier substrate.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: July 21, 2015
    Assignee: Luxvue Technology Corporation
    Inventors: Clayton Ka Tsun Chan, Andreas Bibl
  • Patent number: 9076882
    Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Ravindranath V Mahajan, Omkar Karhade, Nitin Deshpande
  • Patent number: 9041198
    Abstract: Maskless hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface with a plurality of integrated circuits thereon and having a passivation layer disposed between and covering metal pillar/solder bump pairs of the integrated circuits involves laser scribing, without the use of a mask layer, the passivation layer to provide scribe lines exposing the semiconductor wafer. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the passivation layer protects the integrated circuits during at least a portion of the plasma etching. The method also involves thinning the passivation layer to partially expose the metal pillar/solder bump pairs of the integrated circuits.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: May 26, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, James S. Papanu, Ajay Kumar
  • Publication number: 20150125997
    Abstract: A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure.
    Type: Application
    Filed: November 7, 2013
    Publication date: May 7, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Ping Wang, Ming-Kai Liu, Kai-Chiang Wu
  • Publication number: 20150118797
    Abstract: A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through a top portion of the molding compound using a first beveled saw blade, while leaving a bottom portion of the molding compound remaining. The method further includes sawing through the bottom portion of the molding compound and the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the first saw blade. The resulting structure is within the scope of the present disclosure.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 30, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Kai Liu, Yen-Ping Wang, Kai-Chiang Wu
  • Patent number: 9012304
    Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: April 21, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, John M. Parsey, Jr.
  • Patent number: 9006004
    Abstract: A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Szu Wei Lu
  • Patent number: 8999816
    Abstract: Approaches for protecting a wafer during plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer with a front surface having a plurality of integrated circuits thereon involves laminating a pre-patterned mask on the front surface of the semiconductor wafer. The pre-patterned mask covers the integrated circuits and exposes streets between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the streets to singulate the integrated circuits. The pre-patterned mask protects the integrated circuits during the plasma etching.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: April 7, 2015
    Assignee: Applied Materials, Inc.
    Inventors: James M. Holden, Aparna Iyer, Brad Eaton, Ajay Kumar
  • Patent number: 9000434
    Abstract: A semiconductor device including a semiconductor substrate having a surface including an active semiconductor device including one of a laser and a photodiode; and a visual indicator disposed on the semiconductor body and at least adjacent to a portion of said active semiconductor device, the indicator having a state that shows if damage to the active semiconductor device may have occurred.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: April 7, 2015
    Assignee: Emcore Corporation
    Inventors: Richard Carson, Elaine Taylor, Douglas Collins
  • Patent number: 8987058
    Abstract: A plurality of macro and micro alignment marks may be formed on a wafer. The macro alignment marks may be formed in pairs at opposite edges of the wafer. The micro alignment marks may be formed to align to streets on the wafer along a first and second direction. A molding compound may be formed on the wafer. The macro alignment marks may be exposed from the molding compound. A pair of the micro alignment marks may be exposed from the molding compound at opposite ends of the streets along the first and the second direction. The wafer may be aligned to a dicing tool using pairs of the macro alignment marks. The dicing tool may be aligned to the streets using pairs of the micro alignment marks. The wafer may be diced using successive pairs of micro alignment marks along the first and second direction.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Peng Tsai, Wen-Hsiung Lu, Cheng-Ting Chen, Hsien-Wei Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 8980673
    Abstract: Provided are a solar cell and a method of manufacturing the same. The method of manufacturing the solar cell includes stacking a solar cell device layer containing GaN on a sacrificial substrate, etching the solar cell device layer to expose the sacrificial substrate, thereby forming one or more solar cell devices comprising the solar cell device layer, anisotropically etching the exposed sacrificial substrate, contacting the solar cell devices to a stamping processor to remove the solar cell devices from the sacrificial substrate, and transferring the solar cell devices onto a receiving substrate. A high temperature semiconductor process may be performed on a substrate such as a silicon substrate to transfer the solar cell devices onto the substrate, thereby manufacturing flexible solar cells. Also, a large number of solar cells may be excellently aligned on a large area. In addition, economical solar cells may be manufactured.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: March 17, 2015
    Assignees: LG Siltron Incorporated, Korea Advanced Institute of Science
    Inventors: Keon Jae Lee, Sang Yong Lee, Seung Jun Kim
  • Patent number: 8962452
    Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 8956917
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: (a) forming cutting grooves in an element formation surface of a semiconductor wafer on which semiconductor elements are formed; (b) applying a protection tape on the element formation surface of the semiconductor wafer; (c) grinding a rear surface of the semiconductor wafer to thin the semiconductor wafer and to divide the semiconductor wafer into a plurality of semiconductor chips on which the semiconductor elements are formed; (d) forming an adhesive layer on the rear surface of the semiconductor wafer; (e) separating and cutting the adhesive layer for each of the semiconductor chips; and (f) removing the protection tape. The (e) is performed by spraying a high-pressure air to the adhesive layer formed on the rear surface of the semiconductor wafer while melting or softening the adhesive layer by heating.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Kurosawa, Shinya Takyu, Akira Tomono
  • Patent number: 8951843
    Abstract: The present invention provides a laminated sheet that can prevent the decrease in adhering strength of a resin composition layer and the deterioration in electrical reliability and in which a back grinding tape can be peeled from a plurality of semiconductor elements collectively after dicing. The laminated sheet has a back grinding tape in which a pressure-sensitive adhesive layer is formed on a base, and a resin composition layer that is provided on the pressure-sensitive adhesive layer of the back grinding tape, wherein the tensile modulus of the pressure-sensitive adhesive layer at 23° C. is 0.1 to 5.0 MPa, and the T-peeling strength between the pressure-sensitive adhesive layer and the resin composition layer is 0.1 to 5 N/20 mm at 23° C. and 300 mm/min.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: February 10, 2015
    Assignee: Nitto Denko Corporation
    Inventors: Hiroyuki Senzai, Shumpei Tanaka, Koji Mizuno
  • Publication number: 20150035133
    Abstract: A method is described for making electronic modules includes molding onto a substrate panel a matrix panel defining a plurality of cavities, attaching semiconductor die to the substrate panel in respective cavities of the molded matrix panel, electrically connecting the semiconductor die to the substrate panel, affixing a cover to the molded matrix panel to form an electronic module assembly, mounting the electronic module assembly on a carrier tape, and separating the electronic module assembly into individual electronic modules. An electronic module is described which includes a substrate, a wall member molded onto the substrate, the molded wall member defining a cavity, at least one semiconductor die attached to the substrate in the cavity and electrically connected to the substrate, and a cover affixed to the molded wall member over the cavity.
    Type: Application
    Filed: August 2, 2013
    Publication date: February 5, 2015
    Applicant: STMicroelectronics Pte Ltd.
    Inventor: Wing Shenq Wong
  • Patent number: 8936970
    Abstract: A light-emitting structure comprises a semiconductor light-emitting element which includes a first connection point and a second connection point. The light-emitting structure further includes a first electrode electrically connected to the first connection point, and a second electrode electrically connected the second connection point. The first electrode and the second electrode can form a concave on which the semiconductor light-emitting element is located.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: January 20, 2015
    Assignee: Epistar Corporation
    Inventor: Chia-Liang Hsu
  • Patent number: 8916420
    Abstract: An embodiment provides a chip package including a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and the protective layer covering the chip.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: December 23, 2014
    Inventors: Baw-Ching Perng, Chun-Lung Huang
  • Patent number: 8916453
    Abstract: A semiconductor wafer includes a first main face and a second main face opposite to the first main face and a number of semiconductor chip regions. The wafer is diced along dicing streets to separate the semiconductor chip regions from each other. At least one metal layer is formed on the first main face of each one of the semiconductor chip regions.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: December 23, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gopalakrishnan Trichy Rengarajan, Armin Tilke
  • Patent number: 8912669
    Abstract: Provided are a sealing resin sheet, wherein a clean, smooth and flat ground surface is obtained by grinding after resin sealing, a method for producing an electronic component package using the same, and an electronic component package obtained by the production method. The present invention provides a sealing resin sheet, wherein a ground surface has a mean surface roughness Ra of 1 ?m or less when grinding is performed under conditions of a grind bite peripheral velocity of 1000 m/minute, a feed pitch of 100 ?m and a cut depth of 10 ?m after a heat curing treatment is performed at 180° C. for 1 hour; and a Shore D hardness at 100° C. after the heat curing treatment is 70 or more.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: December 16, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Eiji Toyoda, Yusaku Shimizu
  • Patent number: 8906743
    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: December 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Chan Yoo, Todd O. Bolken
  • Patent number: 8906745
    Abstract: A method of dividing a semiconductor wafer in which a sheet of deformable material engaging the metal layer side of the wafer has pressurized fluid applied thereto to cause the metal layer to break at the locations of wafer scribe streets.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: December 9, 2014
    Assignee: Micro Processing Technology, Inc.
    Inventors: Paul C. Lindsey, Jr., Darrell Foote
  • Patent number: 8900925
    Abstract: In a method for manufacturing a diode, a semiconductor crystal wafer is used to produce a p-n or n-p junction, which extends in planar fashion across the top side of a semiconductor crystal wafer. Separation edges form perpendicularly to the top side of the semiconductor crystal wafer, which edges extend across the p-n or n-p junction. The separation of the semiconductor crystal wafer is achieved in that, starting from a disturbance, a fissure is propagated by local heating and local cooling of the semiconductor crystal wafer. The separation fissure thus formed extends along crystal planes of the semiconductor crystal, which avoids the formation of defects in the area of the p-n or n-p junction.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: December 2, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Alfred Goerlach, Robert Kolb