Abstract: A solid-state imaging device comprises a housing in which a base and ribs forming a rectangular frame are formed in one piece by a resin; a plurality of metal lead pieces embedded in the housing, each of which has an internal terminal portion facing an internal space of the housing and an external terminal portion exposed at an outer portion of the housing; an imaging element arranged on the base in the internal space of the housing; connecting members connecting electrodes of the imaging element to the internal terminal portions of the metal lead pieces; and a transparent plate fastened to an upper face of the ribs. The upper face of the ribs is provided with a lower step portion that is lowered along an external periphery, and the transparent plate is fastened to the upper face of the ribs by an adhesive filled at least into the lower step portion.

Abstract: This application relates to a method of manufacturing a semiconductor device comprising: providing multiple chips each comprising contact elements on a first main face of each of the multiple chips, and a first layer applied to each of the first main faces of the multiple chips; placing the multiple chips over a carrier with the first layers facing the carrier; applying encapsulation material to the multiple chips and the carrier to form an encapsulation workpiece embedding the multiple chips; and removing the carrier from the encapsulation workpiece.

Abstract: A method of producing semiconductor devices. One embodiment provides producing at least two semiconductor chips. An encapsulation material is applied to the at least two semiconductor chips to form an encapsulation layer. The at least two semiconductor chips are separated from each other to obtain at least two separated semiconductor devices. The outline of each one of the semiconductor devices includes three corners in total or more than four corners.

Abstract: A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate.

Abstract: A wafer processing method for dividing a wafer having function elements in area sectioned by dividing lines formed on the front surface in a lattice pattern into individual chips along the dividing lines, comprising a deteriorated layer forming step for forming a deteriorated layer on the side of the back surface of a position at a distance corresponding to the final thickness of the chip from the front surface of the wafer by applying a laser beam capable of passing through the wafer along the dividing lines from the back surface of the wafer; a dividing step for dividing the wafer into individual chips along the dividing lines by applying external force to the wafer in which the deteriorated layer has been formed along the dividing lines; and a back surface grinding step for grinding the back surface of the wafer divided into individual chips to the final thickness of the chip.

Abstract: A semiconductor spacer structure comprises in order a backgrinding tape layer, a spacer adhesive layer, a semiconductor spacer layer, an optional second spacer adhesive layer, a dicing tape layer. In a first method a spacer wafer having first and second sides, a backgrinding tape layer and a spacer adhesive layer between the first side and the backgrinding tape layer, is obtained. The second side is background and secured to a dicing tape. The backgrinding tape is removed and the resulting structure is diced to create spacer/adhesive die structures. A second method backgrinds the second side with the backgrinding tape layer at the first side. A protective cover layer is secured to the second side with a spacer adhesive layer therebetween. The backgrinding tape layer is removed and the remaining structure is secured to a dicing tape with the protective cover layer exposed. The protective cover layer is removed and the resulting structure is diced thereby creating spacer/adhesive die structures.

Abstract: The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.

Abstract: A chip scale package (CSP) structure and the packaging process thereof are described. By using a matrix of interlinked heat sink units compatible with the block substrate, the packaging process can be simplified and a plurality of packages units or chip scale packages with enhanced thermal performance can be obtained after singulation.

Abstract: When a thin semiconductor device is formed by grinding a wafer, it has been necessary to dice the wafer into dies and process the back surfaces of the dies separately. In the invention, a wafer 2a is half-diced from the front surface thereof to form groove portions 4 therein, and in this state, the front surface of the wafer 2a is attached to a supporting body 5 having rigidity with an adhesive layer 6. Then, the wafer 2a is ground from the back surface and diced into individual dies 2b, and then a back surface process including a heat treatment such as the formation of back surface electrodes 9a is performed in the state where the dies 2b are attached to the supporting body 5.

Abstract: A semiconductor device is made by creating a gap between semiconductor die on a wafer. An insulating material is deposited in the gap. A first portion of the insulating material is removed from a first side of the semiconductor wafer to form a first notch. The first notch is less than a thickness of the semiconductor die. A conductive material is deposited into the first notch to form a first portion of the conductive via within the gap. A second portion of the insulating material is removed from a second side of the semiconductor wafer to form a second notch. The second notch extends through the insulating material to the first notch. A conductive material is deposited into the second notch to form a second portion of the conductive via within the gap. The semiconductor wafer is singulated through the gap to separate the semiconductor die.

Abstract: A method of manufacturing a semiconductor device is disclosed, which includes at least the steps of preparing a laminated structure including a single chip or a plurality of chips, and dividing the laminated structure into a plurality of sub-laminated structures. A laminated structure comprised of a silicon substrate and a single chip or a plurality of chips laminated on the silicon substrate is formed. Then, the laminated structure is divided into a plurality of sub-laminated structures. Each of the sub-laminated structures includes a semiconductor device.

Abstract: A separating device for separating a semiconductor substrate includes: a cutting element for cutting the semiconductor substrate into a plurality of chips along with a cutting line on the semiconductor substrate; an adsorbing element for adsorbing a dust on a surface of the semiconductor substrate by using electrostatic force; and a static electricity generating element for generating static electricity and for controlling the static electricity in order to remove the dust from the adsorbing element.

Abstract: A glass substrate is bonded through a resin to the top surface of a semiconductor wafer on which a first wiring is formed. A V-shaped groove is formed by notching from the back surface of the wafer. A second wiring connected with the first wiring and extending over the back surface of the wafer is formed. A protection film composed of an organic resin or a photoresist layer to provide protection with an opening is formed on the second wiring by spray coating. A conductive terminal is formed by screen printing using the protection film as a solder mask. A cushioning material may be formed on the back surface of the wafer by spray coating.

Abstract: In a method for cutting a solid-state image pickup device of the present invention, a glass cover plate is diced with a surface thereof being protected, so that chipping of the glass cover plate can be significantly prevented. In addition, since a CCD wafer is adhered after the glass cover plate is diced, no glass fragments scattered due to chipping of the glass cover plate touch the CCD wafer, or cause damage to the CCD wafer, thereby a cutting of solid-state image pickup device can be achieved with high accuracy and high quality.

Abstract: A method (32) of packaging integrated circuit (IC) dies (48) includes applying (36) a laminating material (44) to a wafer (40), and separating (46) the wafer (40) into multiple IC dies (48) such that the laminating material (44) is applied to back surfaces (52) of the IC dies (48). Each of the IC dies (48) is positioned (62) with an active surface (50) facing a support substrate (56). An encapsulant layer (72) is formed (64) overlying the laminating material (44) and the back surfaces (52) of the IC dies (48) from a molding compound (66). The molding compound (66) and the laminating material (44) are removed from the back surfaces (52) of the IC dies (48) to form (76) openings (78) exposing the back surfaces (52). Conductive material (84, 88) is placed in the openings (78) and functions as a heat sink and/or a ground for the IC dies (48).

Abstract: A chip-scale or wafer-level-package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed-package, is provided. The package may be formed by disposing a first passivation layer on the passive or backside surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.

Abstract: In this manufacturing method of a semiconductor device, after a sealing film is applied over an entire surface of a semiconductor wafer and hardened, a second groove for forming a side-section protective film is formed in the sealing film and on the top surface side of the semiconductor wafer. In other words, the sealing film is formed in a state where a groove that causes strength reduction has not been formed on the top surface side of the semiconductor wafer. Since the second groove is formed on the top surface side of the semiconductor wafer after the sealing film is formed, the semiconductor wafer is less likely to warp when the sealing film, made of liquid resin, is hardened.

Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

Abstract: A method for producing many semiconductor chips, each having a semiconductor circuit disposed on the face thereof and a die bonding film stuck to the back thereof, from a semiconductor wafer in which many rectangular regions are defined on its face by streets arranged in a lattice pattern, and the semiconductor circuit is disposed in each of the rectangular regions.

Abstract: The present invention relates to a coating composition for insulating film production, a preparation method of a low dielectric insulating film using the same, a low dielectric insulating film for a semiconductor device prepared therefrom, and a semiconductor device comprising the same, and more particularly to a coating composition for insulating film production having a low dielectric constant and that is capable of producing an insulating film with superior mechanical strength (elasticity), a preparation method of a low dielectric insulating film using the same, a low dielectric insulating film for a semiconductor device prepared therefrom, and a semiconductor device comprising the same. The coating composition of the present invention comprises an organic siloxane resin having a small molecular weight, and water, and significantly improves low dielectricity and mechanical strength of an insulating film.

Abstract: An element is formed on the major surface of a semiconductor wafer, and a groove is formed in the back surface of the semiconductor wafer along a dicing line or chip dividing line by a mechanical or chemical method. A modified layer is formed by irradiating the groove with a laser, and the semiconductor wafer is divided by using the modified layer as a starting point. The back surface of the semiconductor wafer is removed to at least the depth of the groove.

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole and a contact conductive via formed therein, a die disposed within the die receiving through hole, a surrounding material filled in the gap except the die area of the die receiving though hole, a re-distribution layer formed on the substrate and coupled to the contact conductive via, a protection layer formed over the re-distribution layer, a cover material formed over the protection layer; and a terminal contact pad formed on the lower surface of the substrate and under the contact conductive via and the die to couple the contact conductive via.

Abstract: A method for manufacturing a semiconductor device is disclosed. As a part of the method, one surface of a substrate is molded with resin where the substrate and the resin are heated in a first heating process and maintained in a flat condition. The substrate and the resin are returned to room temperature while being maintained in the flat condition after the first heating process. The resin is cut after the substrate and the resin are returned to room temperature from a surface of the resin that is opposite the surface of the resin where the substrate contacts the resin. The substrate is left intact when the resin is cut. Thereafter, the substrate is separated.

Abstract: A method of fabricating a semiconductor chip package, in which a protection layer is formed on a scribe lane of a wafer including a plurality of semiconductor chips, an encapsulation layer is formed on the semiconductor chips and the protection layer, and at least two types of lasers having different respective wavelengths are sequentially irradiated to the scribe lane so as to separate the semiconductor chips. Therefore, the wafer can be protected from the laser that is used to saw the encapsulation layer.

Abstract: A shielded semiconductor device is made by embedding a ground shield between layers of a substrate. Semiconductor die are mounted to the substrate over the ground shields. An encapsulant is formed over the semiconductor die and substrate. The encapsulant is diced to form dicing channels between the semiconductor die. A plurality of openings is drilled into the substrate along the dicing channels down through the ground shield on each side of the semiconductor die. A top shield is formed over the semiconductor die. The openings in the substrate are filled with a shielding material to electrically and mechanically connect the top shield to the ground shield. The substrate is singulated to separate the semiconductor die with top shield and ground shield into individual semiconductor devices. IPDs in the semiconductor die generate electromagnetic interference which is blocked by the respective top shield and ground shield.

Abstract: The present invention discloses a method for fabricating semiconductor elements, which comprises steps: providing a substrate having a wiring pattern on the upper surface thereon electrically connecting a wafer to the substrate for signal input and output; filling a resin into between the wafer and tire substrate to fix the wafer to the substrate; and singulating the combination of the wafer and the substrate into a plurality of semiconductor elements. Therefore, the present can simplify the fabrication process or semiconductor elements.

Abstract: A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.

Abstract: Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.

Abstract: A liquid resin composition for use as a sealing resin which reduces wear on a dicing blade or grinder employed for signularization or grinding. The liquid resin composition includes hollow and/or porous particles as a filler, and is adapted in use to be applied on a substrate constituting a semi-conductor device or electronic part.

Abstract: A manufacturing method of manufacturing an electronic device, includes the steps of: applying a thermosetting adhesive on a surface of a base having a conductive pattern formed on a film; mounting a circuit chip on the base through the thermosetting adhesive; holding the base while pressing a circuit chip side of the base and a film side of the base by a heating apparatus that heats the thermosetting adhesive; giving a tension to the base on which the circuit chip is mounted; and heating the thermosetting adhesive by the heating apparatus to cure the thermosetting adhesive, thereby fixing the circuit chip to the conductive pattern.

Abstract: A laser processing method is provided, which, when cutting a substrate formed with a laminate part including a plurality of functional devices into a plurality of chips, each chip including at least one of the functional devices, can cut the laminate part with a high precision together with the substrate. In this laser processing method, modified regions differing from each other in terms of easiness to cause the substrate 4 to fracture are formed along respective lines to cut 5a to 5d. Therefore, when an expandable tape is attached to the rear face of a substrate 4 and expanded, an object to be processed 1 is cut stepwise into a plurality of chips. Such stepwise cutting allows uniform tensile stresses to act on respective parts extending along the lines to cut 5a to 5d, whereby interlayer insulating films on the lines to cut 5a to 5d are cut with a high precision together with the substrate 4.

Abstract: A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive.

Abstract: A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced.

Abstract: A cutting mold for removing two opposite superfluous rigid circuit boards from a rigid-flexible circuit board. A first cutter is connected to a first moldboard. A first barricade is connected to the first moldboard. The maximum vertical distance from the first barricade to the first moldboard exceeds that from the first cutter to the first moldboard. A second moldboard is opposite the first moldboard. The first and second moldboards move with respect to each other. A second cutter is connected to the second moldboard and corresponds to the first cutter. A second barricade is connected to the second moldboard and detachably abuts the first barricade. The maximum vertical distance from the second barricade to the second moldboard exceeds that from the second cutter to the second moldboard. The first and second cutters cut the superfluous rigid circuit boards when the first and second moldboards move toward each other.

Abstract: One aspect includes an electronic device including an integrated component with a substrate. An electrically conductive first layer region is arranged at the substrate, wherein the layer thickness of the first layer region is greater than 10 micrometers or greater than 50 micrometers.

Abstract: A method of dividing an adhesive film for die bonding which is bonded to the rear surface of a wafer having devices in a plurality of areas sectioned by dividing lines formed in a lattice pattern on the front surface, into pieces corresponding to the devices, comprising the steps of putting the adhesive film side of the wafer on the front surface of a dicing tape mounted on an annular frame; cutting the wafer whose adhesive film side has been put on the dicing tape into devices along the dividing lines and cutting the adhesive film incompletely in such a way that an uncut portion is caused to remain; and expanding the dicing tape after the cutting step to divide the adhesive film into pieces corresponding to the devices.

Abstract: In a die bonding method, a bonding film is stuck to a rear surface of a wafer and to a dicing tape stuck to a dicing frame. The wafer is thus supported by the dicing frame. Predetermined dividing lines are completely cut and the bonding film is incompletely cut to leave a cut-residual portion. The dicing tape is stretched to break the cut-remaining portion. The die to which the bonding film is stuck is picked up from the dicing tape and bonded to a mount-targeted substrate.

Abstract: In a method of manufacturing semiconductor chips by dicing individual semiconductor devices from a semiconductor wafer, masks formed for plasma dicing in which a semiconductor wafer is divided by conducting plasma etching are removed by mechanical grinding using a grinding head. Accordingly, by removing the masks for plasma dicing using mechanical grinding, generation of reaction products is prevented when removing the masks, so that the dicing can be conducted without causing quality deterioration due to the accumulated particles.

Abstract: A ceramic substrate (100) includes a top surface, a plurality of identification marks (104), a protective compound (110), a bottom surface, and a plurality of grooves (106). The top surface includes a first area and a second area. The first area is defined at one or more edges portions of the top surface. The second area is defined inside the first area. The identification marks are arranged on the first area. The protective compound is covered on the second area. The grooves are defined at the bottom surface, and corresponding to the identification marks. A related method for breaking a ceramic substrate includes: (a) pasting one or more tapes on the first area; (b) covering protective compound on the second area; (c) removing the tapes; (d) cutting the protective compound according to the identification marks; and (e) breaking the ceramic substrate into individual circuit unit pieces along the grooves.

Abstract: In a production of a semiconductor device, after a step in which a thermosetting resin is thermally cured to seal a semiconductor chip with the resin and before a step in which a characteristic of the semiconductor chip is inspected, the thermosetting resin is baked at a temperature higher than the resin sealing temperature in said resin sealing step.

Abstract: One embodiment provides a method of manufacturing semiconductor devices. For example, a sawn and expanded wafer is utilized having dielectrical material deposited between the diced and deposited chips. The method includes placing at least two chips on a metallic layer, depositing mold material on the metallic layer and between the chips, and selectively removing a portion of the mold material from the metallic layer to selectively expose a portion of the metallic layer. The method additionally includes covering the selectively exposed portion of the metallic layer with a conductive material, and singulating the at least two chips.

Abstract: A method for manufacturing a wafer level package of an integrated circuit element for direct attachment to a wiring board is disclosed. An integrated circuit element includes input/output pads located on an active side. A non-conductive support structure is formed on the active side of the integrated circuit element in an area that is free from input/output pads. A conductive path is formed upon the support structure and a non-conductive coating is formed on over the active side of the integrated circuit element such that a surface is formed which leaves interface pads accessible.

Abstract: A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and side surfaces of the semiconductor substrate.

Abstract: Isolation structure for CMOS image sensor device chip scale packages and fabrication methods thereof. A CMOS image sensor chip scale package includes a transparent substrate configured as a support structure for the package. The transparent substrate includes a first cutting edge and a second cutting edge. A CMOS image sensor die with a die circuitry is mounted on the transparent substrate. An encapsulant is disposed on the substrate encapsulating the CMOS image sensor die. A connection extends from the die circuitry to a plurality of terminal contacts for the package on the encapsulant, wherein the connection is exposed by the first cutting edge. An isolation structure is disposed on the first cutting edge passivating the exposed connection and co-planed with the second cutting edge.

Abstract: Methods of packaging integrated circuits are described. One method relates to attaching a singulated device wafer to a substrate. The singulated device wafer includes a multiplicity of integrated circuit dice arranged in a first configuration. The method also involves a substrate, which includes a sacrificial semiconductor wafer having device areas with metalized contacts. The device areas on the substrate may be arranged in a configuration matching that of the dice on the device wafer. The method also entails aligning the singulated device wafer as a whole with the substrate so that the dice of the device wafer are positioned substantially simultaneously over associated device areas on the substrate. The method also involves attaching the dice from the singulated wafer as a whole substantially simultaneously to the substrate such that each die of the device wafer is attached to an associated device area of the substrate.

Abstract: A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

Abstract: A method and system for utilizing a semiconductor wafer is disclosed. The wafer comprises a plurality of semiconductor die and a plurality of scribe areas interspersed between. The method and system comprises forming bond out pads in the scribe areas such that the bond out pads are disposed on the semiconductor wafer between the plurality of semiconductor die. Additionally, the method and system comprises separating the semiconductor wafer into individual die such that when the semiconductor wafer is separated in a first manner at least one product die is provided. Furthermore, when the semiconductor wafer is separated in a second manner at least one test die is provided.

Abstract: A wafer processing apparatus (10), for processing a wafer (20) with a surface protective film (110) attached on the front surface (21) on which at least one circuit pattern is formed, includes a dicing tape application unit (30) for attaching a dicing tape (3) on a frame (36) and the wafer, a surplus dicing tape take-up unit (40) for taking up the surplus part of the dicing tape attached on the frame and the wafer and a surface protective film peeling unit (50) for peeling the surface protective film from the wafer using a peeling tape (4). At least one of the dicing tape application unit, the surplus dicing tape take-up unit and the surface protective film peeling unit is slidably arranged in that order on common rails (91, 92). As a result, tape can be loaded and the maintenance work on each unit can be carried out easily.

Abstract: Objects are to reduce damage to a semiconductor integrated circuit by external stress and to increase the manufacturing yield of a thinned semiconductor integrated circuit. A single crystal semiconductor layer separated from a single crystal semiconductor substrate is used for a semiconductor element included in the semiconductor integrated circuit. Moreover, a substrate which is formed into a thin shape and provided with the semiconductor integrated circuit is covered with a resin layer. In a separation step, a groove for separating a semiconductor element layer is formed in the supporting substrate, and a resin layer is provided over the supporting substrate in which the groove is formed. After that, the resin layer and the supporting substrate are cut in the groove so as to be divided into a plurality of semiconductor integrated circuits.

Abstract: In some embodiments, a metal cover on flip-chip matrix-array (FCMX) substrate for low cost CPU assembly is presented. In this regard, an apparatus is introduced comprising a plurality of integrated circuit dice coupled with a substrate, a thermal interface material on top surfaces of the dice, and a metal plate on top of the thermal interface material on top of the dice. Other embodiments are also disclosed and claimed.