Abstract: A semiconductor device includes a link portion that connects a second heat sink to a third heat sink via a solder. The solder is arranged on a connecting surface of a base portion of the link portion, which is orthogonal to a plate thickness direction of the base portion, in a direction perpendicular to first and second surfaces. The link portion has a rib that protrudes from the base portion in a direction orthogonal to the first and second surfaces, and a thickness of a portion where the rib is provided is equal to or less than the thickness of the corresponding heat sink. The rib is provided across an entire length of a first region that is sealed by a sealing resin body and that is between the second and the third heat sinks, in an alignment direction of a first heat sink and the third heat sink.

Abstract: A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.

Abstract: A semiconductor package includes terminals extending from a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. Each terminal includes a first plated section, a second plated section, and a portion of a sheet carrier from which the semiconductor package is built upon, wherein the portion is coupled between the first and second plated sections. Each interconnection routing is electrically coupled with a terminal and can extend planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes at least one intermediary layer, each including a via layer and an associated routing layer. The semiconductor package includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.

Abstract: An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.

Abstract: A power semiconductor device comprising a power semiconductor module and a heat sink; and a method for its manufacture. The module has a cooling plate, with an opening delimited by a lateral first surface thereof extending circumferentially around the opening. The cooling plate is arranged in the opening and has a lateral first surface which extends circumferentially around the cooling plate. The two first surfaces are at a respective angle of less than 90° with respect to a main surface of the cooling plate facing the power semiconductor components. The two first surfaces are pressed together, extending circumferentially along the first surface of the cooling plate and extending circumferentially along the first surface of the heat sink. The inventive power semiconductor device has good heat conduction from the power semiconductor components to the heat sink through which a liquid can flow, and which is reliably leaktight over the long term.

Abstract: An article of manufacture comprises a composite, layered, and compressible TIM differentially adhered to a heat-spreader surface and a heat-source surface, such as a circuit card, where at least one of the surfaces comprises an uneven surface, and the TIM is compressively bonded to the uneven surface. The adhesive strength of the TIM to the heat-spreader surface is unequal to the adhesive strength of the TIM to the heat-source surface, and is adjusted so that the heat-spreader surface and the heat-source surface can be separated without damaging the heat-source surface. A process comprises manufacturing the article of manufacture.

Abstract: A semiconductor package usable with a mobile device includes a circuit board including conductive wirings therein and contact terminals on a rear surface thereof, an integrated circuit chip positioned on a front surface of the circuit board and electrically connected to the conductive wirings, a cover including at least an opening, and to cover the integrated circuit chip such that a flow space is provided around the integrated circuit chip and the opening communicates with the flow space, and an air flow generator positioned on the cover to generate a compulsory air flow through the flow space and the opening, thereby dissipating heat out of the semiconductor package from the integrated circuit chip by the compulsory air flow.

Abstract: A metal matrix composite is disclosed that includes graphene nanoplatelets dispersed in a metal matrix. The composite provides for improved thermal conductivity. The composite may be formed into heat spreaders or other thermal management devices to provide improved cooling to electronic and electrical equipment and semiconductor devices.

Abstract: A resin-encapsulated semiconductor device includes: a semiconductor element mounted on a die pad portion; a plurality of lead portions disposed so that distal end parts thereof are opposed to the die pad portion; a metal thin wire for connecting an electrode of the semiconductor element to the lead portion; and an encapsulating resin for partially encapsulating those components. A bottom surface part of the die pad portion, and a bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulating resin. A plated layer is formed on the exposed lead bottom surface part and the exposed lead upper end part.

Abstract: Various embodiments relate to a microchip die cooling assembly comprising a circuit board; a microchip having an exposed die attached to the circuit board; a heatspreader having a top side and a bottom side; a heat sink having a bottom side and a top side comprising a cooling structure; a first thermal interface material in contact with the exposed die and the bottom side of the heatspreader; and a second thermal interface material in contact with the top side of the heat spreader and the bottom side of the heat sink.

Abstract: A semiconductor device has a die mounted on a die paddle that is elevated above and thermally connected via tie bars to a heat sink structure. Heat generated by the die flows from the die to the die paddle to the tie bars to the heat sink structure and then to either the external environment or to an external heat sink. By elevating the die/paddle sub-assembly above the heat sink structure, the packaged device is less susceptible to delamination between the die and die attach adhesive and/or the die attach adhesive and the die paddle. An optional heat sink ring can surround the die paddle.

Abstract: An integrated circuit packaging system, and method of manufacture therefor, includes: a substrate; a mold cap formed on the substrate; fiducial mark inscribed in the mold cap; a thermal interface material applied over the substrate and referenced by the fiducial mark; and a heat spreader, mounted on the thermal interface material, precisely positioned by a position notch aligned relative to the fiducial mark.

Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.

Abstract: A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel, and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel. Other embodiments are also disclosed and claimed.

Abstract: Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Abstract: A method includes recording a wafer ID and a location ID of a device die in a database, and bonding the device die over a package substrate, wherein the device die and the package substrate are disposed in a package. A package ID is on the package. A mapping is established to link the wafer ID and the location ID of the device die to the package ID.

Abstract: A BGA type packaged integrated circuit (IC) die has an exposed coronal heat spreader. The die, which is attached to a substrate, is encapsulated in a central segment of molding compound. The central segment is laterally surrounded by, and separated by a moat from a ring segment of molding compound, to a form a slot. The coronal heat spreader is inserted into the slot to cap the central segment. The coronal heat spreader is attached to the substrate and to the central segment with thermal glue. In operation, at least some of the heat generated by the die is dissipated through the coronal heat spreader.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor chip; a resin which covers the semiconductor chip, and includes first and second surfaces opposite to each other, first and second side surfaces opposite to each other, and third and fourth side surfaces opposite to each other; a first conductive member which is formed on the semiconductor chip on a first surface side, and includes an end portion projecting from the first or second side surface; a second conductive member including an end portion projecting from the first or second side surface; and a metal which is formed on a second surface side of the semiconductor chip, is exposed from the resin body on the second surface side, and includes an end portion thereof exposed from the third and fourth side surfaces on the same plane as the third and fourth side surfaces.

Abstract: According to one embodiment, a semiconductor device includes a metal plate, a plurality of semiconductor chips, an insulation layer, a wiring layer, external connection terminals and a sealing resin portion. The metal plate includes a first surface and the plurality of semiconductor chips are laminated on a second surface of the metal plate. The insulation layer and the wiring layer are provided on the semiconductor chips. The external connection terminals are provided on the insulation layer and the wiring layer. The sealing resin portion seals the plurality of semiconductor chips while exposing the first surface of the metal plate. At least one pair of opposing outer peripheral surfaces of the metal plate are covered with the sealing resin portion.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor element, a mounting member including Cu, and a bonding layer provided between the semiconductor element and the mounting member. The bonding layer includes a first region including Ti and Cu, and a second region provided between the first region and the mounting member, and including Sn and Cu. A first position along the first direction is positioned between the semiconductor element and a second position along the first direction. The first position is where the composition ratio of Ti in the first region is 0.1 times a maximum value of the composition ratio of Ti. The second position is where the composition ratio of Sn in the second region is 0.1 times a maximum value of the composition ratio of Sn. A distance between the first position and the second position is not less than 0.1 micrometers.

Abstract: In one embodiment, a heat dissipation connector mounted on a semiconductor chip and sealed up with a molding resin along with the semiconductor chip and a lead frame includes a heat dissipation portion configured to have a block shape, and have an upper face exposed out of the molding resin. The connector further includes a connecting portion configured to extend from a first side face of the heat dissipation portion, and electrically connect an electrode arranged on the semiconductor chip to the lead frame. The heat dissipation portion and the connecting portion are integrally made of the same metal sheet.

Abstract: In a package structure, a stiffener ring is over and bonded to a top surface of a first package component. A second package component is over and bonded to the top surface of the first package component, and is encircled by the stiffener ring. A metal lid is over and bonded to the stiffener ring. The metal lid has a through-opening.

Abstract: In accordance with one or more embodiments, a semiconductor device comprises a semiconductor die having a heat region disposed on at least one portion of the semiconductor die, and a diamond substrate disposed proximate to the semiconductor die, wherein the diamond substrate is capable of dissipating heat from the diamond substrate via at least one or more bumps coupling the diamond substrate to the heat region of the semiconductor die.

Abstract: A power semiconductor device comprising a power semiconductor module and a heat sink and a method for its manufacture. The heat sink has a first cooling housing component, with a cutout passing therethrough, and a second cooling housing component, with a cooling plate arranged in the cutout. The first and second cooling housing components are configured and arranged relative to one another so that a cavity is formed at the side of the cooling plate facing away from the power semiconductor components. The cooling plate is connected to the first cooling housing component by a first weld seam which extends circumferentially therearound. The first weld seam seals the cooling plate in relation to the first cooling housing component, and the second cooling housing component is connected to the first cooling housing component. The inventive power semiconductor device has good heat conduction from the power semiconductor components to a heat sink.

Abstract: High-power electronic components generate significant amounts of heat that must be removed in the course of normal device operations. Certain types of electronic components, such as some monolithic microwave integrated circuits and LEDs, can contain materials that are difficult to effectively bond to a heat gink in order to establish a thermal interface between the two. Device assemblies can include a heat-generating electronic component in thermal communication with a metallic heat sink via a metallic thermal interface layer. The metallic thermal interface layer is disposed between the heat-generating electronic component and the metallic heat sink. The metallic thermal interface layer is formed from a composition including a plurality of metal nanoparticles that are at least partially fused together with one another.

Abstract: A DC voltage conversion module includes a substrate, an input terminal, an output terminal, a ground terminal, a DC voltage conversion control element mounted on the substrate, a coil mounted on the substrate and connected to the DC voltage conversion control element and the output terminal, an input-side capacitor mounted on the substrate and connected to the input terminal and the ground terminal, and an output-side capacitor mounted on the substrate and connected to the output terminal and the ground terminal. The input terminal, the output terminal and the ground terminal project in a predetermined projecting direction parallel to each other. The ground terminal is arranged between the input terminal and the output terminal in a direction perpendicular to the projecting direction.

Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A heat spreader encircles the die and the interposer. A wire includes a first end bonded to one of the plurality of metal lines, and a second end bonded to the heat spreader.

Abstract: A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a thermal attach cluster includes: forming a heat collector having a heat dissipation surface, forming a cluster bridge, having a thermal surface, connected to the heat collector, forming a cluster pad, having an attachment surface, connected to the end of the cluster bridge opposite the heat collector; connecting an integrated circuit to the thermal attach cluster; and forming an encapsulation over the thermal attach cluster with the heat dissipation surface, the thermal surface, and the attachment surface exposed from and coplanar with the encapsulation.

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting a device mounting structure over a bottom substrate; mounting a heat spreader having an opening formed by a single integral structure with a dam and a flange, the dam having a dam height greater than a flange height of the flange; and forming a package encapsulation over the device mounting structure and the bottom substrate with the device mounting structure exposed within the opening.

Abstract: In a semiconductor device, a semiconductor module is pressed against a cooler by a spring member. The spring member is compressed by a beam member that is connected with a strut fixed to the cooler. The cooler has a pressed part in which the semiconductor module is pressed, and a strut fixing part to which the strut is fixed. The strut fixing part has higher rigidity than the pressed part.

Abstract: A semiconductor device includes a semiconductor chip joined with a substrate and a base plate joined with the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure. The second metal layer has a sub-layer that has no pins and no pin-fins. The first metal layer has a first thickness and the sub-layer has a second thickness. The ratio between the first thickness and the second thickness is at least 4:1.

Abstract: A method of manufacturing a core substrate having an electronic component, including providing a core substrate having a first surface and a second surface on an opposite side of the first surface, forming a through hole extending from the first surface to the second surface in the core substrate, attaching an adhesive tape to the second surface of the core substrate such that the through hole formed in the core substrate is closed on the second surface, attaching an electronic component to the adhesive tape inside the through hole, filling the through hole with a filler, and removing the adhesive tape from the second surface of the core substrate.

Abstract: Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.

Abstract: Provided is a semiconductor device including a flexible circuit board which includes a first external electrode provided on a first face and second and third external electrodes provided on a second face; a plurality of memory devices and passive components; a supporter which is provided with a groove on one face; and a computing processor device. The memory devices and the passive components are connected to the first external electrode, the one face of the supporter is bonded on the first face of the flexible circuit board so that the groove houses the memory devices and the passive components. The flexible circuit board is bent along a perimeter of the supporter to be wrapped around a side face and another face of the supporter. On the flexible circuit board, the second external electrode is provided on the second face which is opposite to the first external electrode, and the third external electrode is provided on the second face which is bent to the another face of the supporter.

Abstract: A semiconductor device has a connection structure in which a power semiconductor chip is mounted on an insulating substrate having conductor patterns bonded to front and rear surfaces thereof, and the insulating substrate is connected to a heat-dissipating base member to dissipate heat generated from the power semiconductor chip to outside. The conductor pattern on the rear surface bonded to the heat-dissipating base member has a bonding portion having a rectangular shape and a predetermined curvature radius in vicinity of corners.

Abstract: A low cost and high performance flip chip package is disclosed. By assembling the package using a substrate panel level process, a separate fabrication of a substrate is avoided, thus enabling the use of a coreless substrate. The coreless substrate may include multiple stacked layers of laminate dielectric films having conductive traces and vias. As a result, electrical connection routes may be provided directly from die contact pads to package contact pads without the use of conventional solder bumps, thus accommodating very high density semiconductor dies with small feature sizes. The disclosed flip chip package provides lower cost, higher electrical performance, and improved thermal dissipation compared to conventional fabricated substrates with solder bumped semiconductor dies.

Abstract: The electronic device includes a heat generator 54, a heat radiator 58, and a heat radiation material 56 disposed between the heat generator 54 and the heat radiator 58 and including a plurality of linear structures 12 of carbon atoms and a filling layer 14 formed of a thermoplastic resin and disposed between the plurality of linear structures 12.

Abstract: An extended preform of a thermal interface material (TIM) is formed between a heat spreader and a die on a substrate. The preform has an extension beyond a footprint of the die. The preform is cured. A bleed out of the TIM is controlled by the extension upon curing of the preform.

Abstract: A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided.

Abstract: A semiconductor module is manufactured by bonding a resin case having a first opening through which surfaces of main circuit terminals and control terminals are exposed, onto a metal heat-dissipating substrate onto which is bonded, a conductive-patterned insulating substrate onto which are bonded, semiconductor chips, the main circuit terminals, and the control terminals; inserting into and attaching to a second opening formed on a side wall constituting a resin case, a resin body having a nut embedded therein to fix the main circuit terminals and the control terminals; and filling the resin case with a resin material. A side wall of the first opening is tapered toward the surface thereof; a tapered contact portion contacting the tapered side wall is disposed on the control terminal; and the resin body having the embedded nut fixes the control terminal having a one-footing structure that is an independent terminal.

Abstract: An embodiment method for fabricating electronic devices having two components connected by a metal layer includes applying a metal layer to each component and connecting the metal layers such that a single metal layer is formed.

Abstract: A semiconductor device has a first semiconductor die and an encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and encapsulant. A thermal interface material is formed over the first semiconductor die and encapsulant. A stiffening layer is formed over the first semiconductor die and an edge portion of the encapsulant. Alternatively, an insulating layer is formed adjacent to the first semiconductor die and a stiffening layer is formed over the insulating layer. The stiffening layer includes metal, ferrite, ceramic, or semiconductor material. A heat spreader is disposed over the first semiconductor die and a central portion of the encapsulant. Openings are formed in the heat spreader. A recess is formed in the heat spreader along an edge of the heat spreader. A coefficient of thermal expansion (CTE) of the stiffening layer is less than a CTE of the heat spreader.

Abstract: An integrated power module includes a substantially planar insulated metal substrate having at least one cut-out region; at least one substantially planar ceramic substrate disposed within the cut-out region, wherein the ceramic substrate is framed on at least two sides by the insulated metal substrate, the ceramic substrate including a first metal layer on a first side and a second metal layer on a second side; at least one power semiconductor device coupled to the first side of the ceramic substrate; at least one control device coupled to a first surface of the insulated metal substrate; a power overlay electrically connecting the at least one semiconductor power device and the at least one control device; and a cooling fluid reservoir operatively connected to the second metal layer of the at least one ceramic substrate, wherein a plurality of cooling fluid passages are provided in the cooling fluid reservoir.

Abstract: The semiconductor package as well as a method for making it and using it is disclosed. The semiconductor package comprises a semiconductor chip having at least one heat-generating semiconductor device and a volumetrically expandable chamber disposed to sealingly surround the semiconductor chip, the volumetrically expandable chamber filled entirely with a non-electrically conductive liquid in contact with the semiconductor device and circulated within the volumetrically expandable chamber at least in part by the generated heat of the at least one semiconductor device to cool the at least one semiconductor device.

Abstract: An LED manufacturing method includes following steps: providing an LED die; providing an electrode layer having a first section and a second section electrically insulated from the first section, and arranging the LED die on the second section wherein an electrically conductive material electrical connects a bottom of the LED die with second section; forming a transparent conductive layer to electrically connect a top of the LED die with the first section; providing a base and coating an outer surface of the base with a layer of electrically conductive material, defining a continuous gap in the electrically conductive material to divide the electrically conductive material into a first electrode part, and a second electrode part, arranging the electrode layer on the base so that the first section contacts the first electrode part, and the second section contacts the second electrode part.

Abstract: An electronic component comprising a substrate extending in a plane, having electrical connections to connect the component to a circuit, and having an upper face; an electronic chip arranged on the upper face or inside the substrate and connected to the connections via the substrate, a thick insulating layer forming a package and covering the upper face or at least part of the chip, and having an outer face parallel to the plane; a cavity inside the thick layer, the cavity having a bottom parallel to the plane and a side extending from the bottom to the outer face, the cavity having heat-absorbing material inside that is different from the material forming the thick layer. The heat-absorbing material has a specific heat capacity greater than 1 kJKg?1K?1 at a 25° C. and at 100 kPa. Either a bottom or side of the cavity is covered with a interface layer.

Abstract: A semiconductor device (100) comprises a semiconductor chip (310) attached to the pad (302) of a planar leadframe and connected by bonding wires (411) to two leads (403) of the leadframe. The device further includes a plastic body (130) encapsulating chip and wires, the body shaped as a pentahedron with two sides (101, 102) touching at right angle, opposite body ends formed by parallel planes configured as right-angle triangles. The pad (302) and the two leads (303) are exposed from the plastic surface at one body end in order to be operable as solderable device pins positioned in the corners of the triangle.

Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.