Abstract: A quad flat non-lead (QFN) semiconductor package includes a die attach pad having a recessed area; a semiconductor die mounted inside the recessed area of the die attach pad; at least one row of inner terminal leads disposed adjacent to the die attach pad; first wires bonding respective said inner terminal leads to the semiconductor die; at least one row of extended, outer terminal leads disposed along periphery of the QFN semiconductor package; at least one row of intermediary terminals disposed between the inner terminal leads and the extended, outer terminal leads; second wires bonding respective the intermediary terminals to the semiconductor die; and third wires bonding respective the intermediary terminals to the extended, outer terminal leads.

Abstract: A method for improving signal levels between capacitively-coupled chips in proximity communication (PxC) includes depositing a high permittivity dielectric material layer over a signal pad of a first chip, and placing a second chip in close proximity to the first chip such that faces of the signal pads align to enable for capacitive signal coupling. The high permittivity dielectric material layer that fills at least a portion of a gap between the first chip and the second chip, and improves capacitive coupling between signal pads of the first chip and the second chip by providing for an increased permittivity in the gap between the first chip and the second chip. The increased permittivity ensures that electric fields are substantially confined to a space between the signal pad of the first chip and the signal pad of the second chip.

Abstract: A method of assembling an IC device package is provided. A leadframe is formed. At least one IC die is attached to a die attach pad portion of the leadframe. Wire bonds are coupled between the IC die and the leadframe. A cap is attached to the leadframe. A second surface of the cap includes a cavity formed therein. The cap and leadframe form an enclosure structure that substantially encloses the at least one IC die. An encapsulating material is applied to encapsulate at least the IC die. A perimeter support ring portion of the leadframe is trimmed.

Abstract: Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.

Abstract: Embodiments of the invention provide a method for fabricating a system in package. In one embodiment, the method comprises preparing a printed circuit board (PCB) strip comprising a plurality of individual PCBs, stacking a plurality of first semiconductor chips and forming an encapsulant on a first surface of a first individual PCB of the plurality of individual PCBs to form a first semiconductor chip stack structure comprising a first semiconductor chip stack, and performing a first test adapted to test one of the first semiconductor chips in the first semiconductor chip stack. The method further comprises flip chip bonding a second semiconductor chip to a second surface of the first individual PCB if the first semiconductor chip stack structure meets a test standard based on a result of the first test, and dividing the first semiconductor chip stack structure to form a system in package.

Abstract: A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip.

Abstract: A method and device relating the electrical interconnection of angularly disposed conductive is disclosed. Conventional wire bonding equipment is used to apply a wire ball on a first conductive surface in an electronic assembly. A conductive wire is drawn up vertically and terminated such that the central portion of the wire is proximal the second conductive surface. The electronic assembly is reoriented with respect to the travel of the capillary whereby a stitch bond is defined upon the second conductive surface to define an interconnect wire and a terminal wire portion, which terminal wire portion is removed.

Abstract: A method for manufacturing a semiconductor device includes mounting a first chip over a first area of a chip mounting section of a lead frame and mounting a second chip over a second area of the chip mounting section, wherein the second area is adjacent to the first area via the slit. The chip mounting section is disposed on a flat heating jig. First pads of the first chip are connected with second pads of the second chip via first wires, respectively, and the first pads are connected with leads of the lead frame via second wires, respectively. the first chip, the second chip, the first wires and the second wires are sealed with a resin such that a part of each of the leads is exposed from the resin, and each of the leads is then separated from the lead frame.

Abstract: An object is to provide an electronic device of a multilayer structure with high density and high reliability that can be reduced in size while incorporating an electronic component therein, and further provide a production method for easily producing such an electronic device. An electronic device of the present invention includes wiring layers and electrically insulating layers stacked on a core board and establishes predetermined electrical conduction between the wiring layers through upper-lower side conducting vias provided in the electrically insulating layers.

Abstract: A semiconductor device and manufacturing method. One embodiment provides at least two semiconductor chips. A dielectric material is applied to the at least two semiconductor chips to attach the at least two semiconductor chips to each other. A portion of the dielectric material is selectively removed between the at least two semiconductor chips to form at least one recess in the dielectric material. Metal particles including paste is applied to the at least one recess in the dielectric material.

Abstract: A method is disclosed to form an upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-type region is doped with arsenic, and the semiconductor material of the diode is crystallized in contact with an appropriate silicide, germanide, or silicide-germanide. A large array of such upward-pointing diodes can be formed with excellent uniformity of current across the array when a voltage above the turn-on voltage of the diodes is applied. This diode is advantageously used in a monolithic three dimensional memory array.

Abstract: The invention relates to the field of electronics, more particularly to the wire bonds incorporated into an integrated circuit package such as a quad flat pack, a ball grid array or hybrid style module. The present invention takes the normally undesirable wire bond inductance and uses it in an operational circuit where positive inductance is required. The circuit in which the wire bond inductance is used is located primarily in the integrated circuit die housed in the integrated circuit package, but may also include off-die components. In one example, a wire bond is used as the required series inductance in a discrete circuit impedance inverter which consists of two shunt-to-ground negative inductances and one series positive inductance. One of the negative inductances is located on-die, while the other is located off-die.

Abstract: A method of manufacturing a semiconductor device is provided, involving forming a first flexible film on a rigid carrier substrate, attaching a die to the flexible film, so as to leave contacts on the die exposed, forming a wiring layer to contact the contacts of the die, and releasing the flexible film where the die is attached, from the carrier. An area of the first flexible film where the die is attached can have a lower adhesion to the rigid carrier substrate than other areas, so that releasing can involve cutting the first flexible film to release a part of the area of lower adhesion, and leaving an area of higher adhesion. A combined thickness of the die, the first flexible film and the wiring layer can be less than 150 ?m, so that the device is bendable. Devices can be stacked.

Abstract: A packaging substrate structure with electronic components embedded therein and a method for manufacturing the same are disclosed. The packaging substrate structure comprises: a core board; a built-up structure disposed on at least one surface of the core board, wherein the built-up structure has a plurality of conductive pads and an electronic component-disposing part on the surface thereof; a solder mask disposed on the surface of the built-up structure, where the solder mask has a open area to expose the electronic component-disposing part and a plurality of openings to expose the conductive pads of the built-up structure; and an electronic component disposed on the electronic component-disposing part and in the open area. Accordingly, the packaging substrate disclosed by the present invention exhibits enhanced electrical performance and product reliability.

Abstract: Stacked microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such microelectronic device can include a support member and a first known good microelectronic die attached to the support member. The first die includes an active side, a back side opposite the active side, a first terminal at the active side, and integrated circuitry electrically coupled to the first terminal. The first die also includes a first redistribution structure at the active side of the first die. The microelectronic device can also include a second known good microelectronic die attached to the first die in a stacked configuration such that a back side of the second die is facing the support member and an active side of the second die faces away from the support member. The second die includes a second redistribution structure at the active side of the second die.

Abstract: A semiconductor device is made by providing a sacrificial substrate, forming a first insulating layer over the sacrificial substrate, forming a first passivation layer over the first insulating layer, forming a second insulating layer over the first passivation layer, forming an integrated passive device over the second insulating layer, forming a wafer support structure over the integrated passive device, removing the sacrificial substrate to expose the first insulating layer after forming the wafer support structure, and forming an interconnect structure over the first insulating layer in electrical contact with the integrated passive device. The integrated passive device includes an inductor, capacitor, or resistor. The sacrificial substrate is removed by mechanical grinding and wet etching. The wafer support structure can be glass, ceramic, silicon, or molding compound.

Abstract: A packaging method comprises: forming a circuit board by forming a substantially continuous conductive layer on an insulating board and removing selected portions of the continuous conductive layer to define an electrically conductive trace; laser cutting the electrically conductive trace to define sub-traces electrically isolated from each other by a laser-cut gap formed by the laser cutting; and bonding a light emitting diode (LED) chip to the circuit board across or adjacent to the laser-cut gap, the bonding including operatively electrically connecting an electrode of the LED chip to one of the sub-traces without using an interposed submount. A semiconductor package comprises an LED chip flip-chip bonded to sub-traces of an electrically conductive trace of a circuit board, the sub-traces being electrically isolated from each other by a narrow gap of less than or about 100 microns.

Abstract: A semiconductor process is provided. First, a silicon base is provided. Next, a surface of the silicon base is partially exposed and at least a stair structure is formed on the silicon base by etching the surface of the silicon base. The stair structure has a first notch with a first depth and a second notch with a second depth. The first depth is smaller than the second depth, and a diameter of the first notch is larger than a diameter of the second notch. A final insulating layer and a metal seed layer are sequentially formed on the stair structure. A patterned photoresist layer is formed on the metal seed layer. A circuit layer coving exposed portions of the metal seed layer located above the first notch is formed. The patterned photoresist layer and portions of the metal seed layer disposed below the patterned photoresist layer are then removed.

Abstract: Embodiments of the present invention includes a method of assembling a chip scale package (CSP). The method comprises adding bumps, sawing the saw streets from the front of a wafer, molding the front of the wafer, grinding the back of the wafer, sawing the saw streets from the back of the wafer, molding the back of the wafer, and sawing between devices to form a plurality of packaged devices. Sawing the saw streets from the front of the wafer establishes a first cut. Molding the front of the wafer includes using a first mold compound such that the mold compound fills in the first cut. Sawing the saw streets from the back of the wafer establishes a second cut.

Abstract: A high reliability radiation shielding integrated circuit apparatus comprising a plurality of package layers; a radiation shielding lid or base coupled to the plurality of package layers; wherein the circuit die are shielded from receiving an amount of radiation greater than the total dose of tolerance of the circuit die. In one embodiment, an integrated circuit apparatus for use in high reliability applications is disclosed. The integrated circuit apparatus is designed to be highly reliable and protect integrated circuit die from failing or becoming unreliable due to radiation, mechanical forces, thermal exposure, or chemical contaminates.

Abstract: Some embodiments of the present invention relate to a semiconducting device and method that include a substrate and a first die that is attached to the substrate. The first die includes active circuitry (e.g., a flash memory array or logic circuitry) on an upper surface of the first die. The semiconducting device further includes a spacer that covers the active circuitry on the upper surface of the first die and a second die that is stacked onto the spacer and the first die. The spacer extends from a first side of the first die to an opposing second side of the first die. The spacer also extends near a third side of the first die and an opposing fourth side of the first die such that the active circuitry is exposed near the third and fourth sides of the first die.

Abstract: This invention is a method for manufacturing a high-frequency module device. A high-frequency circuit unit (2) in which first to third unit wiring layers (5) to (7), each having a capacitor (12) or the like at a part, are stacked and formed on flattened one surface of a dummy board (30) so that a third pattern wiring is exposed from a connection surface (2a) of an uppermost layer is mounted on a mounting surface (3a) of a base board (3) where an input/output terminal part (18) is exposed, in such a manner that the third pattern wiring and the input/output terminal part are connected with each other, and after that, the dummy board is removed. A high-frequency module device is thus manufactured.

Abstract: A semiconductor device in which a semiconductor has good heat dissipation efficiency, a display employing such a semiconductor device and a method for manufacturing a semiconductor device. A conductive pattern providing a semiconductor-connecting terminal portion and further providing first and second external-connection terminal portion on the opposite sides of the semiconductor-connecting terminal portion is formed on the surface of a flexible insulating substrate to produce a flexible printed wiring board on which a semiconductor is mounted and connected with the semiconductor-connecting terminal portion in the conductive pattern. In such a semiconductor device, a slit is formed in the insulating substrate to surround the semiconductor while leaving a part around the semiconductor thus providing a semiconductor holding part.

Abstract: A method for assembling a hermetically sealed package to contain a MEMS die and the hermetically sealed package are presented. The method includes selectively applying a glass mixture to a dome. The dome is heated to a first temperature sufficient to flow the glass mixture. The dome is pressed into contact with a carrier containing the MEMS device, the pressing being maintained at a pressure and for a temporal interval sufficient to flow the glass mixture onto the carrier. The dome is cooled while maintaining contact with the carrier, to a second temperature sufficient to allow the glass mixture to harden into a glass frit thereby to seal the carrier to the dome. The glass frit has a seal width.

Abstract: A method and an apparatus for improving the delivery and filtering of power to a semiconductor device is disclosed by organizing out interconnects (pins, balls, pads or other interconnects) used to carry power in a striped configuration that shortens the conductive path required between a power source and a semiconductor device and that reduces the resistance of that conductive path.

Abstract: A semiconductor device includes a plurality of insulating layers laminated on a substrate to cover passive elements such as a capacitor, an inductor, and the like, and to fix an IC chip in a face up state in one of the insulating layers. The insulating layers have similar structures in each of which the passive element or the semiconductor chip is disposed in at the bottom, a plug is formed in the insulating layer to pass therethrough in the thickness direction for extending an electrode of one of these elements to the top surface, and a conductive layer is provided as wiring on the top surface of the insulating layer to be connected to the plugs for electrically connecting respective elements or rearranging the electrode position. Also, an insulating layer is provided on the top for protecting the semiconductor device and for providing an external connecting electrode.

Abstract: An edge-sealed, encapsulated environmentally sensitive device. The device includes an environmentally sensitive device, and at least one edge-sealed barrier stack. The edge-sealed barrier stack includes a decoupling layer and at least two barrier layers. The environmentally sensitive device is sealed between an edge-sealed barrier stack and either a substrate or another edge-sealed barrier stack. A method of making the edge-sealed, encapsulated environmentally sensitive device is also disclosed.

Abstract: A first dielectric layer is formed on a mold having a surface and protruding components and covers the protruding components. At least one electronic component having an active surface, a back surface, and contacts formed on the active surface is disposed on the first dielectric layer. The active surface is faced to the first dielectric layer, and the contacts are corresponding to the protruding components. A second dielectric layer is formed on the first dielectric layer and a carrier is disposed on the back surface of the electronic component. Openings located corresponding to the contacts are further formed within the first dielectric layer by the protruding components in an imprinting step, such that when the mold is removed, the contacts are exposed from the openings.

Abstract: A process includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The process includes placing a first die in a first die recess of the first heat spreader, and placing a second die in a second die recess in the second heat spreader. The process includes reflowing thermal interface material between each die and respective heat spreader. Thereafter, the process includes separating the first heat spreader and the second heat spreader. A package is achieved by the process, with reduced thicknesses. The package can be disposed onto a mounting substrate. The package can be assembled into a computing system.

Abstract: There is provided a method of forming a component package. The method includes the steps of providing the die pad or heat sink, forming an isolation layer on the rear surface of the die pad or heat sink and encapsulating the die pad with encapsulating material in a mold cavity after forming the isolation layer on the rear of the die pad or heat sink.

Abstract: A method for manufacturing a thin but robust stack of electrically connected thin film semiconductor elements includes the steps of forming a first element to be stacked: forming a separation layer and a semiconductor element layer over a substrate, forming a wiring connected to the semiconductor element layer, forming a protective material over the semiconductor layer and the wiring, forming a conductive region electrically connected to the wiring in the protective layer, and separating the semiconductor element layer from the substrate along the separation layer. A second element is formed according to the aforementioned process, and the first element is stacked thereon, before separating the second element from its substrate. The first element is bonded to the protective layer of the second element so that the semiconductor element layers of the first and the second element are electrically connected to each other through the protective layer, without damaging the protective layer.

Abstract: A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.

Abstract: A tape automated bonding (TAB) structure which includes a flex tape having a conductive lead pattern formed thereon. The conductive lead pattern includes a plurality of leads configured to form an inner lead bond (ILB) portion of the TAB structure. At least one of the plurality of leads is internally routed and has a contact exposed interior to the ILB portion of the TAB structure.

Abstract: A method of forming a microelectronic package including the steps of providing a three-layer metal plate, having a first layer, a second layer and a third layer. A plurality of conductive elements is formed from the first layer of the metal plate. A dielectric sheet is attached to the first layer of the metal plate, such that the dielectric sheet is remote from the third layer. A plurality of conductive features is then formed from the third layer of the metal plate which are also remote from the dielectric sheet. A microelectronic element is next electrically conducted to the conductive elements and a heat spreader is thermally connected the microelectronic element.

Abstract: An implantable hermetically sealed microelectronic device and method of manufacture are disclosed. The microelectronic device of the present invention is hermetically encased in a insulator, such as alumina formed by ion bean assisted deposition (“IBAD”), with a stack of biocompatible conductive layers extending from a contact pad on the device to an aperture in the hermetic layer. In a preferred embodiment, one or more patterned titanium layers are formed over the device contact pad, and one or more platinum layers are formed over the titanium layers, such that the top surface of the upper platinum layer defines an external, biocompatible electrical contact for the device. Preferably, the bottom conductive layer is larger than the contact pad on the device, and a layer in the stack defines a shoulder.

Abstract: A wiring substrate (1) comprises an insulating base (10) with connection holes (11), buried conductors (12) provided in the connection holes (11) without reaching a rear surface of the insulating base (10), and wiring layers 14 connected to the buried conductors (12). The buried conductors (12) thicken the wiring layers (14), and can form aligning parts (110) on the rear surface of the connection holes (11) to be used for three-dimensional mounting structure. Each wiring layer (14) includes thin terminals (14A), wirings (14B) and thick electrodes (14C). Not only the terminals (14A) and wirings (14B) but also the buried conductors (12) are raised by the same manufacturing process. A semiconductor element (2) is attached to the electrodes (14C) of the wiring substrate (1).

Abstract: A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions.

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: A mold array process (MAP) for manufacturing a plurality of semiconductor packages is revealed. Firstly, a substrate strip including a plurality of substrate units arranged in an array within a molding area is provided. A plurality of chips are disposed on the substrate units. An encapsulant by molding is formed on the molding area of the substrate strip to continuously encapsulate the chips. During the molding process, an adjustable top mold is implemented where a cavity width between two opposing sidewalls inside a top mold chest can be adjusted to make the mold flow speeds at the center and at the side rails of the molding area the same.

Abstract: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.

Abstract: A semiconductor package includes a wiring substrate having a connection pad on both surface sides respectively, and a supporting plate provided on one surface side of the wiring substrate and formed of an insulator in which an opening portion is provided in a portion corresponding to the connection pad. The external connection terminals (the lead pins, or the like) are provided on the connection pads on the surface of the wiring substrate on which the supporting plate is provided, and the semiconductor chip is mounted on the connection pads on the opposite surface.

Abstract: A MEMS switch with a platinum-series contact is capped through a process that also passivates the contact by controlling, over time, the amount of oxygen in the environment, pressures and temperatures. Some embodiments passivate a contact in an oxygenated atmosphere at a first temperature and pressure, before hermetically sealing the cap at a higher temperature and pressure. Some embodiments hermetically seal the cap at a temperature below which passivating dioxides will form, thus trapping oxygen within the volume defined by the cap, and later passivate the contact with the trapped oxygen at a higher temperature.

Abstract: An apparatus, method, and system for providing thermal management for an integrated circuit includes a first metallic layer directly placed on a back surface of the integrated circuit. An integrated heat spreader with a substantially cap-like shape is placed over the integrated circuit, with an aperture of a ceiling wall of the integrated heat spreader exposing a back surface of the integrated circuit at least in part. The first metallic layer is directly placed on top of an exterior surface of the ceiling wall of the integrated heat spreader as well as the back surface of the integrated circuit.

Abstract: An apparatus, method, and system for providing a mechanical divider adapted to shield at least a portion of an active surface of an integrated circuit from out-gassing from underfill material. The mechanical divider is attached to a mounting substrate. The underfill material is dispensed on the mounting substrate. The integrated circuit is placed on both the mechanical divider and on the underfill material after the mechanical divider has been at least partially cured. The mechanical divider may include a base surface adapted to contact the mounting substrate, a lower wall surface extending upwardly from the base surface, an upper wall surface adapted to abut a side wall of the integrated circuit, and a ledge surface extending between the lower wall surface and the upper wall surface, the ledge surface adapted to contact at least a portion of the active surface of the integrated circuit.

Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.

Abstract: A method of fabricating an integrated spatial light modulator. The method includes providing a first substrate including a bonding surface and processing a device substrate to form at least an electrode layer. The method also includes depositing a first portion of a multi-layer standoff layer on the electrode layer, depositing a second portion of the multi-layer standoff layer on the first portion of the multi-layer standoff layer, and forming electrically insulating standoff structures from the multi-layer standoff layer. The method further includes joining the bonding surface of the first substrate to the standoff structures on the device substrate, thinning the first substrate, patterning the first substrate to form a mask, and forming a plurality of moveable structures from the first substrate. The moveable structures are aligned with at least one of the plurality of electrodes and adapted to rotate with respect to the standoff structures.

Abstract: A semiconductor device has an adhesive layer depositing over a temporary carrier. A plurality of fiduciary patterns is formed over the adhesive layer. A repassivation layer is formed over semiconductor die. The repassivation layer may be a plurality of discrete regions. Alignment slots are formed in the repassivation layer. The fiducial patterns and alignment slots have slanted sidewalls. Leading with the repassivation layer, the semiconductor die is placed onto the carrier so that the alignment slots envelope and lock to the fiducial patterns. Alternatively, a die without the repassivation layer is placed between the fiducial patterns. An encapsulant is deposited over the semiconductor die while the die remain locked to the fiducial patterns. The carrier, adhesive layer, and fiducial patterns are removed after depositing the encapsulant. An interconnect structure is formed over the repassivation layer to electrically connect to contact pads on the semiconductor die.

Abstract: A semiconductor device including: a semiconductor substrate in which an integrated circuit is formed; an insulating layer formed on the semiconductor substrate and having a first surface and a second surface which is higher than the first surface; a first electrode formed to avoid the second surface and electrically connected to the inside of the semiconductor substrate; and a second electrode formed on the second surface and electrically connected to the inside of the semiconductor substrate.

Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.

Abstract: Microshells for encapsulation of devices such as MEMS and microelectronics. In an embodiment, the microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation as a function of the dimension of the perforation to form cavities having different vacuum levels on the same substrate.