Abstract: A method of fabricating a semiconductor package is provided, including: providing a carrier having a plurality of chip areas defined thereon, and forming a connection unit on each of the chip areas; disposing a semiconductor element on each of the connection units; forming an insulating layer on the carrier and the semiconductor elements; and forming on the insulating layer a circuit layer electrically connected to the semiconductor elements. Since being formed only on the chip areas instead of on the overall carrier as in the prior art, the connection units are prevented from expanding or contracting during temperature cycle, thereby avoiding positional deviations of the semiconductor elements.

Abstract: A method of manufacturing a ball grid array substrate includes: forming a first circuit pattern and a second circuit pattern on a first metal carrier and a second metal carrier, respectively; stacking a first insulating layer and a second insulating layer with a separable material interposed therebetween, wherein each of the first and second insulating layers has first and second surfaces opposing each other, and the first surface contacts the separable material; burying the first and second circuit patterns in the second surfaces of the first and second insulating layers, respectively; removing the first and second metal carriers; removing the separable material to separate the first and second insulating layers from each other; and forming an opening in each of the first and second insulating layers to connect the first and second surfaces with each other. The method may also be part of a process for manufacturing a semiconductor package.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: A semiconductor device includes: a first semiconductor element having a first terminal surface on which a first terminal is disposed and a first rear surface on which no terminal is disposed; a second semiconductor element having a second terminal surface on which a second terminal is disposed and a second rear surface on which no terminal is disposed, the second rear surface being bonded to the first rear surface; a terminal member having a surface set substantially flush with the second terminal surface; and a conductive wire connecting the terminal member and the first terminal.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer.

Abstract: Disclosed is a semiconductor device that is capable of handling multiple different high-frequency contactless communication modes and that is formed by a multi-chip structure. A first semiconductor chip, which performs interface control of high-frequency contactless communication and data processing of communications data, is mounted on a wiring board; and a second semiconductor chip, which performs another data processing of the communication data, is mounted on the first semiconductor chip. In this case, transmission pads in the first semiconductor chip are arranged at positions farther from a periphery of the chip than those of receiving pads, and the second semiconductor chip is mounted by being biased on the first semiconductor chip so as to keep away the transmission pads.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: A 3D interposer (and method of making same) that includes a crystalline substrate handler having opposing first and second surfaces, with a cavity formed into the first surface. A layer of insulation material is formed on the surface of the handler that defines the cavity. The cavity is filled with a compliant dielectric material. A plurality of electrical interconnects is formed through the interposer. Each electrical interconnect includes a first hole formed through the crystalline substrate handler extending from the second surface to the cavity, a second hole formed through the compliant dielectric material so as to extend from and be aligned with the first hole, a layer of insulation material formed along a sidewall of the first hole, and conductive material extending through the first and second holes.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Abstract: An integrated circuit package system includes: providing a singulated, layered structure equivalent in size to an integrated circuit die and having an adhesive layer, an electrical insulator layer, and a heat slug; attaching the integrated circuit die to a base; attaching bond wires to a top of the base for electrical connection between the integrated circuit die and the base; attaching the singulated, layered structure to the integrated circuit die wherein the bond wires are surrounded by the adhesive layer; and encapsulating the integrated circuit die and a portion of the heat slug with a molding compound.

Abstract: A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure.

Abstract: Various interposers and method of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an identification structure to an interposer. The identification structure is operable to provide identification information about the interposer. The identification structure is programmable to create or alter the identification information.

Abstract: A semiconductor chip package includes a substrate unit, a chip, metal members, a molding compound and a shielding layer. The chip is assembled on and electrically connected with the substrate unit. The substrate unit includes conductive seat portions surrounding the chip, and defines through holes respectively coated by conducting films to ground the corresponding seat portions. The metal members are assembled on the seat portions, surround the chip, and are grounded through the conducting films. The molding compound encapsulates the chip and the metal members, with part of each metal member exposed out of the molding compound. The shielding layer covers the molding compound and the parts of each metal member exposed out of the molding compound to shield the chip from electromagnetic radiation.

Abstract: Embodiments of the present invention provide a vapor phase organic polymer film deposited using a CVD process at low temperature during a process sequence for wafer-level chip scale packaging (WL-CSP), including system-in package (SiP), Package-on-Package (PoP) and Package-in-Package (PiP).

Abstract: A resin sealing method of a semiconductor device includes: positioning semiconductor devices at predetermined positions of an adhesive layer formed on a support body and adhering the semiconductor devices thereto, sealing a part of each of the semiconductor devices with resin by curing a first seal resin in a fluidization state so as to fix the semiconductor devices adhered to the predetermined positions of the adhesive layer formed on the support body, setting the semiconductor devices fixed to the predetermined positions of the adhesive layer formed on the support body in a mold and sealing the exposure parts of the semiconductor devices exposed from the first seal resin with a second seal resin, and removing the support body and the adhesive layer from the semiconductor devices sealed with the resin.

Abstract: An integrated circuit package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween and a semiconductor die mounted on the first surface of the substrate. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulant encapsulates the wirebonds and the semiconductor die. A heat spreader has a cap, at least a portion of the cap extending inwardly toward and being spaced from the semiconductor die. The encapsulant fills the space between the portion of the cap and the semiconductor die. The heat spreader further has at least one sidewall extending from the cap, the at least one sidewall disposed on the substrate. A ball grid array is disposed on the second surface of the substrate, bumps of the ball grid array being in electrical connection with ones of the conductive traces.

Abstract: An integrated circuit package system that includes: providing a first package including a first package first device and a first package second device both adjacent a first package substrate; and mounting and electrically interconnecting a second package over an electrical interconnect array formed on a substrate of the first package second device.

Abstract: A substrate-free semiconducting sheet has an array of semiconducting elements dispersed in a matrix material. The matrix material is bonded to the edge surfaces of the semiconducting elements and the substrate-free semiconducting sheet is substantially the same thickness as the semiconducting elements.

Abstract: A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate having a component side and a system side; coupling stacking interconnects on the component side; and forming an integrated circuit receptacle, for receiving an integrated circuit device, by molding a reinforced encapsulant on the component side and exposing a portion of the stacking interconnects.

Abstract: A power semiconductor module is provided in which power semiconductor chips with an aluminum-based chip metallization and power semiconductor chips with a copper-based chip metallization are included in the same module, and operated at different barrier-layer temperatures during use.

Abstract: A power semiconductor module includes an electrically insulating substrate, copper metallization disposed on a first side of the substrate and patterned into a die attach region and a plurality of contact regions, and a semiconductor die attached to the die attach region. The die includes an active device region and one or more copper die metallization layers disposed above the active device region. The active device region is disposed closer to the copper metallization than the one or more copper die metallization layers. The copper die metallization layer spaced furthest from the active device region has a contact area extending over a majority of a side of the die facing away from the substrate. The module further includes a copper interconnect metallization connected to the contact area of the die via an aluminum-free area joint and to a first one of the contact regions of the copper metallization.

Abstract: The present invention relates to a method of making a semiconductor assembly. In accordance with a preferred embodiment, the method includes: preparing a dielectric layer and a supporting board including a stiffener, a bump/flange sacrificial carrier and an adhesive, wherein the adhesive bonds the stiffener to the sacrificial carrier and the dielectric layer covers the supporting board; then removing the bump and a portion of the flange to form a cavity and expose the dielectric layer; then mounting a semiconductor device into the cavity; and then forming a build-up circuitry that includes a first conductive via in direct contact with the semiconductor device and provides signal routing for the semiconductor device. Accordingly, the direct electrical connection between the semiconductor device and the build-up circuitry is advantageous to high I/O and high performance, and the stiffener can provide adequate mechanical support for the build-up circuitry and the semiconductor device.

Abstract: A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

Abstract: A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. The flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer.

Abstract: A method of manufacturing is provided that includes providing a semiconductor chip device that has a circuit board and a first semiconductor chip coupled thereto. A lid is placed on the circuit board. The lid includes an opening and an internal cavity. A liquid thermal interface material is placed in the internal cavity for thermal contact with the first semiconductor chip and the circuit board.

Abstract: A chip assembly includes a PCB and a chip positioned on the PCB. The PCB includes a number of first bonding pads. Each bonding pad includes two soldering balls formed thereon. The chip includes a number of second bonding pads, and each second bonding pad corresponds to a respective first bonding pad. The two soldering balls of each first bonding pad are electrically connected to a corresponding second bonding pad via two bonding wires, and the bonding wires are bonded to the second corresponding bonding pad by a wedge bonding manner.

Abstract: A semiconductor device has an insulation substrate formed with a conductive pattern; an independent terminal, which is an externally leading terminal, soldered to the conductive pattern of the insulation substrate; a case disposed over the insulation substrate such that a top surface of the independent terminal is exposed; an opening provided on a side surface of the case; a nut glove inserted from the opening so as to be below the independent terminal, and fix the independent terminal; and a first projection part formed on a side surface of the nut glove, and having tapers in a frontward direction and a rearward direction of insertion of the nut glove, respectively. The rearward taper of the first projection part is pressure contacting with a sidewall surface of the opening.

Abstract: A wiring substrate includes a core substrate. The core substrate includes a first surface, a second surface, and an opening extending through the core substrate between the first and second surfaces. A first conductive film is formed on the first surface and covers the opening. A second conductive film is formed on the second surface. The second conductive film covers the opening. An electronic component is arranged in the opening and connected to the first conductive film. An insulator fills the opening. A first wiring portion includes alternately stacked insulative layers and wiring layers and covers the first surface of the core substrate and the first conductive film. A second wiring portion includes alternately stacked insulative layers and wiring layers, and covers the second surface of the core substrate and the second conductive film.

Abstract: A method for producing a microfluid component includes: Producing a single polymer layer made of at least one plastic or a plastic composite and having a microfluid structure, fitting the polymer layer with at least one semiconductor element, and/or with at least one electronic component, and/or with an optical or optoelectronic component, sealing the microfluid structure.

Abstract: A chip package includes a PCB, a chip positioned on the PCB and bonding wires electrically connecting the chip to the PCB. The PCB includes a number of first bonding pads formed thereon. Each first bonding pad includes a first soldering ball. The chip includes a number of second bonding pads. Each second bonding pad includes a second bonding ball. Each bonding wire electrically connects a first bonding pad to a corresponding second bonding ball. Each bonding wire forms a vaulted portion upon the first bonding ball.

Abstract: A semiconductor device includes a housing made of a thermoplastic resin and having an internal space that is opened on one side and an inner wall portion that has an inner peripheral surface defining the internal space; and a core portion engaged in the internal space of the housing. The core portion includes a substrate, a semiconductor element mounted on the substrate, a wire electrically connecting the substrate and the semiconductor element, and a mold resin sealing the substrate, the semiconductor element and the wire. The core portion has a side surface provided with a convex portion that is in contact with the inner peripheral surface of the inner wall portion. Accordingly, a semiconductor device allowing a lengthened life and improved productivity, and a method of manufacturing the semiconductor device can be provided.

Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.

Abstract: A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %.

Abstract: Methods and apparatus to inhibit cracks and delaminations in a semiconductor chip solder bump and to reduce pad parasitic capacitance are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first insulating layer over plural conductor pads of a semiconductor chip and forming an opening over each of the conductor pads. An individual solder structure is coupled to the insulating layer. The solder structure has a projection in each of the openings and in electrical contact with one of the plural conductor pads.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base carrier; forming a conductive post on the base carrier, the conductive post having a top protrusion with a protrusion top side; mounting a base integrated circuit over the base carrier; and forming a base encapsulation over the base integrated circuit, the base encapsulation having an encapsulation top side and an encapsulation recess with the conductive post partially exposed within the encapsulation recess, the encapsulation top side above the protrusion top side.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having an outer pad at a substrate top side; forming a resist layer directly on the substrate top side, the resist layer having a resist top side with a channel array adjacent the outer pad exposed from the resist layer; mounting an integrated circuit having an active side facing the resist top side, the integrated circuit having a non-horizontal side adjacent the outer pad; and forming a dielectric between the active side and the resist top side, the dielectric having a fillet extended from the non-horizontal side to the substrate top side inside an inner extent of the channel array.

Abstract: A 3D interposer (and method of making same) that includes a crystalline substrate handler having opposing first and second surfaces, with a cavity formed into the first surface. A layer of insulation material is formed on the surface of the handler that defines the cavity. The cavity is filled with a compliant dielectric material. A plurality of electrical interconnects is formed through the interposer. Each electrical interconnect includes a first hole formed through the crystalline substrate handler extending from the second surface to the cavity, a second hole formed through the compliant dielectric material so as to extend from and be aligned with the first hole, a layer of insulation material formed along a sidewall of the first hole, and conductive material extending through the first and second holes.

Abstract: A heat dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted on a chip carrier. A heat sink is mounted on the chip, and includes an insulating core layer, a thin metallic layer formed on each of an upper surface and a lower surface of the insulating core layer and a thermal via hole formed in the insulating core layer. A molding process is performed to encapsulate the chip and the heat sink with an encapsulant to form a package unit. A singulation process is performed to peripherally cut the package unit. A part of the encapsulant above the thin metallic layer on the upper surface of the heat sink is removed, such that the thin metallic layer on the upper surface of the heat sink is exposed, and heat generated by the chip can be dissipated through the heat sink.

Abstract: Provided is a highly reliable LED package with significantly improved heat radiating properties, manufacturing method of the LED package, and an LED chip assembly used in the LED package. The LED package is characterized in that the LED chip assembly (10) is bonded to a circuit board (11) created by forming metal circuitry (3) on a metal substrate (5) with an insulation layer (4) therebetween, whereas an LED chip (1) of the LED chip assembly and the metal circuitry (3) of the circuit board are connected via an electrical connection member (9), and at least the LED chip assembly and the electrical connection member are encapsulated with resin encapsulant (8) including fluorescent material.

Abstract: An electronic device includes a substrate provided with a passing opening and a MEMS device including an active surface wherein a portion of the MEMS device is integrated sensitive to chemical/physical variations of a fluid. The active surface of the MEMS device faces the substrate and is spaced therefrom, the sensitive portion being aligned to the opening. A protective package incorporates at least partially the MEMS device and the substrate, leaving at least the sensitive portion of the MEMS device, and the opening of the substrate exposed. A barrier element is positioned in an area which surrounds the sensitive portion to realize a protection structure for the MEMS device, so that the sensitive portion is free.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a single-layer support structure having a structure non-horizontal surface; forming a single-layer contact coplanar with the single-layer support structure, the single-layer contact having a contact non-horizontal surface; forming a single-layer insulation coplanar with the single-layer contact and horizontally between the structure non-horizontal surface and the contact non-horizontal surface; forming an upper support pad over the single-layer insulation and directly on the single-layer support structure; and mounting an integrated circuit over the upper support pad.

Abstract: A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A duplex plated bump on lead pad is formed over the substrate. An insulating layer is formed over the first conductive layer and the substrate. A portion of the insulating over the duplex plated bump on lead pad is removed using a laser direct ablation process. The insulating layer is a lamination layer. The duplex plated bump on lead pad has a wide bump on lead pad. A semiconductor die is mounted over the substrate. The semiconductor die has a composite conductive interconnect structure. The semiconductor die has a first bump and a second bump with a pitch ranging from 90-150 micrometers between the first bump and the second bump. A duplex plated contact pad is formed on a surface of the substrate opposite the duplex plated bump-on-lead pad.

Abstract: A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate.