Abstract: Methods for temporary wafer molding for chip-on-wafer assembly may include bonding one or more semiconductor die to an interposer wafer, applying a temporary mold material to encapsulate the bonded die, and backside processing the interposer, which may be singulated to generate assemblies comprising the bonded die, the interposer die, which may be bonded to packaging substrates. The temporary mold material may be removed and the bonded die may be tested. Additional die may be bonded to the assemblies based on the electrical testing. The interposer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The backside processing may comprise thinning the interposer wafer to expose through-silicon-vias (TSVs) and placing metal contacts on the exposed TSVs. The die may be bonded to the interposer utilizing a mass reflow or thermal compression process.

Abstract: A semiconductor device is made by forming solder bumps on a first side of a semiconductor wafer. A protective layer is formed on a second side of the semiconductor wafer opposite the first side. The protective layer can be adhesive paste, laminated film, spin-coated resin, epoxy based elastomer, organic rubbery material, polystyrene, polyethylene terephthalate, or other polymer material. The semiconductor wafer is singulated into semiconductor die. The semiconductor die is mounted to a carrier. A molding compound is formed around the semiconductor die. The protective layer provides stress relief for the semiconductor die. The protective layer is removed from the semiconductor die. The protective layer can provide a thermal dissipation, in which case it is made with metal or polymer-based material with a filler such as alumina, zinc oxide, silicon dioxide, silver, aluminum, and aluminum nitride.

Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad.

Abstract: A multifunction semiconductor package structure includes a substrate unit, a circuit unit, a support unit, a semiconductor unit, a package unit and an electrode unit. The substrate unit includes a substrate body and a first electronic element having a plurality of conductive contact portions. The circuit unit includes a plurality of first conductive layers disposed on the substrate body. The semiconductor unit includes a plurality of second electronic elements. Each second electronic element is electrically connected between two corresponding first conductive layers. The package unit includes a package body disposed on the substrate body to enclose the second electronic elements. The electrode unit includes a plurality of top electrodes, a plurality of bottom electrodes, and a plurality of lateral electrodes electrically connected between the top electrodes and the bottom electrodes.

Abstract: Methods for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die. An underfill material may be applied between the semiconductor die and the interposer die, and a mold material may be applied to encapsulate the semiconductor die. The interposer die may be thinned to expose through-silicon-vias (TSVs). The bonding of the semiconductor die may comprise adhering the semiconductor die to an adhesive layer, and bonding the semiconductor die to the interposer die. The semiconductor die may comprise micro-bumps for coupling to the interposer die, wherein the bonding comprises: positioning the micro-bumps in respective wells in a layer disposed on the interposer die; and bonding the micro-bumps to the interposer die. The semiconductor die may be bonded to the interposer die utilizing a mass reflow process or a thermal compression process.

Abstract: A method for forming a circuit pattern forming region in an insulating substrate may include preparing a metallic pattern, coating a polymer solution on a casting vessel, precuring the polymer solution, and forming an imprinted circuit pattern forming region in the precured polymer solution using the metallic pattern.

Abstract: A chip module comprises a carrier, having a first main surface and a second main surface opposite to the first main surface. A first recess structure is arranged in the carrier in the first main surface, and a chip is arranged in the first recess structure of the carrier. A patterned metallization layer is deposited on the second main surface of the carrier, the metallization layer having a first metallization structure and a second metallization structure, the first metallization structure being electrically isolated from the second metallization structure. The chip is electrically connected to the first metallization structure and the second metallization structure. The chip module comprises in particular an RFID chip and is suited to be connected to a textile substrate by way of laser reflow soldering.

Abstract: A semiconductor device includes an insulating substrate joined with a semiconductor chip, a case covering a surface of the insulating substrate where the semiconductor chip is joined, and a control terminal in which one end portion is electrically connected to the semiconductor chip, and another end portion passes through the case and is exposed to outside of the case. A portion of the control terminal exposed to the outside of the case includes a cut-out section where a part of the exposed portion is cut out, and a blocking section formed by bending a portion surrounded by the cut-out section and remaining on the control terminal. The blocking section contacts the case from the outside of the case and blocks a movement of the control terminal.

Abstract: A semiconductor package of an embodiment includes: a semiconductor chip having a signal input terminal and a signal output terminal; and a cap unit that is formed on the semiconductor chip. The cap unit includes a concave portion forming a hollow structure between the semiconductor chip and the cap unit, a first through electrode electrically connected to the signal input terminal, and a second through electrode electrically connected to the signal output terminal. Of the inner side surfaces of the concave portion, a first inner side surface and a second inner side surface facing each other are not parallel to each other.

Abstract: A semiconductor device includes a substrate comprising a stack of alternating wiring layers and insulating layers. The wiring layers include conductive wiring patterns. Primary conductive vias extend through respective ones of the insulating layers and electrically connect first ones of the wiring patterns on different ones of the wiring layers to provide electrical connections between opposing first and second surfaces of the substrate. Dummy conductive vias extend through respective ones of the insulating layers and electrically connect second ones of the wiring patterns on different ones of the wiring layers. The dummy conductive vias are arranged in the substrate around a perimeter of a region including the first ones of the wiring patterns, and the dummy conductive vias and the second ones of the wiring patterns electrically connected thereto have a same electric potential to define an electromagnetic shielding structure within the substrate.

Abstract: An electronic device includes a substrate; an element configured to be formed on the substrate; a sidewall member configured to enclose the element on the substrate; a cover member configured to be disposed on the sidewall member, and to partition a space around the element along with the sidewall member on the substrate; and a seal member configured to be disposed outside of the sidewall member, to bond the sidewall member and the cover member to a surface of the substrate, and to seal the space.

Abstract: The present disclosure provides semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board. The substrate is formed using several techniques that minimize the amount of mask levels used to form the substrate. For example, a metal substrate is patterned to form a three dimensional pattern on the surface. A dielectric material is deposited on the three dimensional pattern. Using several patterning and polishing embodiments described herein, the metal/dielectric substrate is patterned and polished to form a substantially flush surface that is bonded to the semiconductor device. In one embodiment, the top surface of the metal/dielectric substrate is patterned to expose the underlying metal substrate and the bottom surface of the metal substrate is polished to be substantially flush with the dielectric material.

Abstract: A method for fabricating an electronic device package having a column grid array is disclosed. A column grid array package includes a substrate, an integrated circuit located on a first side of the substrate, and a set of solder columns located on a second side of the substrate. The column grid array package also includes multiple two-tab electronic devices located on the second side of the substrate. The heights of the two-tab electronic devices are substantially identical to the heights of the solder columns.

Abstract: According to an embodiment, a chip package is provided, which includes: a substrate having a first surface and a second surface; a device region formed in the substrate; a passivation layer formed overlying the first surface of the substrate; at least a polymer planarization layer formed overlying the passivation layer; a package substrate disposed overlying the first surface of the substrate; and a spacer layer disposed between the package substrate and the passivation layer, wherein the spacer layer and the package substrate surround a cavity overlying the substrate, wherein the polymer planar layer does not extends to an outer edge of the spacer layer.

Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.

Abstract: Microelectronic devices, associated assemblies, and associated methods are disclosed herein. For example, certain aspects of the invention are directed toward a microelectronic device that includes a microfeature workpiece having a side and an aperture in the side. The device can further include a workpiece contact having a surface. At least a portion of the surface of the workpiece contact can be accessible through the aperture and through a passageway extending between the aperture and the surface. Other aspects of the invention are directed toward a microelectronic support device that includes a support member having a side carrying a support contact that can be connectable to a workpiece contact of a microfeature workpiece. The device can further include recessed support contact means carried by the support member. The recessed support contact means can be connectable to a second workpiece contact of the microfeature workpiece.

Abstract: A method and structures are provided for implementing enhanced thermal conductivity between a lid and heat sink for stacked modules. A chip lid and lateral heat distributor includes cooperating features for implementing enhanced thermal conductivity. The chip lid includes a groove along an inner side wall including a flat wall surface and a curved edge surface. The lateral heat distributor includes a mating edge portion received within the groove. The mating edge portion includes a bent arm for engaging the curved edge surface groove and a flat portion. The lateral heat distributor is assembled into place with the chip lid, the mating edge portion of the lateral heat distributor bends and snaps into the groove of the chip lid. The bent arm portion presses on the curved surface of the groove, and provides an upward force to push the flat portion against the flat wall surface of the groove.

Abstract: Disclosed herein is a device package that comprises a device having a top substrate that is disposed on a supporting surface of a package substrate. A package frame contacts the top surface of the top substrate and top surface of the package substrate, and hermetically seals the device between the top surfaces of the top substrate and package substrate. The device can be a semiconductor device, a microstructure such as a microelectromechanical device, or other devices.

Abstract: A radio frequency switch includes a first transmission line, a second transmission line, a first electrode electrically coupled to the first transmission line, a second electrode electrically coupled to the second transmission line, and a phase change material, the first transmission line coupled to a first area of the phase change material and the second transmission line coupled to a second area of the phase change material. When a direct current is sent from the first electrode to the second electrode through the phase change material, the phase change material changes state from a high resistance state to a low resistance state allowing transmission from the first transmission line to the second transmission line. The radio frequency switch is integrated on a substrate.

Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).

Abstract: An apparatus including a printed circuit board including a body of a plurality of alternating layers of conductive material and insulating material; and a package including a die disposed within the body of the printed circuit board. A method including forming a printed circuit board including a core and a build-up section including alternating layers of conductive material and insulating material coupled to the core; and coupling a package including a die to the core of the printed circuit board such that at least a portion of a sidewall of the package is embedded in at least a portion of the build-up section. An apparatus including a printed circuit board including a body; a computing device including a package including a microprocessor disposed within the body of the printed circuit board; and a peripheral device that provides input or output to the computing device.

Abstract: An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is plated on surfaces of a plurality of the first recesses to form a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A filler material is deposited in the first conductive structures. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive structures. A conductive material is plated on surfaces of a plurality of the second recesses to form a plurality of second conductive structures electrically coupled to, and extending parallel to the first conductive structures.

Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.

Abstract: During manufacture of an electronic device, an aerogel coating is applied to a first side of an IC substrate of a first IC. A bonding procedure is initiated, during which IC interconnects are either placed on the coated side of the substrate or on the opposite side of the substrate. The first IC is connected on a carrier to a second IC with the coated side of the first IC facing the second IC to reduce heat transmission to the second IC during operation of the first IC. The aerogel coating reduces thermal stress to the circuit board and surrounding components, reduces the risk of overheating of critical circuit components, provides chemical and mechanical insulation from contamination during subsequent wafer handling operations, and provides a thermal isolator between IC regions of dissimilar power dissipation, which isolator facilitates efficient thermal extraction from localized hotspots.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: A method for manufacturing a metal pad structure of a die is provided, the method including: forming a metal pad between encapsulation material of the die, wherein the metal pad and the encapsulation material are separated from each other by a gap; and forming additional material in the gap to narrow at least a part of the gap.

Abstract: A semiconductor device includes a first semiconductor chip; an extension formed at a side surface of the first semiconductor chip; a connection terminal formed on the first semiconductor chip; a re-distribution part formed over the first semiconductor chip and the extension and including an interconnect connected to the connection terminal and an insulating layer covering the interconnect; and an electrode formed above the extension on a surface of the re-distribution part and connected to the interconnect at an opening of the insulating layer. The electrode is mainly made of a material having an elastic modulus higher than that of the interconnect. The electrode includes a bonding region where the electrode is bonded to the interconnect at the opening, and an outer region closer to an end part of the extension. The interconnect is formed so as not to continuously extend to a position right below the outer region.

Abstract: Provided is a hybrid substrate with high density and low density substrate areas and a method of manufacturing the same. The hybrid substrate with high density and low density substrate areas includes a low density substrate layer having a cavity and a low density area, a high density substrate layer mounted in the cavity of the low density substrate layer and formed of a high density area having a higher pattern density than that of the low density area, an insulating support layer comprising a deposition area formed on upper portions, lower portions and the upper and lower portions of the high density substrate layer and the low density substrate layer, insulating layer vias passing through the deposition area of the insulating support layer and connected to patterns of the high density substrate layer and the low density substrate layer, and an outer pattern layer.

Abstract: A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins.

Abstract: The present invention relates to a semiconductor device, including: a substrate; a plurality of first semiconductor elements and a second semiconductor element arranged on a mount area of the substrate; an external electrode to supply electricity to the first and second semiconductor elements; and a frame of reflective material formed at a periphery of the mount area.

Abstract: The semiconductor module includes a base and at least one circuit substrate. The at least one circuit substrate has a supporting substrate and a semiconductor element supported by the supporting substrate. The base and/or the supporting substrate has a structure for fitting the at least one circuit substrate with the base.

Abstract: Disclosed herein are an embedded ball grid array substrate and a manufacturing method thereof. The embedded ball grid array includes: a core layer having a cavity therein; a semiconductor device embedded in the cavity of the core layer; a first circuit layer having a circuit pattern including a wire bonding pad formed thereon; a second circuit layer having a circuit pattern including a solder ball pattern formed thereon; and a wire electrically connecting the semiconductor device to the wire bonding pad.

Abstract: A 3D interposer (and method of making same) that includes a crystalline substrate handler having opposing first and second surfaces, with a cavity formed into the first surface. A layer of insulation material is formed on the surface of the handler that defines the cavity. The cavity is filled with a compliant dielectric material. A plurality of electrical interconnects is formed through the interposer. Each electrical interconnect includes a first hole formed through the crystalline substrate handler extending from the second surface to the cavity, a second hole formed through the compliant dielectric material so as to extend from and be aligned with the first hole, a layer of insulation material formed along a sidewall of the first hole, and conductive material extending through the first and second holes.

Abstract: A structure comprises a substrate comprising a plurality of traces on top of the substrate, a plurality of connectors formed on a top surface of a semiconductor die, wherein the semiconductor die is formed on the substrate and coupled to the substrate through the plurality of connectors and a dummy metal structure formed at a corner of a top surface of the substrate, wherein the dummy metal structure has two discontinuous sections.

Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.

Abstract: A semiconductor device connected by an anisotropic conductive film, the film having a storage modulus of 100 MPa to 300 MPa at 40° C. after curing of the film, and a peak point of 80° C. to 90° C. in a DSC (Differential Scanning calorimeter) profile of the film.

Abstract: A device is disclosed which includes an interposer, at least one capacitor formed at least partially within an opening formed in the interposer and an integrated circuit that is operatively coupled to the interposer. A method is disclosed which includes obtaining an interposer having at least one capacitor formed at least partially within an opening in the interposer and operatively coupling an integrated circuit to the interposer. A method is also disclosed which includes obtaining an interposer comprising a dielectric material, forming an opening in the interposer and forming a capacitor that is positioned at least partially within the opening.

Abstract: A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate.

Abstract: Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. The computer modules can also include a microelectronic package carried by the module substrate. The microelectronic package includes a semiconductor die carried by a package substrate. At least a portion of the semiconductor die extends into the substrate material via the aperture.

Abstract: A semiconductor embedded module 1 of the present invention has a configuration in which a semiconductor device 20, which is an electronic component such as a semiconductor IC (die) in a bare chip state, is embedded in a resin layer 10 (second insulating layer). In the semiconductor device 20, a redistribution layer 22 is connected to land electrodes. A protective layer 24 (first insulating layer) is provided on the redistribution layer 22, and is provided with openings such that external connection pads P of the redistribution layer 22 are exposed. Also, the resin layer 10 is formed to cover the protective layer 24, and vias V are formed at the positions of the respective external connection pads P of the redistribution layer 22. The grinding rate of the resin layer 10 is larger than that of the protective layer 24.

Abstract: In some examples, a semiconductor package can be configured to electrically couple to a printed circuit board. The semiconductor package can include: (a) a lid having one or more first electrically conductive leads; (b) a base coupled to the lid and having one or more second electrically conductive leads electrically coupled to the one or more first electrically conductive leads; (c) one or more first semiconductor devices mechanically coupled to the lid and electrically coupled to the one or more first electrically conductive leads; and (d) one or more first micro-electrical-mechanical system devices mechanically coupled to the lid and electrically coupled to the one or more first electrically conductive leads. At least one of the lid or the base can have at least one port hole. The one or more first electrically conductive leads can be configured to couple to the printed circuit board. Other embodiments are disclosed.

Abstract: A semiconductor module including a semiconductor chip having a light receiving device formed at a front thereof and a light permeable cover having a front, a back, and a side. The light permeable cover is disposed opposite to the front of the semiconductor chip such that the front of the semiconductor chip is covered by the back of the light permeable cover. The light permeable cover is provided at the outer circumferential region of the front thereof and at the side thereof with a light shielding layer. It is possible to prevent the incidence of unnecessary light from the side of the light permeable cover of a CSP and to easily adjust the distance between a lens and the front of the semiconductor chip within tolerance.

Abstract: A circuit board (1) exhibits an average coefficient of thermal expansion (A) of the first insulating layer (21) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point of equal to or higher than 3 ppm/degrees C. and equal to or lower than 30 ppm/degrees C. Further, an average coefficient of thermal expansion (B) of the second insulating layer (23) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point is equivalent to an average coefficient of thermal expansion (C) of the third insulating layer (25) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point. (B) and (C) are larger than (A), and a difference between (A) and (B) and a difference between (A) and (C) are equal to or higher than 5 ppm/degrees C. and equal to or lower than 35 ppm/degrees C.

Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.

Abstract: Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the second substrate. At least one of the substrates may include a raised feature formed under at least one of the metal layers. The two metals may for an alloy of a predefined stoichiometry in at least two locations on either side of the midpoint of the raised feature. This alloy may have advantageous features in terms of density, mechanical, electrical or physical properties that may improve the hermeticity of the seal, for example.

Abstract: A semiconductor device includes a circuit substrate which is configured with an insulative substrate formed of a ceramic material and provided on its one surface with an electrode formed of a copper material, and a power semiconductor element bonded with the electrode using a sinterable silver-particle bonding material, wherein the electrode has a Vickers hardness of 70 HV or more in its portion from the bonding face with the power semiconductor element toward the insulative substrate to a depth of 50 ?m, and has a Vickers hardness of 50 HV or less in its portion at the side toward the insulative substrate.

Abstract: Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.

Abstract: A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

Abstract: Provided is an interleaved or wavy spatial arrangement of the micro-vias providing the electrical pathways for the power and ground leads are described. The spatial arrangement increases the coupling pairs between power and ground vias or leads. This spatial arrangement is maintained even as the micro-vias transition across a plane from a direction of travel. Thus, the charge from the decoupling capacitor is able to more efficiently be delivered as the inductances are minimized through this design.