Abstract: A first via opening is formed to a first conductor and a second via opening is formed to a second conductor. The first and second via openings are formed through insulative material. Then, the first conductor is masked from being exposed through the first via opening and to leave the second conductor outwardly exposed through the second via opening. An antifuse dielectric is formed within the second via opening over the exposed second conductor while the first conductor is masked. Then, the first conductor is unmasked to expose it through the first via opening. Then, conductive material is deposited to within the first via opening in conductive connection with the first conductor to form a conductive interconnect within the first via opening to the first conductor and to within the second via opening over the antifuse dielectric to form an antifuse comprising the second conductor, the antifuse dielectric within the second via opening and the conductive material deposited to within the second via opening.

Abstract: A method for manufacturing a fuse of a semiconductor device comprises forming an island-type metal fuse in a region where a laser is irradiated, so that laser energy may not be dispersed in a fuse blowing process, thereby improving repair efficiency.

Abstract: A fuse structure, a method for fabricating the fuse structure and a method for programming a fuse within the fuse structure each use a fuse material layer that is used as a fuse, and located upon a monocrystalline semiconductor material layer in turn located over a substrate. At least part of the monocrystalline semiconductor material layer is separated from the substrate by a gap. Use of the monocrystalline semiconductor material layer, as well as the gap, provides for enhanced uniformity and reproducibility when programming the fuse.

Abstract: A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured.

Abstract: A fuse box of a semiconductor device includes a plurality of metal fuses formed on a first interlayer dielectric of a semiconductor substrate and previously removed in blowing regions thereof; a conductive oxidation layer formed to cover removed blowing regions of the metal fuses; a second interlayer dielectric formed on the first interlayer dielectric including the conductive oxide layer; and a plurality of plugs formed in the second interlayer dielectric to be brought into contact with the metal fuses which are removed in the blowing regions thereof.

Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.

Abstract: The present invention relates to a laser fuse structure for high power applications. Specifically, the laser fuse structure of the present invention comprises first and second conductive supporting elements (12a, 12b), at least one conductive fusible link (14), first and second connection elements (20a, 20b), and first and second metal lines (22a, 22b). The conductive supporting elements (12a, 12b), the conductive fusible link (14), and the metal lines (22a, 22b) are located at a first metal level (3), while the connect elements (20a, 20b) are located at a second, different metal level (4) and are connected to the conductive supporting elements (12a, 12b) and the metal lines (22a, 22b) by conductive via stacks (18a, 18b, 23a, 23b) that extend between the first and second metal levels (3, 4).

Abstract: An integrated circuit device is provided including an integrated circuit substrate having a fuse region. A window layer is provided on the integrated circuit substrate that defines a fuse region. The window layer is positioned at an upper portion of the integrated circuit device and recessed beneath a surface of the integrated circuit device. A buffer pattern is provided between the integrated circuit substrate and the window layer and a fuse pattern is provided between the buffer pattern and the window layer. Methods of forming integrated circuit devices are also described.

Abstract: A set (50) of laser pulses (52) is employed to sever a conductive link (22) in a memory or other IC chip. The duration of the set (50) is preferably shorter than 1,000 ns; and the pulse width of each laser pulse (52) within the set (50) is preferably within a range of about 0.1 ps to 30 ns. The set (50) can be treated as a single “pulse” by conventional laser positioning systems (62) to perform on-the-fly link removal without stopping whenever the laser system (60) fires a set (50) of laser pulses (52) at each link (22). Conventional IR wavelengths or their harmonics can be employed.

Abstract: A non-volatile device includes a semiconductor substrate having a fuse window region. At least one fuse crosses the fuse window region. Field regions are arranged outside of the fuse window region and arranged under end portions of the at least one fuse. An isolation layer is configured to isolate the field regions. A fuse insulating layer is interposed between the at least one fuse and the field regions.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.

Abstract: A semiconductor device having a moisture-proof dam and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating layer provided on a substrate having a fuse region. A fuse guard dam is provided on the interlayer insulating layer to surround the fuse region. A cover insulating layer is provided on the interlayer insulating layer to cover the fuse guard dam and have a fuse window exposing a middle part of the fuse region, and at least two upper extension dams are provided in the cover insulating layer to sequentially surround the fuse region and be connected to the fuse guard dam.

Abstract: Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a ?-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.

Abstract: An electrical fuse and a method for forming the same are provided. The electrical fuse includes a dielectric layer over a shallow trench isolation region and a contact plug extending from a top surface of the dielectric layer to the shallow trench isolation region, wherein the contact plug comprises a middle portion substantially narrower than the two end portions. The contact plug forms a fuse element. The electrical fuse further includes two metal lines in a metallization layer on the dielectric layer, wherein each of the two metal lines is connected to different ones of the end portions of the contact plug.

Abstract: A semiconductor device manufacturing method including forming a dummy capacitor in a fuse region to avoid a step height between plate electrodes in a cell region and in a fuse region, is disclosed herein. The method can be used so that only an insulating film at a target thickness may remain on an upper part of the plate electrode in the fuse region during an etching process for forming a fuse open region, and a fuse failure due to laser blowing can be prevented.

Abstract: A method of forming a fuse region in a semiconductor damascene process in which a specific layer is formed to prevent corrosion and re-connection of a severed part of the fuse region to prevent malfunction. A first conductive layer is formed over a substrate and an interlayer dielectric layer is deposited over the first conductive layer. A second conductive layer is buried in the interlayer dielectric layer by a dual damascene process to simultaneously form an interconnection and a fuse. The resultant structure is coated with a passivation layer. The fuse is cut to form a severed portion. A selective metal layer is deposited over the severed portion.

Abstract: Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.

Abstract: There is provided a semiconductor chip having fuses. The semiconductor chip includes fuses each having a first terminal electrically connected to a first logic circuit, a second terminal electrically connected to a second logic circuit, and a blowable region formed between the first terminal and the second terminal; and fuse residues each having the same patterns with those of the first terminal and the second terminal of the fuses, and configured so that patterns corresponded to the first terminals and the second terminals are electrically disconnected from each other.

Abstract: A semiconductor device has a programming circuit that includes an active device and a programmable electronic component. The programmable electronic component includes a carbon nanotube having a segment with an adjusted diameter. The programmable electronic component has a value that depends upon the adjusted diameter. The programming circuit also includes interconnects that couple the active device to the programmable electronic component. The active device is configured to control a current transmitted to the programmable electronic component.

Abstract: A semiconductor device includes an electric fuse formed on a semiconductor substrate and composed of an electric conductor. The electric fuse includes an upper layer interconnect, a via coupled to the upper interconnect and a lower layer interconnect coupled to the via, which are formed in different layers, respectively, in a condition before cutting the electric fuse, and wherein the electric fuse includes a flowing-out region formed of the electric conductor being flowed toward outside from the second interconnect and a void region formed between the first interconnect and the via or in the via, in a condition after cutting the electric fuse.

Abstract: A semiconductor device includes an interlayer insulating film on a substrate. A runner part includes a plurality of runner lines spaced apart from each other by a regular interval under the interlayer insulating film. A fuse cut part includes a plurality of fuse lines spaced apart from each other by a wider interval than the interval between the runner lines. A via in the interlayer insulating film connects a fuse line and a runner line to each other.

Abstract: Programmable devices, methods of manufacture thereof, and methods of programming devices are disclosed. In one embodiment, a programmable device includes a link and at least one first contact coupled to a first end of the link. The at least one first contact is adjacent a portion of a top surface of the link and at least one sidewall of the link. The programmable device includes at least one second contact coupled to a second end of the link. The at least one second contact is adjacent a portion of the top surface of the link and at least one sidewall of the link.

Abstract: A semiconductor device and methods for protecting a semiconductor device. In an example, the semiconductor device may include a semiconductor substrate including at least one electrostatic discharge (ESD) protection device, at least one metal interconnection line connected to the at least one ESD protection device through a conductive plug and a passivation layer disposed on less than all of the metal interconnection line. In an example method, a semiconductor device may be protected by diverting at least a portion of an electron build-up from an accumulation point to one or more protective circuits along one or more conductive paths, the electron build-up, without the diverting, sufficient to cause an ESD at the accumulation point. In another example, a semiconductor device may be protected by exposing one or more conductive lines to a fuse opening to avoid an ESD by diverting an electron build-up at the fuse opening to one or more ESD protection devices.

Abstract: An input protection circuit comprises a semiconductor chip, an internal circuit disposed on the semiconductor chip, a first input/output terminal which is disposed on the semiconductor chip and connected to the internal circuit, a second input/output terminal which is disposed on the semiconductor chip, connected to the internal circuit and disposed at a position adjacent to the first input/output terminal, and a fusing part which is disposed on the semiconductor chip and connected between the first and second input/output terminals.

Abstract: A method of forming a carbon nanotube fuse by depositing a carbon nanotube layer, then depositing a cap layer directly over the carbon nanotube layer. The cap layer is formed of a material that has an insufficient amount of oxygen to significantly oxidize the carbon nanotube layer under operating conditions, and is otherwise sufficiently robust to protect the carbon nanotube layer from oxygen and plasmas. A photoresist layer is formed over the cap layer, and the photoresist layer is patterned to define a desired size of fuse. Both the cap layer and the carbon nanotube layer are completely etched, without removing the photoresist layer, to define the fuse having two ends in the carbon nanotube layer. Just the cap layer is etched, without removing the photoresist layer, so as to reduce the cap layer by a desired amount at the edges of the cap layer under the photoresist layer, without damaging the carbon nanotube layer.

Abstract: A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction.

Abstract: In one embodiment a fuse region includes an insulating layer disposed on a substrate, a fuse disposed on the insulating layer and including a fuse barrier pattern and a fuse conductive pattern, which are stacked, and a supporting plug disposed beneath the fuse, and penetrating the insulating layer and the fuse barrier pattern.

Abstract: A semiconductor device includes a fuse pattern formed as conductive polymer layer having a low melting point. The fuse pattern is easily cut at low temperature to improve repair efficiency. The semiconductor device includes first and second fuse connecting patterns that are separated from each other by a distance, a fuse pattern including a conductive polymer layer formed between the first and second fuse connection patterns and connecting the first and second fuse connection patterns, and a fuse box structure that exposes the fuse pattern.

Abstract: An isolation circuit, comprising a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal, a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal, a second pad coupled to the first source/drain of the first transistor, the second pad operable to receive a ground potential, a first fuse device coupling the second source/drain terminal to a node, a second fuse device coupling the node to the first pad, a third pad operable to receive a signal to be applied to at least one die, and a second transistor operable to selectively transfer the signal received at the third pad to the at least one die in response to a control signal provided by the node.

Abstract: When the film thickness of an insulating film on a fuse connected to a circuit is not uniform within a wafer surface, there was a problem that disconnection of the fuse might become insufficient due to the insufficient intensity of a laser or disconnection of even an adjacent fuse due to excessive laser irradiation might occur. Further, a problem also occurred that after disconnection of the fuse, moisture entered from exterior through the region in which the fuse has been disconnected, so that the quality of a film underlying the fuse was adversely affected. After a SiON film, a SiN film, and a SiO2 film have been formed to cover the fuse in this stated order, etching is performed to the SiN film, which is an etching stopper film. The SiON film having a uniform and desired film thickness is thereby formed on the fuse.

Abstract: Electrically programmable integrated fuses are provided for low power applications. Integrated fuse devices have stacked structures with a polysilicon layer and a conductive layer formed on the polysilicon layer. The integrated fuses have structural features that enable the fuses to be reliably and efficiently programmed using low programming currents/voltages, while achieving consistency in fusing locations. For example, programming reliability and consistency is achieved by forming the conductive layers with varied thickness and forming the polysilicon layers with varied doping profiles, to provide more precise localized regions in which fusing events readily occur.

Abstract: A semiconductor device with a fuse 3a to be cut for a circuit modification, of which passivation film coating the uppermost wiring layer is formed in a two-layer structure including a first insulating film 11 with high filling capability and a second insulating film 12 blocking penetration of moisture or impurities. An opening 21 formed in a specific depth through the insulating films on the fuse 3a is coated by a third insulating film 13 with the blocking capability. This prevents the penetration of moisture or impurities, and the corrosion of the fuse 3a.

Abstract: A programmable fuse and method of formation utilizing a layer of silicon germanium (SiGe) (e.g. monocrystalline) as a thermal insulator to contain heat generated during programming. The programmable fuse, in some examples, may be devoid of any dielectric materials between a conductive layer and a substrate. In one example, the conductive layer serves as programmable material, that in a low impedance state, electrically couples conductive structures. A programming current is applied to the programmable material to modify the programmable material to place the fuse in a high impedance state.

Abstract: A self repairing field effect transistor (FET) device, in accordance with one embodiment, includes a plurality of FET cells each having a fuse link. The fuse links are adapted to blow during a high current event in a corresponding cell.

Abstract: The present invention relates to a phase changeable structure having decreased amounts of defects and a method of forming the phase changeable structure. A stacked composite is first formed by (i) forming a phase changeable layer including a chalcogenide is formed on a lower electrode, (ii) forming an etch stop layer having a first etch rate with respect to a first etching material including chlorine on the phase changeable layer, and (iii) forming a conductive layer having a second etch rate with respect to the first etching material on the etch stop layer. The conductive layer of the stacked composite is then etched using the first etching material to form an upper electrode. The etch stop layer and the phase changeable layer are then etched using a second etching material that is substantially flee of chlorine to form an etch stop pattern and a phase changeable pattern, respectively.

Abstract: A fuse region and a wiring region are defined on a base to form a fuse in the fuse region of the base. A first insulation film is formed on the base and the fuse. After a first contact opening is formed in the first insulation film in the wiring region, a first plug is formed by filling a conductive material in the first contact opening. A second insulation film is formed on the first insulation film. A second contact opening, in which the first plug is exposed, and a stopper opening, in which the first insulation film of the fuse region is exposed, are formed in the second insulation film. A second plug is formed by filling the second contact opening with a conductive material and a stopper film is formed by filling the stopper opening with conductive material.

Abstract: A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed between the substrate and the fuse material layer while using a self-aligned etching method, when the fuse material layer comprises lobed ends and a narrower middle region. The void is separated by a pair of sacrificial layer pedestals that support the fuse material layer. The void is encapsulated to form the cavity by using an encapsulating dielectric layer. Alternatively, a block mask may be used when forming the void interposed between the substrate and the fuse material layer.

Abstract: A fuse of a semiconductor device, and a method for forming the same, wherein the fuse includes a zigzag-shaped fuse portion on a planar structure, thereby reducing energy when the fuse is cut. The laser irradiation time can be reduced, thereby preventing fuse cutting defects and damages on a neighboring fuse. Also, a laser point where a laser is irradiated is not affected by misalignment, thereby improving characteristics of the fuse.

Abstract: A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.

Abstract: A structure and method of fabricating reversible fuse and antifuse structures for semiconductor devices is provided. In one embodiment, the method includes forming at least one line having a via opening for exposing a portion of a plurality of interconnect features; conformally depositing a first material layer over the via opening; depositing a second material layer over the first material layer, wherein the depositing overhangs a portion of the second material layer on a top portion of the via opening; and depositing a blanket layer of insulating material, where the depositing forms a plurality of fuse elements each having an airgap between the insulating material and the second material layer. The method further includes forming a plurality of electroplates in the insulator material connecting the fuse elements.

Abstract: A method for manufacturing a fuse of a semiconductor device comprises forming an island-type metal fuse in a region where a laser is irradiated, so that laser energy may not be dispersed in a fuse blowing process, thereby improving repair efficiency.

Abstract: A programmable logic device (PLD) includes electrically programmable fuses that may be programmed with an identifier of the PLD. The PLD also includes programmable tiles and an interface port that is coupled to a shift register and a subset of the programmable tiles. The interface port includes a control port and a first and second serial data signals. The shift register has a parallel input port to load the identifier from the set of electrically programmable fuses in response to a read command of the control port. The shift register serially shifts by one bit in response to a shift command of the control port, including shifting a bit from the subset of the programmable tiles to the shift register via the first serial data signal and shifting a bit from the shift register to the subset of the programmable tiles via the second serial data signal.

Abstract: A semiconductor device with a capacitor and a fuse, and a method for manufacturing the same are described. The semiconductor device comprises a semiconductor substrate having a capacitor region and a fuse region defined therein, a insulating layer over the semiconductor substrate, a storage node hole formed in the insulating layer, a barrier metal in the storage node hole, a dielectric layer formed on the barrier metal and the insulating layer, a lower metal layer for a plate electrode filling the storage node hole such that it is flush with the dielectric layer, an upper metal layer for the plate electrode on the dielectric layer and lower metal layer for the plate electrode; and a fuse metal layer formed of the same material as that of the upper metal layer for the plate electrode on the dielectric layer in the fuse region.

Abstract: An illuminating efficiency-increasable and light-erasable embedded memory structure including a substrate, a memory device, many dielectric layers, many cap layers and at least three metal layers is described. The substrate includes a memory region and a core circuit region. The memory device includes a select gate and a floating gate, and the select gate and the floating gate are disposed adjacently on the substrate in the memory region. The dielectric layers are disposed on the substrate and cover the memory device. The dielectric layers have a first opening located above the floating gate. Each of the cap layers is disposed on each of the dielectric layers, respectively. The metal layers are disposed in the dielectric layers in the core circuit region.

Abstract: As to an electromagnetic radiation detecting apparatus, a radiation detecting apparatus, a radiation detecting system and a laser processing method, a TFT is disposed on an insulating substrate. A conversion element converting electromagnetic radiation into an electric signal is disposed over the TFT. A member for marking the position of the switching element is disposed on the conversion element. The position of a switching element having a defect can be located by means of the member on the conversion element. By radiating laser light to be focused on the member, it becomes possible to perform repair accurately.

Abstract: A fuse structure (100) suitable for incorporation in an integrated circuit presents a reduced thermal conduction footprint to the substrate (103). A patterned material stack (102) is formed on a substrate (103) and at least a portion of a material disposed between the substrate (103) and an upper portion of the fuse structure (100) is selectively etched so as to reduce the thermal conduction pathway between the upper portion and the substrate (103). In a further aspect of the present invention, the reduced cross-section of the fuse structure (100) has an increased current density resulting in a lower amount of current being needed to program the fuse.

Abstract: Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.

Abstract: A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material.

Abstract: A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process.

Abstract: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.