Abstract: A method for forming a fuse in a semiconductor device comprising: forming a second insulating layer on a first insulating layer; etching the second insulating layer to form a trench; depositing a first metal layer on the trench and the second insulating layer; performing a chemical-mechanical polishing (CMP) process on the first metal layer to form the first metal wiring; forming a third insulating layer on the first metal wiring and the second insulating layer; etching the third insulating layer to form a second trench; depositing a barrier layer and a second metal layer on the second trench and the third insulating layer, and performing a CMP process on the barrier layer and the third insulating layer to form the second metal wiring; depositing a buffer layer on the second metal wiring and the third insulating layer; forming a passivation layer on the buffer layer; and etching the passivation layer.

Abstract: A method of forming an integrated circuit device can include forming a plurality of fuse wires on an integrated circuit substrate, and forming an insulating layer on the integrated circuit substrate and on the plurality of fuse wires so that the fuse wires are between the integrated circuit substrate and the insulating layer. A plurality of fuse cutting holes can be formed in the insulating layer wherein each of the fuse cutting holes exposes a target spot on a respective one of the fuse wires, and a cross-sectional area of the fuse wires can be reduced at the exposed target spots. Related structures are also discussed.

Abstract: A structure and associated method for protecting an electrical structure during a fuse link deletion by focused radiation. The structure comprises a fuse element, a protection plate, a first dielectric layer, and a second dielectric layer. The structure is formed within a semiconductor device. The protection plate is formed within the first dielectric layer using a damascene process. The second dielectric layer is formed over the protection plate and the first dielectric layer. The fuse element is formed over the second dielectric layer. The fuse element is adapted to be cut with a laser beam. The dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer. The protection plate is adapted to shield the first dielectric layer from energy from the laser beam.

Abstract: The act of blowing an unpassivated electrical fuse (for example, fuse 405) using a laser can result in the splattering of the fuse material and result in electrical short circuits. A blast barrier (for example blast barrier 406) formed around an area of the fuse that is blown by the laser helps to contain the splattering of the fuse material. The blast barrier may be formed from the same material as the fuses themselves and, therefore, can be created in the same fabrication step.

Abstract: A fuse structure for a semiconductor device on a substrate includes a fuse having an electrically conductive fuse line of a standard fuse length formed in an electrically conductive layer disposed over the substrate, and a pair of electrically conductive, inwardly bent interconnects formed in a first plurality of electrically conductive layers disposed over the substrate, below the electrically conductive layer in which the fuse line is formed. The inwardly bent interconnects couple the fuse line to a circuit area of the substrate disposed under the fuse line. The fuse structure may further include a protective guard ring formed around the fuse. The guard ring includes a second plurality of electrically conductive interconnects.

Abstract: A surface of a semiconductor substrate defined with at least one fuse area and at least one bonding pad area. A conductive layer with a thickness of 12 k? and a protective layer are sequentially formed on the surface of the semiconductor substrate. Then portions of the protective layer and portions of the conductive layer in the fuse area are etched to make the thickness for the remaining conductive layer in the fuse area be approximately 5 k?. Finally a dielectric layer is formed on the surface of the semiconductor substrate, and portions of the first dielectric layer and portions of the protective layer in the bonding pad area are etched until reaching the top surface of the conductive layer.

Abstract: The present invention relates to a method for fabricating a complementary metal oxide semiconductor (CMOS) image sensor having a redundancy module. The method includes the steps of: forming a semiconductor substrate structure including a fuse and a pad deposited respectively in a redundancy region and a pad region of a substrate and a passivation layer deposited over the semiconductor substrate structure; etching a portion of the passivation layer disposed above the pad to open the pad and simultaneously etching another portion of the passivation layer disposed above the fuse and a partial portion of the insulation layer with use of a photoresist pattern as an etch mask; forming an over coating layer (OCL) pattern on the photoresist, the OCL pattern masking the pad; etching the exposed partial portion of the insulation layer with use of the photoresist pattern as an etch mask to open and then cut the fuse; and removing the OCL pattern and the photoresist pattern.

Abstract: Methods for treating a wafer to protect a fuse box of a semiconductor chip are provided. These methods include applying an insulating coating solution onto the surface of at least one of a plurality of fuse boxes in a semiconductor chip so as to prevent moisture or impurities from seeping into the fuse box. With these methods, the degradation of the semiconductor chip can be substantially reduced by protecting the fuse box from a high-temperature and very humid atmosphere, and impurities such as particles. Thus, characteristics and reliability of the semiconductor chip can be also improved.

Abstract: An improved method for forming a fuse element is disclosed. During the formation of the upper capacitor plate in a capacitor structure, metals or their alloys are simultaneously patterned as an upper capacitor plate and as a fuse.

Abstract: A method of forming a metal fuse in a semiconductor device. In one embodiment, a specific additional mask is applied to form the metal fuse to reduce the thickness of the fuse. The method also includes forming a fuse window opening that is very shallow in the semiconductor device. The shallower opening allows for better control and removal of the remaining passivation left over the fuse during a fuse burning laser process. The thinner fuse and the thinner remaining passivation reduce the amount of laser energy required to vaporize the oxide and to cut the fuse. The location of the fuse also greatly enlarges the laser energy window that can be utilized to make laser repairs. The larger energy window results in a higher laser repair success ratio even if some deviation in the fabrication process occurs.

Abstract: The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending therethrough to the electrical nodes. The individual openings each have a periphery defined by one of the electrical nodes and at least one sidewall. One of the openings extends to the first electrical node and is a first opening, and the other of the openings extends to the second electrical node and is a second opening. A dielectric material layer is formed within the openings to narrow the openings. Conductive material plugs are formed within the narrowed openings. The conductive material plug within the first opening is a first material plug, and is separated from the first electrical node by the dielectric material; and the conductive plug within the second opening is a second material plug, and is not separated from the second electrical node by the dielectric material.

Abstract: A vertical nanotube transistor and a process for fabricating the same. First, a source layer and a catalyst layer are successively formed on a substrate. A dielectric layer is formed on the catalyst layer and the substrate. Next, the dielectric layer is selectively removed to form a first dielectric mesa, a gate dielectric layer spaced apart from the first dielectric mesa by a first opening, and a second dielectric mesa spaced apart from the gate dielectric layer by a second opening. Next, a nanotube layer is formed in the first opening. Finally, a drain layer is formed on the nanotube layer and the first dielectric mesa, and a gate layer is formed in the second opening. The formation position of the nanotubes can be precisely controlled.

Abstract: Methods and systems are provided for forming an electrical interconnect layer between two layers of an integrated circuit. The interconnect layer is formed using a material having a first electrical conductivity corresponding to a first state and a second electrical conductivity corresponding to a second state, where the first electrical conductivity is different from the second electrical conductivity. An area of the material of the interconnect layer may be selected, for example, using a mask. Then energy may be applied to the selected area to change the electrical conductivity of the material in the selected area of the interconnect layer. Thus, the present invention may be used to implement optical memory devices which may be read by an electrical circuit.

Abstract: Adjacent ones of a plurality of fuse electrodes extending parallel to each other are cut off by a laser beam. Cutting positions on the adjacent fuse electrodes are set to positions which are different from each other in a direction in which the fuse electrodes extend. Since the cutting positions on the adjacent fuse electrodes are different from each other, the adjacent fuse electrodes are prevented from being short-circuited by fragments of components thereof that are scattered when the laser beam is applied to cut off the fuse electrodes.

Abstract: A method of monitoring heat dissipation behavior of a fuse element formed in an integrated circuit structure is provided. A fuse element is fabricated in an integrated circuit structure. A plurality of resistors are formed adjacent the fuse element, wherein a resistivity of the resistors is temperature dependent. The fuse element is triggered, whereby heat is dissipated into the integrated circuit structure. A resistance change in the resistors is monitored to determine the heat dissipation behavior of the fuse element during triggering.

Abstract: A fuse layout (10) constructed of a wiring electrode made of a barrier metal layer of a high melting point and a main wiring metal layer comprises a plurality of fusion-type fuse sections (11 and 12) connected to each other in series and a plurality of fuse pads (13, 14, and 15) for drawing current to the respective fuse sections. If only one of the fuse sections is cut, the whole fuse layout is put in the “cut condition” so that the total fraction defective of incomplete cut of the fuse layout is largely reduced. Even if the barrier metal layer is not cut to remain, it has a high resistance so that the fuse resistance of the whole fuse layout becomes very high and the fuse layout is considered in the “cut condition”.

Abstract: An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first region has an N-type dopant and the second region has a P-type dopant. The polysilicon layer can also include a third region in between the first and second regions, which also has a different dopant. During a fusing event, a distribution of temperature peaks around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration of the silicide layer starts reliably within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions. An improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is realized compared to conventional polysilicon fuses.

Abstract: An uppermost interlayer isolation film is provided on a semiconductor substrate. An uppermost wire is provided on the uppermost interlayer isolation film. A silicon oxide film is provided to cover the upper surface and the side wall of the uppermost wire. A nitride film is provided on the uppermost interlayer isolation film to cover the uppermost wire through the silicon oxide film. A polyimide film is provided on the nitride film. A portion of the uppermost interlayer isolation film other than a portion located under the uppermost wire is downwardly scooped. The nitride film covers the scooped portion of the uppermost interlayer isolation film. According to the present invention, a semiconductor device improved to be capable of improving coverage of a silicon nitride passivation film is obtained.

Abstract: An active fuse includes an active fuse geometry (120) that is used to form both a variable resistor (106) and a select transistor (110). In one embodiment, the active fuse geometry is formed in a portion of an active region (160) of a semiconductor substrate (140), and a select gate (124) is disposed over an end portion (123) of the active fuse geometry to form an integral select transistor (110) for use in programming the active fuse. The use of a shared active fuse geometry within the active region allows for reduced area requirements and improved sensing margins.

Abstract: The present invention relates to a method for fabricating a complementary metal oxide semiconductor (CMOS) image sensor having a redundancy module. The method includes the steps of: forming a semiconductor substrate structure including a fuse and a pad deposited respectively in a redundancy region and a pad region of a substrate and a passivation layer deposited over the semiconductor substrate structure; etching a portion of the passivation layer disposed above the pad to open the pad and simultaneously etching another portion of the passivation layer disposed above the fuse and a partial portion of the insulation layer with use of a photoresist pattern as an etch mask; forming an over coating layer (OCL) pattern on the photoresist, the OCL pattern masking the pad; etching the exposed partial portion of the insulation layer with use of the photoresist pattern as an etch mask to open and then cut the fuse; and removing the OCL pattern and the photoresist pattern.

Abstract: Integrated circuit devices and fuse boxes have a fuse line at a fuse portion of the integrated circuit device and a first insulating layer on the fuse line. A first guard ring pattern is provided that encloses the fuse line on the first insulating layer and a second insulating layer is provided on the first guard ring pattern and the first insulating layer. A second guard ring pattern that encloses the fuse line is provided on the second insulating layer and a passivation layer is provided on the second insulating layer and the second guard ring pattern. The passivation layer defines at least a portion of a fuse opening having a sidewall in the first and second insulating layers and extends on the sidewall of the fuse opening to at least the first insulating layer.

Abstract: Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers—an overlying and underlying refractory metal nitride layer—on an insulating substrate. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure including the same materials. The fuse, which may be used to program redundant circuitry, may be blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: A method of monitoring heat dissipation behavior of a fuse element formed in an integrated circuit structure is provided. A fuse element is fabricated in an integrated circuit structure. A plurality of resistors are formed adjacent the fuse element, wherein a resistivity of the resistors is temperature dependent. The fuse element is triggered, whereby heat is dissipated into the integrated circuit structure. A resistance change in the resistors is monitored to determine the heat dissipation behavior of the fuse element during triggering.

Abstract: Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.

Abstract: A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.

Abstract: A wafer level testing and bumping process is provided. A plurality of test pads serving as testing point for testing and analyzing the circuits within the wafer is formed on the active surface of the wafer. The test pads are electrically connected to the flip-chip bonding pads respectively. The test pads are positioned on the peripheral section of the active surface. The tip of probe pins hanging from a cantilever probe card touches the test pads so that the wafer can be tested through the probe pins to obtain some test results. Whether to cut a particular fuse line underneath a fuse window by aiming a laser beam at the fuse window can be determined according to the test results. Finally, a passivation layer and bumps are formed on the active surface of the wafer and then the wafer is cut to form a plurality of single chips ready for performing subsequent packing processes.

Abstract: In a semiconductor device, an active region is formed in a semiconductor substrate separated by a plurality of isolation regions. A plurality of surface insulating films of different thickness are formed separately on the active region. A plurality of conductive films are formed on the respective insulating films. Then, one of the surface insulating film having smaller thickness is caused to break down to work as an electric fuse.

Abstract: The present invention provides a method for forming interconnect lines and conductors and passive devices in the fabrication of an integrated circuit. A gap is created in the patterning of a first layer. The gap is filled by a dielectric material so that an encapsulated conduit is formed in the gap. The encapsulated conduit is filled with a conductor by chemical vapor deposition processes or other deposition processes, the filling facilitated by forming via holes to intersect the conduit, and then filling the via holes. The conductor filled conduit can be used as a resistor, fuse, inductor, or capacitor.

Abstract: A thyristor for switching microwave signals includes semiconductor layers disposed on a substrate. A first surface of the thyristor defines an anode, and a second surface of the thyristor defines a cathode. The semiconductor layers include at least one semi-insulating layer. The thyristor transmits a microwave signal between the anode and the cathode in an ON state and blocks the microwave signal between the anode and the cathode in an OFF state.

Abstract: A configuration of fuses in a semiconductor structure having Cu metallization planes is provided. The semiconductor structure has an Al metal layer on the topmost interconnect plane for providing Al bonding pads. The fuses are configured as Al fuses and, in the semiconductor structure having Cu metallization planes, are provided above the diffusion barrier of the topmost Cu metallization plane but below a passivation layer.

Abstract: A magnetic memory cell is disclosed. The memory cell includes first conductor and second conductors coupled to first and second electrodes of a magnetic element. A plurality of memory cells is interconnected by first and second conductors to form a memory array or block. The second conductor is coupled to the second electrode via a conductive strap having a fuse portion. The fuse portion can be blown to sever the connection between the second conductor and magnetic element, Nitride.

Abstract: In an integrated circuit structure, the improvement comprising a self-passivating Cu-laser fuse characterized by resistance to oxidation and corrosion and improved adhesion in the interface between Cu and metallization lines and Cu and a dielectric cap subsequent to blowing the fuse by an energizing laser, the fuse comprising:

Abstract: A method for preventing burnt fuse pads from further electrical connection suitable before the formation of bumps on the wafer. A dielectric layer is formed over the active surface of the wafer covering the bump pads and the fuse pads of the wafer, wherein a central region of the fuse pads is burnt to form a gap which allows the material of the dielectric layer to fill up the gap. Afterwards, either a part of the dielectric layer is removed and the part of the dielectric layer covering the fuse pads remainsor a part of the dielectric layer covering the bump pads is removed. Then, an under ball metallurgy layer is formed on the bump pads of the wafer so that the material of the under ball metallurgy layer does not cover the two sides of the fuse pad at the same time, or fill into the gap. As a result, the electrical isolation still remains.

Abstract: A complementary metal oxide semiconductor (CMOS) fabrication process. The process comprises creating a polysilicon layer having a first thickness for a transistor gate area and a second thickness for a fuse area. The first thickness is greater than the second thickness, wherein most of the polysilicon in the fuse area will react with a metal layer to form polysilicide during a rapid thermal anneal (RTA) process.

Abstract: A method and a circuit arrangement for protecting integrated circuits against electrostatic discharge (ESD) during and after packaging. An electrical connection between two integrated circuits is made by producing a low-impedance connection in the first integrated circuit, between a signal pad and a pad for a supply potential. The connection has a portion of reduced cross section, which is preferably severed by a current pulse applied after the arrangement has been assembled in a package and the connection has been electrically bonded to the second integrated circuit. The ESD protection during assembly requires no additional chip surface area.

Abstract: A copper fuse structure and the method for fabricating the same is disclosed in this present invention. By employing an inner copper metal layer as a fuse, the copper fuse according to this invention can be easily zipped with a laser repair tool. Furthermore, the openings on a bonding pad and the fuse of the semiconductor structure can be identified with the method according to this invention. Moreover, in contrast of the fuse formed with an upper aluminum layer in the prior art, the cost of the fuse manufacturing is lower in the method according to this invention by fabricating the fuse with an inner copper layer.

Abstract: A method of forming a metal fuse comprising the following steps. A structure is provided having exposed adjacent metal structures. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having via openings 2exposing at least a portion of the exposed adjacent metal structures. A metal fuse portion is formed between at least two of the adjacent metal structures without additional photolithography, etch or deposition processes. The metal fuse portion including a portion having a nominal mass and a sub-portion of the portion having a mass less than the nominal mass so that the metal fuse portion is more easily disconnected at the less massive sub-portion during programming of the metal fuse portion.

Abstract: Methods and systems are provided for forming an electrical interconnect layer between two layers of an integrated circuit. The interconnect layer is formed using a material having a first electrical conductivity corresponding to a first state and a second electrical conductivity corresponding to a second state, where the first electrical conductivity is different from the second electrical conductivity. An area of the material of the interconnect layer may be selected, for example, using a mask. Then energy may be applied to the selected area to change the electrical conductivity of the material in the selected area of the interconnect layer. Thus, the present invention may be used to implement optical memory devices which may be read by an electrical circuit.

Abstract: A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications.

Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

Abstract: A method of fabrication used for semiconductor integrated circuit devices to define a thin copper fuse at a top via opening, in a partial etch, dual damascene integration scheme, efficiently reducing top metal thickness in a fusible link, for the purpose of laser ablation. Some advantages of the method are: (a) avoids copper fuse contact to low dielectric material, which is subject to the thermal shock of laser ablation, (b) increases insulating material thickness over the fuse using better thickness control, and most importantly, (c) reduces the copper fuse thickness, for easy laser ablation of the copper fuse, and finally, (d) uses USG, undoped silicate glass to avoid direct contact with low dielectric constant materials.

Abstract: In a wafer, a plurality of basic chips F is arranged therein. The basic chip F has a memory capacity of i-mega bytes. By dicing, a memory chip including four basic chips F is cut out of the wafer. The memory chip has a memory capacity of 4×i-mega bytes. A Dicing line is interposed between four basic chips F configuring the memory chip. Four basic chips F can change a word organization by a control signal individually.

Abstract: A method of forming a fuse structure in which passivating material over the fuse has a controlled, substantially uniform thickness that is provided after C4 metallurgy formation. A laser fuse deletion process for the fuse formed by this method is also disclosed.

Abstract: A fuse structure and method for fabricating same are disclosed. The fuse structure is designed for opening by conventional laser energy application. The fuse structure is characterized by an absence of high stress areas in the surrounding substrate thereby resulting in higher fabrication yields due to lower occurrence of substrate fracturing or other damage occasioned by the opening of the fuse.

Abstract: Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads. Also disclosed is the apparatus made from the method.

Abstract: The present invention provides methods of forming fuse box guard rings for integrated circuits and integrated circuit devices having the same. A fuse line is formed at a fuse portion of an integrated circuit device and a first insulating layer is formed on the fuse line. A guard ring pattern that encloses the fuse line is formed on the first insulating layer. A second insulating layer is formed on the guard ring pattern and the first insulating layer. The second insulating layer is partially etched to remove a portion of the second insulting layer in the fuse portion of the integrated circuit device enclosed by the guard ring pattern exposing a portion of the first insulating layer and to form a via hole in a peripheral circuit region of the integrated circuit device.

Abstract: A structure for using fuse structure integrated wire bonding on the substrate, and relates to methods for making the same are disclosed, in which an Al-fuse has an extra-etching process pattern by fuse-open mask and has been thinned down from Al-fuse thickness. The Al fuse structure integrated Al wire-bonding pad has two kind of thickness under fuse-open and for the other area. This invention makes the fuse easy to blow without suffering any bondability from wire bonding for packaging.

Abstract: A method is provided for forming a device. The method provides a substrate, and provides a plurality of nanotubes in contact with the substrate. The method comprises depositing metal contacts on the substrate, wherein the metal contacts are in contact with a portion of at least one nanotube. The method further comprises selectively breaking the at least one nanotube using an electrical current, removing the metal contacts, cleaning a remaining nanotube, and depositing a first metal contact in contact with a first end of the nanotube and a second metal contact in contact with a second end of the nanotube.

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: An electronic device having stacked modules and method for producing it are described. Each module has a chip. Each chip is mounted on a stack intermediate plane. The stack intermediate planes of a stack have identical layouts, while chip select circuits which can be set irreversibly via contact areas are disposed on the chips, which chip select circuits enable an irreversible assignment of the contact areas to the stack intermediate planes.