Abstract: A programmable phase change material (PCM) structure includes a heater element formed at a BEOL level of a semiconductor device, the BEOL level including a low-K dielectric material therein; a first via in electrical contact with a first end of the heater element and a second via in electrical contact with a second end of the heater element, thereby defining a programming current path which passes through the first via, the heater element, and the second via; a PCM element disposed above the heater element, the PCM element configured to be programmed between a lower resistance crystalline state and a higher resistance amorphous state through the use of programming currents through the heater element; and a third via in electrical contact with the PCM element, thereby defining a sense current path which passes through the third via, the PCM element, the heater element, and the second via.

Abstract: A redundant fuse is provided with a redundant length, here a winding structure, at one end thereof, here at a vicinity of a second wire side to which a high voltage (Vcc) is impressed. A disconnected portion is provided between the other end side of the redundant fuse, here a second wire side which is on the ground potential (GND) and the winding structure.

Abstract: A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.

Abstract: A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material.

Abstract: A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.

Abstract: Provided are a semiconductor device which substantially prevents repair failure and a method of manufacturing the same. The semiconductor device includes a plurality of first fuses formed apart from each other on a semiconductor substrate, and on which a protective layer is formed; a first insulating layer filled in between the first fuses and configured to expose the protective layer; a plurality of second fuses formed between the first fuses and on the first insulating layer; and a second insulating layer formed on the first insulating layer, wherein the second insulating layer includes a fuse window configured to fully expose the second fuses and the protective layer formed on the first fuses.

Abstract: A set (50) of laser pulses (52) is employed to sever a conductive link (22) in a memory or other IC chip. The duration of the set (50) is preferably shorter than 1,000 ns; and the pulse width of each laser pulse (52) within the set (50) is preferably within a range of about 0.1 ps to 30 ns. The set (50) can be treated as a single “pulse” by conventional laser positioning systems (62) to perform on-the-fly link removal without stopping whenever the laser system (60) fires a set (50) of laser pulses (52) at each link (22). Conventional IR wavelengths or their harmonics can be employed.

Abstract: Embodiments of the invention relate to efficient formation of improved fuses and fuse arrays, such as can be used in memory devices for example, by use of a printer that transfers material to a flexible substrate. In one embodiment, a fuse is printed using an inkjet printer on a flexible substrate fed therethrough, by depositing droplets of conductive material. The droplets form a weak portion and one or more main portions. In one embodiment, the fuse may comprise a single metal material. In additional embodiments, an array of fuses can be printed by an inkjet printer in layers for use as digital memory. For example, a layer can be printed that forms fuse elements and word address conductors, an insulating layer can be printed over the fuses but leaving a window portion exposed, and a third layer can be printed over the window portions to provide bit address conductors.

Abstract: A method for making a semiconductor device having a fuse window above a substrate is disclosed. The semiconductor device has at least one fuse protection circuit located under the fuse window. The fuse protection circuit includes a fuse having a first end connected to a first voltage and a second end. A first transistor having a drain is connected to the second end of the fuse, a gate for receiving an input signal, and a source is connected to a second voltage. A second transistor having a drain is connected to the second end of the fuse, a gate, and a source is connected to the second voltage. A first diode having an anode and a cathode, the anode of the first diode is connected to the second voltage and the cathode of the first diode is connected to the second end of the fuse. A second diode having an anode and a cathode, the anode of the second diode is connected to the second end of the fuse and the cathode of the second diode is connected to the first voltage.

Abstract: A semiconductor device comprising a programming circuit that includes an active device on or in a substrate and a programmable electronic component on the substrate. The programmable electronic component includes at least one carbon nanotube having a segment with an adjusted diameter. The programmable electronic component has a value that depends upon the adjusted diameter. The programming circuit also includes interconnects that couple the active device to the programmable electronic component. The active device is configured to control a current transmitted to the programmable electronic component.

Abstract: An electronic device is disclosed having a dielectric layer (12) formed at a semiconductor substrate (10). A polysilicon fuse structure (14) having a first length is formed overlying the dielectric layer (12). First and second portions (141, 142) of the polysilicon fuse structure are silicided, wherein a third portion (143) of the polysilicon fuse structure (114) that abuts the first portion (141) and the second portion (142) of the polysilicon fuse remains unsilicided.

Abstract: An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.

Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).

Abstract: A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contact is made long enough so that it makes contact at each end with a metal layer, but design rule spacing is still maintained between the connections with the metal layer. The overlapping areas between the rectangular contact and the metal layers are asymmetrical. Alternatively, these overlapping areas are smaller than the design rule overlap requirements. In a second embodiment, a fuse element is constructed with a plurality of rectangular-shaped contacts. As a result, a current value that is significantly lower than conventional fuse current values, can be used to melt such a contact or blow the fuse.

Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.

Abstract: A fuse for use in a semiconductor device includes spaced-apart terminals with at least two layers of conductive material and a single-layer conductive link joining the spaced-apart terminals and including a single layer of conductive material. A first, lower layer of the terminals of each fuse may be formed from conductively doped polysilicon. The second, upper layer of each fuse terminal may be formed from a polycide, a metal silicide, a metal, or a conductive alloy. The conductive link of each fuse may be formed from either the material of the first layer or the material of the second layer. Methods for fabricating the fuse include forming the first and second layers and patterning the first and second layers so as to form a fuse with the desired structure.

Abstract: An integrated circuit device is provided including an integrated circuit substrate having a fuse region. A window layer is provided on the integrated circuit substrate that defines a fuse region. The window layer is positioned at an upper portion of the integrated circuit device and recessed beneath a surface of the integrated circuit device. A buffer pattern is provided between the integrated circuit substrate and the window layer and a fuse pattern is provided between the buffer pattern and the window layer. Methods of forming integrated circuit devices are also described.

Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.

Abstract: A method for programming a laser fuse. The laser fuse has a fuse link including a material having a characteristic of changing its electrical resistance after being exposed to a laser beam. The laser beam is directed to the fuse link, the laser beam being controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off.

Abstract: An input protection circuit comprises a semiconductor chip, an internal circuit disposed on the semiconductor chip, a first input/output terminal which is disposed on the semiconductor chip and connected to the internal circuit, a second input/output terminal which is disposed on the semiconductor chip, connected to the internal circuit and disposed at a position adjacent to the first input/output terminal, and a fusing part which is disposed on the semiconductor chip and connected between the first and second input/output terminals.

Abstract: A fuse box includes a semiconductor substrate having a fuse region, and a lower line in the fuse region that has a first region and a second region. An upper line is placed on the upper part of the lower line to overlap the first region. A fuse is placed on the upper part of the upper line, and connects electrically to the second region of the lower line and the upper surface of the upper line. A lower interlayer insulating layer is interposed between the lower line and the upper line, and an upper interlayer insulating layer is interposed between the upper line and the fuse. The fuse is formed on the upper interlayer insulating layer. Both ends of the fuse connect electrically to the second region of the lower line and the upper line, respectively, through fuse holes penetrating the lower and upper interlayer insulating layers.

Abstract: A semiconductor device has a semiconductor substrate, first and second insulating layers, a fuse, a diffusion layer and a conductive pattern. The first insulating layer is selectively formed on a surface of the semiconductor substrate. The fuse is formed on the first insulating layer. The diffusion layer is formed on the surface of the semiconductor substrate. The diffusion layer is applied to a fixed potential. The second insulating layer is formed on the fuse. The conductive pattern is formed on the second insulating layer. The conductive pattern surrounds the fuse. Further, the conductive pattern is electrically connected to the diffusion layer.

Abstract: A specially shaped laser pulse energy profile characterized by different laser wavelengths at different times of the profile provides reduced, controlled jitter to enable semiconductor device micromachining that achieves high quality processing and a smaller possible spot size.

Abstract: A semiconductor structure having an efficient thermal path and a method for forming the same are provided. The semiconductor structure includes a protection ring over a semiconductor substrate and substantially encloses a laser fuse structure. The laser fuse structure includes a laser fuse and a connection structure connecting the fuse to integrated circuits. The protection ring is thermally coupled to the semiconductor substrate by contacts. The semiconductor structure further includes a metal plate conducting heat generated by a laser beam to the protection ring.

Abstract: A semiconductor device, capable of improving integration density and solving problems that may occur in a laser repair process, and a method of fabricating the same are provided. A fuse circuit is formed in a cell region, not in a peripheral region, and thus it is possible to reduce the size of a semiconductor chip.

Abstract: The present invention provides electrically-programmable fuse structures having radiation inhibitive properties for preventing non-destructive security breaches by radiation imaging techniques such as X-ray imaging, without adversely effecting fuse programmability, and methods of designing the same.

Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

Abstract: A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopant region that is located within the semiconductor substrate. The present invention also provides a method of fabricating such a semiconductor structure in which the embedded e-fuse is formed substantially at the same time with the trench isolation regions.

Abstract: A fuse element has a first region, a second region and a third region. The first region is a portion for isolating circuitry. The second region and the third region are respectively connected to both ends of the first region and have a wider pattern width than that of the first region. The second region, the first region and a part of the third region of the fuse element are formed on a thick insulating film, while the remaining part of the third region is formed on a thin insulating film. Heat generated in the fuse element is less likely to be released to a semiconductor substrate through the thick insulating film, but is more likely to be released to the semiconductor substrate through the thin insulating film. The fuse element therefore has a large temperature change and a large temperature gradient. This facilitates electrical blowing of the first region.

Abstract: A semiconductor device wherein return wires corresponding to a plurality of fuse wires are arranged collectively in the same region. Moreover, the return wires are arranged in multiple layers. This arrangement creates a region where no return wire is disposed between the fuse wires, thereby permitting an arrangement of the fuse wires at the minimum wiring pitch. Alternatively, the semiconductor device may include fuse strings arranged in a plurality of stages and a plurality of connection wires for supplying signals to the fuse strings in the plurality of stages, respectively, wherein connection wires for other fuse strings are arranged in a region between adjacent fuse strings.

Abstract: A method for making a one time programmable (OTP) memory array includes providing a wafer comprising a buried insulator layer and a semiconductor layer over the buried insulator layer and forming a plurality of bit lines in the semiconductor layer. Each of the plurality of bit lines comprise a portion of the semiconductor layer and the plurality of bit lines are separated from each other by isolation regions formed in the semiconductor layer. The method further includes forming an anti-fuse dielectric layer over and in physical contact with the plurality of bit lines and the isolation regions, and forming a plurality of word lines over and in physical contact with the anti-fuse dielectric layer.

Abstract: A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline body, such as an oxide. The body may be doped, and may also include a silicide layer on the upper surface. This fuse structure may be successfully programmed over a wide range of programming voltages and time.

Abstract: In a fuse region of a semiconductor device, and a method of fabricating the same, the fuse region includes an interlayer insulating layer on a semiconductor substrate, a plurality of fuses on the interlayer insulating layer disposed in parallel with each other, a blocking layer on the interlayer insulating layer between each of the plurality of fuses and in parallel with the plurality of fuses, and a plurality of fuse grooves recessed into the interlayer insulating layer between each of the plurality of fuses and the blocking layer.

Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.

Abstract: A method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalize an integrated circuit by means of at least one laser via in a layer at least partially covering the circuit. The component comprises a rewiring of the contact pads. The inventive method comprises the following steps: each laser via is closed by means of a separate covering layer which is to be applied locally; a rewiring extending between the local covering layers is created; the local covering layers are removed; and the laser-induced correction is carried out by means of the open laser vias.

Abstract: Tolerance to ESD is increased in an electronic fuse by providing at least one non-conductive region adjacent to a conductive region on the surface of an insulator. Such an arrangement reduces the thermal stresses imposed on the insulator in high current applications. Where multiple conductive and adjacent non-conductive regions are disposed on an insulator, the fuse can fail in discrete steps, thus providing a well defined and easily detected transisition to a blown state, as well as providing a stepwise increase in resistance between prescribed resistance values.

Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film, etching the aluminum layer to form a bonding pad and fuse elements, depositing by plasma chemical vapor deposition a second insulating film covering the bonding pad and the fuse elements, the second insulating film having planar portions between the fuse elements and ridged portions opposite the fuse elements, depositing by plasma chemical vapor deposition a third insulating film covering the second insulating film, etching the third insulating film to form a first hole exposing a first region of the second insulating film, opposite the fuse elements, and a second hole exposing a second region of the second insulating film, opposite at least part of said bonding pad, and etching the second insulating film to form a third hole exposing at least part of the bonding pad.

Abstract: A method and system position a laser beam spot relative to a semiconductor substrate having structures on or within the semiconductor substrate to be selectively processed by delivering a processing laser beam to a processing laser beam spot. The method generates a metrology laser beam and propagates the metrology laser beam along a propagation path to a metrology laser beam spot on or near a structure to be selectively processed. The method detects a reflection of the metrology laser beam from the structure, thereby generating a reflection signal, and determining, based on the reflection signal, a position of the metrology laser beam spot relative to the structure.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device comprises a fuse bank with a fuse window, a pad area with a pad window, and a composite passivation layer comprising a sacrificial dielectric layer and a final passivation layer. Both the fuse window and the pad window have a bottom portion and two sidewalls, and the composite passivation layer covers both the fuse bank and the pad area except for the bottom portions of the fuse bank and the pad area.

Abstract: An improved fuse link structure and fuse blowing method, the fuse-link structure including a plurality of elongated fuse-link members comprising polysilicon electrically connected in parallel according to a common input Voltage contact and common output current contact to form a fuse-link structure; and, wherein at least a portion of the plurality of elongated fuse-link comprise a different electrical resistance with respect to one another according to a variable condition selected from the group consisting of critical dimension, polysilicon doping condition, and silicide agglomeration condition.

Abstract: An integrated circuit device is provided with a plurality of normally open fuse elements. A fuse element includes a fuse insulation film lining a sidewall and a bottom of a recess in a semiconductor substrate. A semiconductor fuse region of first conductivity type (e.g., N-type) is provided in the semiconductor substrate. The semiconductor fuse region extends to the sidewall of the recess. A fuse conductor is provided on a portion of the fuse insulation film extending opposite the semiconductor fuse region. A voltage induced rupture in the fuse insulation film results in a direct electrical connection between the fuse conductor and the semiconductor fuse region.

Abstract: A method of making a nanostructure array including disposing a masking material on a nanoporous template such that a first number of the plurality of nanopores are fully coated while a second number of the plurality of nanopores are not-fully coated by the masking material is provided. The method includes forming the nanostructures within the plurality of nanopores that are not-fully coated by the masking material. A nanostructure array fabricated in accordance to above said method and devices based on the nanostructure array is also provided.

Abstract: A metal layer structure is disclosed. The metal layer structure includes a substrate, a first dielectric layer on a surface of the substrate, and at least one first conductor and at least one second conductor on the first dielectric layer. The second conductor has at least one thin portion.

Abstract: Various methods and systems measure, determine, or align a position of a laser beam spot relative to a semiconductor substrate having structures on or within the semiconductor substrate to be selectively processed by delivering a processing laser beam to a processing laser beam spot. A metrology laser beam spot is directed to one or more of those structures to be selectively processed (e.g., laser-severable conductive links), and reflections of the metrology laser beam off of those structures to be selectively processed are detected to perform the measurement, determination, or alignment. The processing laser beam can then be accurately directed onto those structures to process them on a selective basis. The various methods and systems thus utilize those structures themselves—rather than relying exclusively on dedicated alignment markers—to perform the measurement, determination, or alignment.

Abstract: A semiconductor device includes an electric fuse formed on a semiconductor substrate and composed of an electric conductor. The electric fuse includes an upper layer interconnect, a via coupled to the upper interconnect and a lower layer interconnect coupled to the via, which are formed in different layers, respectively, in a condition before cutting the electric fuse, and wherein the electric fuse includes a flowing-out region formed of the electric conductor being flowed toward outside from the second interconnect and a void region formed between the first interconnect and the via or in the via, in a condition after cutting the electric fuse.

Abstract: Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

Abstract: A semiconductor device comprises a multiple insulation layer structure in which multiple insulation layers each having interconnection layer are built up and either one of the interconnection layer forming a fuse is blown in order to select a spare cell to relieve a defective cell; and an opening area corresponding to said fuse, the opening being formed on one or more insulation layers disposed above the layer which includes the fuse, wherein a side wall position corresponding to the opening of the first protective insulation film formed on the top layer of the multiple layers and a side wall position corresponding to the opening of the second protective insulation film formed on the first protective insulation film are continuous at the boundary thereof.

Abstract: Disclosed are methods of fabricating a semiconductor device, by which the pad and fuse layers play their roles smoothly and to enhance a quality of a final semiconductor device. According to one example, a disclosed method includes forming an insulating layer covering a pad and a fuse on prescribed portions of a substrate, simultaneously forming a first trench exposing an anti-reflective coating layer provided as a top layer of the pad and a second trench having a portion of the insulating layer underneath over the fuse by selectively removing the first insulating layer, filling up the first and second trenches with an etch rate adjustment layer, exposing the anti-reflective coating layer to leave a portion of the etch rate adjustment layer within the second trench by selectively removing the etch rate adjustment layer, and simultaneously removing the anti-reflective coating layer and the portion of the etch rate adjustment layer from the second trench.

Abstract: A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

Abstract: Provided are a semiconductor device which substantially prevents repair failure and a method of manufacturing the same. The semiconductor device includes a plurality of first fuses formed apart from each other on a semiconductor substrate, and on which a protective layer is formed; a first insulating layer filled in between the first fuses and configured to expose the protective layer; a plurality of second fuses formed between the first fuses and on the first insulating layer; and a second insulating layer formed on the first insulating layer, wherein the second insulating layer includes a fuse window configured to fully expose the second fuses and the protective layer formed on the first fuses.