Abstract: A method for fabricating a thin film transistor (TFT) is provided. The method includes steps of a) providing an insulation substrate, b) forming a conductive layer on the insulation substrate, c) defining the conductive layer as a gate conducting structure by a first photolithography and etch process, d) forming a gate insulation layer, a channel layer, a junction layer, a source/drain layer and a data line layer in sequence, and etching the data line layer, the source/drain layer and the junction layer by a second photolithography and etch process to form a source/drain structure and a data line structure, and e) heat-treating the junction layer to reduce resistance between the source/drain structure and the channel layer.

Abstract: A semiconductor device comprising: an SOI substrate having a surface semiconductor layer, a gate electrode formed on the surface semiconductor layer via a gate insulating film, first conductive type source/drain regions formed in the surface semiconductor layer of both sides of the gate electrode, a second conductive type drawing diffusion layer formed in the surface semiconductor layer and contacted with at least one of the first conductive type source/drain regions, and a silicide layer which is formed on the surface semiconductor layer to partially or entirely overlie both said at least one of source/drain regions and the drawing diffusion layer, the silicide layer being grounded.

Abstract: There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention isolates a semiconductor substrate by an oxide layer with only a source, a drain and a channel region necessary for driving a transistor being left. Thus, it can obviate the current components due to parasitic factors to improve the punch-through characteristic.

Abstract: There has been a case where peeling occurs if an internal stress of a wiring of a TFT is strong. In particular, the internal stress of a gate electrode largely influences a stress that a semiconductor film receives, and there has been a case where the internal stress becomes a cause of reduction in electric characteristics of a TFT depending on the internal stress. According to the present invention, an impurity element is introduced into a wiring, or both the introduction of an impurity element and heat treatment are performed, whereby the wiring can be controlled to have a desired internal stress. It is effective that the present invention is particularly applied to a gate electrode. Further, it is possible that the introduction of an impurity element and the heat treatment are conducted to only a desired region to conduct control to attain a desired internal stress.

Abstract: An image display device has an image display section including an insulating substrate having a matrix of pixels formed on an inner surface thereof and a liquid crystal layer sandwiched between the insulating substrate and a substrate opposing the insulating substrate. The image display device includes signal lines, driver circuits for driving the matrix of pixels via the signal lines, voltage amplifiers formed by polycrystalline semiconductor TFTs and each coupled between one of the signal lines and a corresponding one of the driver circuits. The signal lines, the driver circuits and the voltage amplifiers are formed on a surface of the insulating substrate on a side thereof facing the liquid crystal layer. A channel, a source and a drain of the polycrystalline semiconductor TFTs each are formed of a polycrystalline semiconductor film. A gate insulating film and a gate electrode are superposed on the polycrystalline semiconductor film in the order named.

Abstract: In producing a thin film transistor, after an amorphous silicon film is formed on a substrate, a nickel silicide layer is formed by spin coating with a solution (nickel acetate solution) containing nickel as the metal element which accelerates (promotes) the crystallization of silicon and by heat treating. The nickel silicide layer is selectively patterned to form island-like nickel silicide layer. The amorphous silicon film is patterned. A laser light is irradiated while moving the laser, so that crystal growth occurs from the region in which the nickel silicide layer is formed and a region equivalent to a single crystal (a monodomain region) is obtained.

Abstract: Two kinds of TFTs are fabricated by the same process with a high production yield to manufacture an active-matrix circuit and a peripheral driver circuit on the same substrate. The active-matrix circuit is required to have a high mobility and a high ON/OFF current ratio. The peripheral driver circuit needs a complex interconnection structure. The active-matrix circuit and the peripheral driver circuit comprising the TFTs are fabricated monolithically. In this step, the gate electrodes of the TFTs of the active-matrix circuit is coated with an anodic oxide on their top and side surfaces. The gate electrodes of the TFTs of the peripheral driver circuit is coated with the anodic oxide on only their top surfaces; substantially no anodic oxide is present on the side surfaces.

Abstract: A decoupling capacitor and methods for forming the same are provided. In a first aspect, the decoupling capacitor is formed during a process for forming first and second type FETs on a common substrate that comprises a plurality of implant steps for doping channels and diffusions of the first and second type FETs. In a second aspect, a method is provided for forming the novel decoupling capacitor that includes the steps of forming a mandrel layer on a substrate, including forming openings in the mandrel layer and disposing a first type dopant into the substrate through the openings. Thereafter, an epitaxial layer is formed in the openings on the substrate, an insulator layer is formed in the openings on the epitaxial layer and a gate is formed in the openings on the insulator layer. The mandrel layer is removed and the first type dopant is disposed into the substrate abutting the first type dopant in the substrate that was disposed through the openings.

Abstract: An auxiliary capacitor for a pixel of an active matrix type liquid crystal display is provided without decreasing the aperture ratio. A transparent conductive film for a common electrode is formed under a pixel electrode constituted by a transparent conductive film with an insulation film provided therebetween. Further, the transparent conductive film for the common electrode is maintained at fixed potential, formed so as to cover a gate bus line and a source bus line, and configured such that signals on each bus line are not applied to the pixel electrode. The pixel electrode is disposed so that all edges thereof overlap the gate bus line and source bus line. As a result, each of the bus lines serves as a black matrix. Further, the pixel electrode overlaps the transparent conductive film for the common electrode to form a storage capacitor.

Abstract: A SRAM memory cell including two tunnel diodes coupled in series and a MOS FET. first of the tunnel diodes may be formed in a shallow trench. A second of the tunnel diodes may be formed in a source or drain contact region of the FET. The FET acts as a pass gate to allow data to be read from or written to the memory cell when the gate of the FET is biased to turn the FET ON. The FET otherwise acts to prevent the datum stored in the memory cell from being altered when the FET is turned OFF. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.

Abstract: An electrooptical substrate device has pixel electrodes and pixel-switching TFTs connected thereto, on a substrate. The TFT is a P-channel TFT of an SOI structure that does not have a body contact. Due to this, a transistor is architected in each pixel that is suited to broaden the opening area in each pixel, and having comparatively high performance, thereby enabling bright, high-quality image display.

Abstract: An improved method and structure for a transistor device with a lateral drift region and a conducting top field plate is presented. The method consists of decreasing the gate to drain capacitance by means of decreasing the portion of the field plate that is connected to the gate electrode, and hence the effective overlap of the gate with the drift region and drain. This results in decreased energy dissipation in switching the transistor, and more efficient operation. The rate of decrease of the gate to drain capacitance is even faster at higher drain voltages, inuring in significant energy efficiencies in high voltage applications.

Abstract: A method of manufacturing a liquid crystal panel comprises the steps of forming a gate insulating film, a channel layer and an etching stopper layer on a transparent substrate bearing a gate electrode, exposing the substrate to light from its back surface side by using the gate electrode as a light shielding mask by photolithography, developing the resist, etching the etching stopper layer, forming a source/drain layer, and etching the source/drain layer and a remaining part of the etching stopper by chemical gas phase etching.

Abstract: RD-25953-17-A method of fabricating an imager array having a plurality of pixels is provided in which each pixel is made up of a photodiode and a corresponding thin film transistor (TFT) switching device, the method including the steps of depositing materials to form the photodiode island and to form a TFT body over a gate electrode, then depositing a layer of source/drain metal over the silicon layers of the TFT body, and over a common dielectric layer, removing sections of the source/drain metal layer to expose a portion of the silicon layers of the TFT body, but leaving regions of sacrificial source/drain metal over the photodiode islands, and forming a back channel in the TFT body by a back channel etch step. The method further includes then removing the sacrificial regions of source/drain metal from above the photodiode islands, and depositing a passivation layer over the entire exposed surface of the array.

Abstract: A method for forming a semiconductor device that has a fully depleted MOSFET and a partially depleted MOSFET having excellent characteristics on the same substrate without effecting control by means of the impurity concentration of the channel region. A semiconductor device is provided with a fully-depleted SOI MOSFET and a partially-depleted SOI MOSFET on the same SOI substrate through isolation by an element isolation film. The SOI substrate includes a buried oxide film and a SOI layer provided in succession on a silicon substrate.

Abstract: A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

Abstract: In a semiconductor device manufacturing process, a gate insulating film forming step, an amorphous semiconductor film forming step, a crystallizing step and an etch stopper insulating film forming step are continuously performed without exposing the atmosphere.

Abstract: The present invention provides a MOS (metal-oxide-semiconductor) transistor with two empty side slots on its gate and method for forming the same. The MOS transistor comprises a substrate, an insulation layer, a gate and a dielectric layer. The substrate has a surface layer which comprises a drain and a source separately positioned on two separate areas of the surface layer. The insulation layer positioned on the surface of the substrate between the drain and the source. The gate comprises a conducting layer positioned on the insulation layer having a bottom side, a top side, a left side and a right side, and a metallic silicide layer positioned on the top side of the conducting layer for reducing resistance of the conducting layer wherein the width of the metallic silicide layer is greater than that of the bottom side of the conducting layer. The dielectric layer covers the drain, the source and the metallic silicide layer.

Abstract: A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1−xGex, layer on the Si substrate, and a strained surface layer on said relaxed Si1−xGex, layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1−xGex, layer on the Si substrate, and a strained layer on the relaxed Si1−xGex, layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

Abstract: This method forms an SRAM device with an array of cells having low resistance conductors for the reference potential (Vss) circuits connected to transistors in the SRAM device. First form an SRAM device with two pull-up transistors, two pull-down transistors and two pass gate transistors, including thin film gate electrode conductors and interconnection lines, each of the transistors having a drain region and a source region with source regions of the two pull-up transistors connected to a power supply voltage (Vcc). Then form a plurality of dielectric and metallization layers over the transistors, the conductors and the interconnection lines. Form a stack of layers over the transistors, the stack of layers comprising a plurality of metallization layers sandwiched between a plurality of dielectric layers. Form a conductive reference potential node electrically connected to the source region of each of the pull-down transistors.

Abstract: The present invention pertains to a high-performance thin film transistor having a gate and an active region, whose active region comprises a poly-Si1−xGex alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1−xGex alloy material and the gate, and a method for fabricating such a high-performance thin film transistor.

Abstract: A shallow trench isolation (STI) structure is constructed in dual gate oxide device that requires a high voltage and low-voltage operation, for example in a LCD driver IC. The disclosed fabrication method prevents deterioration in operational characteristics of resulting transistors and prevents decrease in the reliability of the gate oxide film.

Abstract: A method for forming an integrated circuit on an insulating substrate is described comprising the steps of forming a semiconductor layer on a seed wafer substrate containing an at least partially crystalline porous release layer, processing the semiconductor layer to form a “transferable” device layer containing at least one semiconductor device, and bonding said transferable device layer to a final, insulating substrate before or after separating said device layer from the seed wafer substrate. A second method, for separating a semiconductor layer from a seed wafer substrate, is described wherein an at least partially crystalline porous layer initially connecting the semiconductor layer and seed wafer substrate is split or broken apart by the steps of (i) introducing a fluid including water into the pores of said porous layer, and (ii) expanding said fluid by solidifying or freezing to break apart the porous layer.

Abstract: A radiation hardened silicon-on-insulator transistor is disclosed. A dielectric layer is disposed on a substrate, and a transistor structure is disposed on the dielectric layer. The transistor structure includes a body region, a source region, a drain region, and a gate layer. The body region is formed on a first surface portion of the dielectric layer, the source region is formed on a second surface portion of the dielectric layer contiguous with the first surface portion, the drain region is formed on a third surface portion of the dielectric layer contiguous with the first surface portion, and the gate layer overlies the body region and being operative to induce a channel in that portion of the body region disposed between and adjoining the source region and the drain region. In addition, multiple diffusions are placed across two edges of the source region.

Abstract: A method of manufacturing a liquid crystal panel comprises the steps of forming a gate insulating film, a channel layer and an etching stopper layer on a transparent substrate bearing a gate electrode, exposing the substrate to light from its back surface side by using the gate electrode as a light shielding mask by photolithography, developing the resist, etching the etching stopper layer, forming a source/drain layer, and etching the source/drain layer and a remaining part of the etching stopper by chemical gas phase etching.

Abstract: This method forms an SRAM device with an array of cells having low resistance conductors for the reference potential (Vss) circuits connected to transistors in the SRAM device. First form an SRAM device with two pull-up transistors, two pull-down transistors and two pass gate transistors, including thin film gate electrode conductors and interconnection lines, each of the transistors having a drain region and a source region with source regions of the two pull-up transistors connected to a power supply voltage (Vcc). Then form a plurality of dielectric and metallization layers over the transistors, the conductors and the interconnection lines. Form a stack of layers over the transistors, the stack of layers comprising a plurality of metallization layers sandwiched between a plurality of dielectric layers. Form a conductive reference potential node electrically connected to the source region of each of the pull-down transistors.

Abstract: An LDMOS field effect transistor (80) provides protection against the inadvertent reversal of polarity of voltage applied across the device. To protect an N-channel device, a floating P-type blocking region (82) is provided surrounding the drain region (32). The blocking region (82) is spaced apart from a body region (28) that forms the diffused channel (34) of the transistor (80). A first gate electrode (36) controls the conductivity of the diffused channel (34) and a second gate electrode (84) controls the conductivity of the surface (35) of the blocking region (82).

Abstract: A double level gate layer with an undercut lower gate layer can be formed by using the etching rate difference between the upper gate layer and the lower gate layer in a polycrystalline Si type TFT LCD that has P-channel TFTs and N-channel TFTs. An LDD structure can be easily formed by using an upper gate layer as ion implant mask during the N-type ion implantation. LDD size is decided by the skew size between the upper gate layer and the lower gate layer. Furthermore, a photolithography step necessary for masking the ion implantation can be skipped.

Abstract: In a region on the left hand of FIG. 1 with respect to the gate electrode (107), a first source region (103a), a body-potential drawing region (105) and a second source region (103b) are formed in this order along the vertical direction of this figure. The first and second source regions (103a, 103b) are of n+ type, and the body-potential drawing region (105) is of p+ type. In a thin-film transistor (100), the body-potential drawing region (105) can draw and fix a body potential.

Abstract: Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically shaped devices relative to the patterned device outlines. Individual formed devices are spaced from at least one other of the devices by a distance no more than a width of one of the electrically insulative spacers. In such manner, device pitch is reduced by almost fifty percent. According to one aspect, elongated electrically conductive lines are formed. According to another aspect, capacitors are formed which, according to a preferred embodiment form part of a dynamic random access memory (DRAM) array.

Abstract: To provide a laser apparatus and a laser annealing method with which a crystalline semiconductor film with a larger crystal grain size is obtained and which are low in their running cost. A solid state laser easy to maintenance and high in durability is used as a laser, and laser light emitted therefrom is linearized to increase the throughput and to reduce the production cost as a whole. Further, both the front side and the back side of an amorphous semiconductor film is irradiated with such laser light to obtain the crystalline semiconductor film with a larger crystal grain size.

Abstract: The present invention provides a heat treatment apparatus capable of forming a uniform thin layer on the substrate provided with a furnace core pipe, a substrate supporting boat for supporting a lot of substrates disposed in the furnace core pipe and a process gas injector pipe having many blowing holes for spouting the process gas toward the substrate, the supporting boat having a rotation mechanism to rotate around the normal line passing through one principal face of the substrate as a rotation axis. In the apparatus, an inert gas injector pipe has the same number of inert gas or nitrogen gas blowing holes as the number of process gas blowing holes and is provided at an approximately symmetrical position relative to the center line of the rotation axis.

Abstract: A method of fabricating integrated circuitry comprises forming a conductive line having opposing sidewalls over a semiconductor substrate. An insulating layer is then deposited. The insulating layer is etched proximate the line along at least a portion of at least one sidewall of the line. An insulating spacer forming layer is then deposited over the substrate and the line. It is anisotropically etched to form an insulating sidewall spacer. A method of forming a local interconnect comprises forming at least two transistor gates over a semiconductor substrate. A local interconnect layer is deposited to overlie at least one of the transistor gates and interconnect at least one source/drain region of one of the gates with semiconductor substrate material proximate another of the transistor gates.

Abstract: A process for forming a polycrystalline TFT LCD is provided, thereby greatly reducing the manufacturing cost and time. The process includes steps of performing a first masking procedure to define a gate conductive region, successively forming an insulation layer, an amorphous channel semiconductor layer, a catalytic layer and a doped semiconductor layer, performing a second masking procedure to remove portions of the semiconductor layer and the catalytic layer to define an electrode region, performing a thermal treatment to respectively convert the electrode region and the amorphous semiconductor channel layer into a source/drain region and a crystalline semiconductor channel layer by the catalytic layer, performing a third masking procedure to define data lines, performing a fourth masking procedure to form a contact hole, and performing a fifth masking procedure to define a transparent pixel electrode region, thereby forming the TFT.

Abstract: A plurality of semiconductor components (33, 35) isolated by an insulating film (39) are formed on a buried oxidation film (3) of an SOI substrate (1), substrate contact holes (5, 6) through the insulating film (39) and the buried oxidation film (3) are provided, a heavily doped diffusion layer (7) is provided in the vicinity of the surface of a support substrate (2) exposed within the substrate contact holes (5, 6), and a metal electrode (22) with a pad portion (22a) extending onto the insulating film (39) electrically connected with the heavily doped diffusion layer (7) through the substrate contact holes (5, 6) is provided.

Abstract: In accordance with the invention, a process for forming a dual gate structure for CMOS devices comprises the steps of a) providing a semiconductor workpiece including n-type and p-type regions and a gate dielectric region for a dual gate structure formed over the regions, b) forming over the gate dielectric region a thin layer of semiconductor doped to one type of conductivity, c) selectively removing the doped semiconductor overlying the workpiece region of like conductivity doping and d) forming a thin layer of semiconductor doped to the opposite kind of conductivity. The doped layers are then planarized as by chemical-mechanical polishing (CMP). An additional layer of undoped semiconductor can optionally be applied to bury the doped layers, and the device can be finished by coating with metal silicide in the usual fashion. This process can be completed with only one photolithography step, simplifying device fabrication by several operations.

Abstract: A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage activated transistors which have the same channel conduction type and are electrically connected in series between a power supply terminal and an output terminal. A source region and a body region of at least the voltage activated transistor connected to the output terminal are electrically connected and have substantially the same potential. The semiconductor integrated circuit has either an SOI or SOS structure.

Abstract: A polycrystalline silicon layer is formed on a substrate. An insulating layer and a gate electrode are formed on the polycrystalline silicon layer. Then, a channel region, a source region and a drain region are formed in a self-aligned manner by doping an impurity in the polycrystalline silicon layer using the gate electrode as a mask. Then, an energy absorption layer is formed so as to cover the entire substrate and a pulsed laser beam is irradiated from the energy absorption layer side. The energy of the pulsed laser beam is almost completely absorbed in the energy absorption layer and a heat treatment is indirectly performed on the underlying layers by radiating the heat. In other words, activation of the impurity and removal of defects in the insulating layer are performed at the same time without damaging the substrate by the heat.

Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.

Abstract: A high-voltage device is proposed. A first well region with the first conductive type is located in a substrate. Several isolation regions are located on the first well region. Each isolation region comprises two field oxide layers on either side of a shallow trench isolation structure. A gate structure is formed on the first well region between the isolation regions and the gate structure expands on a portion of the isolation regions. A source/drain region with the second conductive type is located in the first well region exposed by the gate structure and the isolation regions. A second well region with a second conductive type is located in the first well region beneath the isolation region and the source/drain region. A first doped region with the second conductive type is located in the second well region beneath each of the field oxide layers. A second doped region with the first conductive type is located in the second well region beneath each of the shallow trench isolation structures.

Abstract: In a fabrication of a thin film transistor, an amorphous silicon film 4 is formed on a substrate 1 and, then, phosphor 6 is deposited or diffused on or into a surface of the amorphous silicon film 4 by exposing the amorphous silicon film to phosphine plasma 5. Thereafter, a metal film 7 for source and drain electrodes is formed by sputtering. Phosphor 6 diffuses to a surface layer of the amorphous silicon film 4 during this sputtering and an n-type amorphous silicon film 8 as an ohmic contact layer is formed automatically.

Abstract: A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers includes forming a first doped and activated polysilicon area (either n-type and p-type) on a substrate. An isolation material layer is formed abutting the first activated area. A second doped and activated polysilicon area of opposite conductivity type from the first activated area is formed adjacent to the isolation material layer. The second activated opposite area has a height that does not exceed that of the first doped and activated polysilicon layer. Further processing may be effected to complete the MOS device. The method of the present invention eliminates ion implantation and annealing steps used in previously existing methods.

Abstract: A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120a, 120b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120a, 120b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).

Abstract: In the method of manufacturing the DRAM mixed logic memory, first, a pattern of one gate electrode is formed, and then a pattern of another gate electrode is formed. A step of oxidizing a polycrystalline silicon residue is performed thereafter. Therefore, the polycrystalline silicon residue is prevented from being left and prevention of electric short circuit is allowed.

Abstract: The present invention provides a compact structure for the above-discussed SRAM cell as well as a method for fabricating the structure. The structure is preferably implemented in silicon. The standby power consumption of the cell is only approximately 0.5 nanowatts. The cell structure allows an SRAM cell to be fabricated in only a 16 feature-square area using planar technology. The structure of the cell according to one embodiment of the present invention is comprised of two bus bars of minimum feature size width, each of which has a tunnel diode implanted therein, and an elongated center land area (also of minimum feature size width) between the two bus bars. The transistor is constructed along the elongated center land area. In a preferred embodiment, transistors of neighboring cells share a common drain area and bit line contact. A corresponding method for fabricating the structure is also provided.

Abstract: The present invention relates to a thin film transistor and a fabricating method thereof which improve device characteristics by forming a substance layer such as a vacuum layer or an air layer, which has a remarkable characteristic of insulation, on an active layer. The present invention includes an insulated substrate, an active layer on the insulated substrate wherein the active layer has a source region, a channel region and a drain region, a gate insulating layer having an inner space on the channel region, and a gate electrode on the gate insulating layer over the channel region. And, the present invention includes the steps of forming an active layer on an insulated substrate, forming a gate insulating layer having an inner space on the active layer, forming a gate electrode on the gate insulating layer, and forming a source region and a drain region in the active layer by doping the substrate including the active layer with impurities.

Abstract: The present invention discloses a method of manufacturing a thin film transistor, including: depositing an amorphous silicon layer, an insulating layer, and a gate metal layer on a substrate sequentially; patterning the insulating layer and the gate metal layer to form a gate insulating layer and a gate electrode; treating an impurity and a catalyst metal on the amorphous silicon layer using the gate electrode as a mask; and applying a DC voltage to both terminals of the amorphous silicon layer to form a polysilicon layer, the polysilicon layer having source and drain regions and an active area.

Abstract: The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips. The memory cells use three-dimensional (3D) SRAM structures. Two kinds of 3D logic cells are disclosed. 3D form of the differential cascode voltage switch (DCVS) architecture, and a 3D form of the DCVS with pass gate (DCVSPG) logic architecture. A high density “system on chip” architecture is described. The high density is achieved by locating large PMOS transistors in the TF Si layer, and the fast NMOS transistors in a bulk Si wafer layer. A single process sequence to simultaneously make the logic and memory circuits on the IC chip is also described.

Abstract: Shallow trench isolation is combined with optional deep trenches that are self-aligned with the shallow trenches, at the corners of the shallow trenches, and have a deep trench width that is controlled by the thickness of a temporary sidewall deposited in the interior of the shallow trench and is limited by the sidewall deposition thickness of the deep trench fill.

Abstract: A tPEN layer (108) having a tensile stress is formed over a conductive gate stack (104-106) provided on a semiconductor substrate. Following the formation of the conductive gate stack (104-106), an anneal is performed. The conductive gate stack includes a metal layer to prevent outgassing and poly depletion during the anneal. Next, a photoresist layer (110) is formed and patterned to form a gate (122, 124).