Abstract: To provide a TFT that can operate at a high speed by forming a crystalline semiconductor film while controlling the position and the size of a crystal grain in the film to use the crystalline semiconductor film for a channel forming region of the TFT. Instead of a metal or a highly heat conductive insulating film, only a conventional insulating film is used as a base film to introduce a temperature gradient. A level difference of the base insulating film is provided in a desired location to generate the temperature distribution in the semiconductor film in accordance with the arrangement of the level difference. The starting point and the direction of lateral growth are controlled utilizing the temperature distribution.

Abstract: A six transistor static random access memory (SRAM) cell with thin-film pull-up transistors and method of making the same includes providing two bulk silicon pull-down transistors of a first conductivity type, two active gated pull-up thin-film transistors (TFTs) of a second conductivity type, two pass gates, a common word line, and two bit line contacts. The bulk silicon pull-down transistors, two active gated pull-up TFTs, and two pass gates are connected at four shared contacts. In addition, the two bulk silicon pull-down transistors and the two active gated pull-up TFTs are formed with two polysilicon layers, a first of the polysilicon layers (poly1) is salicided and includes poly1 gate electrodes for the two bulk silicon pull-down transistors. A second of the polysilicon layers (poly2) includes desired poly2 stringers disposed along side edges of the poly1 gate electrodes, the desired poly2 stringers forming respective channel regions of the pull-up TFTs.

Abstract: A double level gate layer with an undercut lower gate layer can be formed by using the etching rate difference between the upper gate layer and the lower gate layer in a polycrystalline Si type TFT LCD that has P-channel TFTs and N-channel TFTs. An LDD structure can be easily formed by using an upper gate layer as ion implant mask during the N-type ion implantation. LDD size is decided by the skew size between the upper gate layer and the lower gate layer. Furthermore, a photolithography step necessary for masking the ion implantation can be skipped.

Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end.

Abstract: An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source shorted to provide load devices for the N channel inverter transistors of the SRAM cell.

Abstract: In a CMOS circuit, impurity regions are formed in the channel forming region of each of an n-channel and p-channel transistors along the channel direction. The intervals between the impurity regions in the n-channel transistor is set narrower than those between the impurity regions in the p-channel transistor so as to make the absolute values of the threshold voltages of the n-channel and p-channel transistors approximately equal to each other. Where active layers are formed by utilizing a crystal structural body that is a collection of needle-like or columnar crystals, the same effect can be attained by controlling the width of the needle-like or columnar crystals.

Abstract: There is disclosed a method of fabricating TFTs using a silicon film crystallized with the aid of nickel. The nickel is removed from the crystallized silicon film. The method starts with maintaining nickel in contact with the surface of an amorphous silicon film. Then, a heat treatment is performed to form a crystalline silicon film. At this time, nickel promotes the crystallization greatly, and nickel diffuses into the film. A mask is formed. A silicon film heavily doped with phosphorus is formed. Thereafter, a heat treatment is performed to move the nickel from the crystalline silicon film into the phosphorus-rich silicon film. This reduces the concentration of nickel in the crystalline silicon film.

Abstract: In producing a thin film transistor, after an amorphous silicon film is formed on a substrate, a nickel silicide layer is formed by spin coating with a solution (nickel acetate solution) containing nickel as the metal element which accelerates (promotes) the crystallization of silicon and by heat treating. The nickel silicide layer is selectively patterned to form island-like nickel silicide layer. The amorphous silicon film is patterned. A laser light is irradiated while moving the laser, so that crystal growth occurs from the region in which the nickel silicide layer is formed and a region equivalent to a single crystal (a monodomain region) is obtained.

Abstract: A double level gate layer with an undercut lower gate layer can be formed by using the etching rate difference between the upper gate layer and the lower gate layer in a polycrystalline Si type TFT LCD that has P-channel TFTs and N-channel TFTs. An LDD structure can be easily formed by using an upper gate layer as ion implant mask during the N-type ion implantation. LDD size is decided by the skew size between the upper gate layer and the lower gate layer. Furthermore, a photolithography step necessary for masking the ion implantation can be skipped.

Abstract: A method for fabricating a thin film transistor includes the steps of forming an active layer on a substrate, forming a metal gate electrode on the active layer, depositing a silicon layer on the metal gate electrode and the active layer, causing the metal gate electrode to react with the silicon layer to form a silicide layer around the metal gate electrode, removing the silicon layer, heavily doping impurities in the active layer using the silicide layer as a mask to form a source/drain region, removing the silicide layer, and lightly doping impurities in the active layer using the metal gate electrode as a mask to form an offset region.

Abstract: A method of forming a semiconductor substrate (and the resulting structure), includes etching a groove into a bulk silicon substrate, forming a dielectric in the groove and planarizing the silicon substrate to form at least one patterned dielectric island in the silicon substrate, forming an amorphous silicon (or SiGe) layer on exposed portions of the silicon substrate and the at least one dielectric island, crystallizing the amorphous silicon (or SiGe) layer using the exposed silicon substrate as a seed, the silicon substrate having direct contact with the formed silicon layer serving as a crystal growth seeding for the crystallization process, and converting the silicon (or SiGe) layer to crystallized silicon, and performing a shallow trench isolation (STI) process, to form oxide isolations between devices.

Abstract: The present invention is directed to method for manufacturing a liquid crystal display apparatus in which a thin film transistor formed by successively depositing on a glass substrate a gate electrode, a gate insulating film, an active layer made of amorphous silicon, a source electrode and a drain electrode is used for driving liquid crystal. The method includes steps of: forming the gate electrode by patterning a gate metal layer coating the glass substrate by a wet etching process using an etchant containing cerium ammonium nitrate; removing an etching reaction product adhering on the substrate by washing it with a hydrofluoric acid solution; and forming the gate insulating film.

Abstract: An SRAM is provided in which adjacent contact holes cannot be connected and which can be miniaturized. An SRAM memory cell includes a gate electrode formed on a silicon substrate, and an interlayer insulation film covering the gate electrode. The interlayer insulation film has a contact hole which reaches an active region and a contact hole which reaches the gate electrode. The contact holes are positioned almost in a lattice manner.

Abstract: In a method of manufacturing a semiconductor device, nickel elements 404 is held on a surface of an amorphous silicon film 403 in a contact manner, and then transformed into a crystalline silicon film 405 through a heat treatment. Thereafter a mask 406 is formed to conduct doping with phosphorus, In this process, a region 407 is doped with phosphorus. Then, the region 407 which has been doped with phosphorus is activated by the irradiation of a laser beam or an intense light. Then, a heat treatment is conducted on the layer again to getter nickel in the region 407. Subsequently, the region 407 into which nickel is concentrated is removed so nickel is gettered, to obtain a region 408 having still higher crystallinity.

Abstract: The present invention pertains to methods of forming integrated circuitry, methods of forming SRAM cells, and methods of reducing alpha particle inflicted damage to SRAM cells. Additionally, the present invention pertains to integrated circuitry. In one aspect, the invention includes a method comprising: a) forming at least one second conductivity type diffusion region beneath at least one of an SRAM cell pull-down device drain of a first conductivity type and an SRAM cell access device source of the first conductivity type; and b) not forming a second conductivity type diffusion region beneath at least one of a source of the SRAM cell pull-down device and a drain of the SRAM cell access device.

Abstract: There is provided a semiconductor device including a semiconductor substrate, a gate electrode formed on the semiconductor substrate, a gate insulating layer sandwiched between the gate electrode and the semiconductor substrate, an interlayer insulating layer formed over the gate electrode and the semiconductor substrate, and a hydroxyl (OH) group trapper formed in the interlayer insulating layer. For instance, the hydroxyl group trapper is constituted of a nitrogen containing oxide layer. The semiconductor device is capable of preventing moisture contained in the interlayer insulating layer from penetrating the gate insulating layer and source/drain regions formed in the semiconductor substrate, resulting in that the semiconductor device can be kept away from being degraded because of hot carriers, even if the gate insulating layer were formed thinner.

Abstract: In a process for producing a semiconductor substrate, comprising sealing surface pores of a porous silicon layer and thereafter forming a single-crystal layer on the porous silicon layer by epitaxial growth, intermediate heat treatment is carried out after the sealing and before the epitaxial growth and at a temperature higher than the temperature at the time of the sealing. This process improves crystal quality of the semiconductor substrate having the single-crystal layer formed by epitaxial growth and improves smoothness at the bonding interface when applied to bonded wafers this process enables the detection of the smaller particles on the surface by a laser light scattering method.

Abstract: A thin film transistor (TFT) which may be used as a pixel drive element in an active matrix LCD display includes a pair of side wall spacers adjacent to the opposing side walls of its gate electrode. The side wall spacers provide the gate electrode with a substantially rectangular cross section, such that the gate electrode has a substantially constant thermal conductivity over its area. The TFT has a uniform device characteristic.

Abstract: A simple and convenient method of manufacturing a CMOS TFT semiconductor circuit device wherein a doping layer doped into a first conductivity type without a mask is compensated with a dopant of a second conductivity type having a high density so that the conductivity type of the doping layer of first conductivity type is inverted into the second conductivity type, and further, in order to carry out the inversion of the conductivity type by the compensation easily and reliably, the surface density of the dopant of the doping layer of first conductivity type is reduced prior to compensating with the dopant of second conductivity type.

Abstract: A CMOS SRAM cell includes a substrate divided by a well trench into an n well region and a p well region, first and second active regions each having a V shape, formed symmetrical relative to each other, and having the well trench in between, third and fourth active regions formed symmetrically relative to each other and offset from the second active region, first and second gate lines each crossing the first active region, the well trench, and the second active region, and a third gate line crossing the third and fourth active regions.

Abstract: An aluminum gate for a thin film transistor is fabricating by implanting ions into the exposed surface of the aluminum gate. The ions are preferably selected from the group consisting of nitrogen, carbon, oxygen and boron ions. A composite layer of aluminum and the implanted ions thereby formed at the exposed surface of the aluminum layer. Gates for thin film transistors, including an aluminum layer and a composite layer of aluminum and another element at the surface thereof can suppress hillocks in the aluminum gate which may be caused by compressive stresses during subsequent fabrication steps. The composite layer can have a low resistance and can allow a direct contact with an indium tin oxide conductive layer.

Abstract: A method of making a resistor begins with forming a field effect transistor on a silicon semiconductor substrate. Then a first insulating layer is deposited on the field effect transistor. The first insulating layer is etched by the photolithography and etching techniques to form a bit line contact, and a bit line is subsequently formed. Next, upon the entire structure, a second insulating layer is formed and etched by the photolithography and ion etching techniques to form a contact hole with high aspect ratio. A polysilicon layer is deposited across the contact hole and the polysilicon outside the contact hole is removed, forming a polysilicon plug in the contact hole. Then, a third insulating layer is formed and etched to form a contact hole for metallurgy. After a first metal interconnection is formed, a third insulating layer is formed upon the entire structure and then etched to form a via hole by the photolithography and plasma etching techniques.

Abstract: In an SRAM having P-channel thin film transistors formed on N-channel drive MOS transistors each of which is composed of a first gate electrode, a first drain layer and a first source layer, N-channel transfer MOS transistors each of which is composed of a second gate electrode, first and second diffusion layers, the MOS transistors are formed on a substrate. A first insulating film is formed on the driver and transfer MOS transistors. On the first insulating film, the p-channel thin film transistors are formed, each of which is composed of a third gate electrode, a second source layer functioning a power supply line pattern, a second drain layer and a gate insulator. Also, at the same time, there are formed another power supply line pattern to be connected to a second source layer of another p-channel thin film transistor, and a wiring layer to be connected to a third gate electrode of the other p-channel thin film transistor.

Abstract: A semiconductor device having a CMOS structure comprising N-channel type and P-channel type insulated gate semiconductor devices combined in a complementary manner, wherein the threshold voltage of the insulated gate semiconductor devices is controlled by using the difference in work function between the gate electrode and the active layer. The present semiconductor device has excellent uniformity and reproducibility.

Abstract: Disclosed is a semiconductor device having an enhanced current amount ratio, and a manufacturing method thereof. The semiconductor device includes a first transistor and a second transistor. There is a selective electric current capacity difference between the first transistor and the second transistor, wherein a gate degeneracy of the first transistor is different from a gate degeneracy of the second transistor. Among the first and second transistors, the gate degeneracy of the transistor requiring a small amount of current is higher than the gate degeneracy of the transistor requiring a large amount of current.

Abstract: A repairable CMOSFET includes an insulating substrate, a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type formed on the insulating substrate, defined as a center and two edges, and spaced apart from each other by a predetermined distance, a third semiconductor layer of a second conductivity type formed to have a predetermined length extending from the edges of the first semiconductor layer of a first conductivity type toward the second semiconductor layer of a second conductivity type, a fourth semiconductor layer of a first conductivity type formed to have a predetermined length extending from the edges of the second semiconductor layer of a second conductivity type to have symmetry to the third semiconductor layer of a second conductivity type, a insulating layer formed on the entire surfaces of the first, second, third, and fourth semiconductor layers, and a gate electrode formed between the centers of the first and second semiconductor l

Abstract: In order to produce an MOS transistor in an SOI substrate, the silicon layer (3), a gate dielectric (4) and an electrode layer (5) are structured in MESA fashion to form an active region. The flanks of the MESA structure (7) are provided with insulating spacers (8). In a further structuring step, a gate electrode (12) is formed from the electrode layer (5). The process provides a high packing density and at the same time avoids the problem of gate side-wall control as well as premature breakdown at oxide edges.

Abstract: A contact process interconnects poly-crystal silicon layer, and more particularly, this process dramatically decreases the voltage drop within a poly-crystal silicon layer. The advantages of the process include not only improvement in the interface quality of Poly-Si/SiO2 to decrease the junction damage but also do not increase its process complexity and its mask number during the fabrication of poly-crystal silicon thin-film SRAM to meet high integration requirement in VLSI.

Abstract: Disclosed is a semiconductor device having a silicon on insulator structure capable of achieving a high integration, and a manufacturing method of the same. The semiconductor device includes a semiconductor substrate having a silicon on insulator structure, in which a insulating layer and a semiconductor layer are formed on a semiconductor wafer in sequence. A gate insulating film and a gate are formed on the semiconductor layer. A first impurity diffusion region and a second impurity diffusion region are formed in the semiconductor layer at both sides of the gate. A intermediate insulating layer having a first contact hole for exposing a predetermined portion of the first impurity diffusion region and a second contact hole for exposing a predetermined portion of the second impurity diffusion region and a predetermined portion of the water, is formed on an overall surface of the substrate.

Abstract: To form a recess defining a channel region in a SOI layer, a LOCOS oxide film is formed on a surface of the SO layer and then removed. Then, side walls of CVD oxide is formed on side surfaces defining an opening of a LOCOS oxide restraining film. Then, a gate oxide film is formed on an exposed surface of the SOI layer inside the opening. Then, CVD polycrystalline silicon is formed on the whole wafer surface, and then etched back to form a gate electrode of polycrystalline silicon inside the opening. At this time, a top surface of the gate electrode is at a level lower than a top surface of the restraining film. Next, the restraining film and the side walls are removed and ion implantation into the SOI layer is performed using the gate electrode as a mask to thereby form a source and a drain region. Then, side walls are formed on side surfaces of the gate electrode, and a silicide film is formed on the gate electrode and the source and drain regions.

Abstract: A method of forming a pair of field effect transistors having different thickness gate dielectric layers includes, a) providing a first region on a substrate for formation of a first field effect transistor s having a first gate dielectric layer of a first thickness and providing a second region on the substrate for formation of a second field effect transistor having a second gate dielectric layer of a second thickness; b) providing the first gate dielectric layer and a first conductive gate layer over the first and second regions; c) patterning the first conductive layer to define a first gate of the first field effect transistor in the first region while leaving the first conductive layer not patterned for gate formation for the second field effect transistor in the second region; d) after defining the first gate, stripping the first conductive layer and the first gate dielectric layer from the second region; e) after stripping the first conductive layer and the first gate dielectric layer from the second

Abstract: A memory cell for a semiconductor device includes two pairs of a transfer transistor and a drive transistor at a first level and a pair of load transistors above the two pairs of transfer and drive transistors at a second level. Each of the load transistors includes a gate, a source/drain, and a channel. The cell further includes a pair of contacts extending between the first and second levels and that connect one of the gates to a respective one of the two pairs of transfer and drive transistors. Each load transistor gate includes a portion that overlies its respective channel and a lateral extension therefrom that contacts a respective one of the contacts. The extension of one load transistor gate overlaps the source/drain of the other load transistor adjacent the respective one of the contacts.

Abstract: A multi-dimensional transistor structure is fabricated which includes a base transistor substrate upon which transistors are formed. An elevated substrate is formed overlying the base transistor and having an oxide isolation formed in localized regions beneath the elevated substrate but overlying the base transistor substrate. A plurality of transistors are formed on a substrate wafer to form a base-level transistor formation. An intralevel dielectric (ILD) layer is deposited overlying the base-level transistor formation. Overlying the ILD layer, a "sandwich" structure is formed with the deposition of a first polysilicon layer, deposition of an oxide isolation layer, and deposition of a second polysilicon layer.

Abstract: Disclosed is a semiconductor device having a silicon on insulator structure capable of achieving a high integration, and a manufacturing method of the same. The semiconductor device includes a semiconductor substrate having a silicon on insulator structure, in which a insulating layer and a semiconductor layer are formed on a semiconductor wafer in sequence. A gate insulating film and a gate are formed on the semiconductor layer. A first impurity diffusion region and a second impurity diffusion region are formed in the semiconductor layer at both sides of the gate. A intermediate insulating layer having a first contact hole for exposing a predetermined portion of the first impurity diffusion region and a second contact hole for exposing a predetermined portion of the second impurity diffusion region and a predetermined portion of the wafer, is formed on an overall surface of the substrate.

Abstract: A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.

Abstract: A method is provided for forming a transistor in which the gate is coupled to a second substrate dielectrically spaced above a first substrate. According to an embodiment, a polysilicon layer is formed across an interposing dielectric layer which is disposed across a single crystalline silicon substrate. The polysilicon layer is doped, making it the second semiconductor substrate. Trench isolation structures may be formed within the second substrate between ensuing active areas. A gate oxide is formed across the second substrate, and an opening is etched through the gate oxide down to the second substrate. A conductive material is formed within the opening, and polysilicon is deposited across the gate oxide. The polysilicon may be etched to form a gate conductor above the gate oxide. LDD implant areas are formed within the second substrate between the gate conductor and adjacent isolation structures.

Abstract: A manufacturing method applicable for forming a via connection to the thin film transistor in a SRAM unit which resolves the problems arising from a conventional method for forming a via for linking up the drain of a load transistor with the gate of a driver transistor in a SRAM unit by changing the processing sequence and also by forming a plug instead of a via.

Abstract: A gate insulating film is formed on a main surface of a semiconductor substrate. A conductive layer P1 including a gate region G1 and a conductive layer P2 including a gate region G2 are formed on the gate insulating film. A diffusion regions D1, S, and D2 are formed with gate regions G1 and G2 interposed therebetween. The conductive layer P1 and the diffusion region D2 are put in contact with each other and the conductive layer P2 and the diffusion region D1 are put in contact with each other. On the main surface region of the substrate corresponding to the conductive layer P1, a buried diffusion layer BD1 of the same conductive type as the diffusion region S is formed contiguously to the diffusion region S. On the main surface region of the substrate corresponding to the conductive layer P2, a buried diffusion layer BD2 of the same conductive type as the diffusion region S is formed contiguously to the diffusion region S. Then, the diffusion region S is grounded.

Abstract: The present invention pertains to methods of forming integrated circuitry, methods of forming SRAM cells, and methods of reducing alpha particle inflicted damage to SRAM cells. Additionally, the present invention pertains to integrated circuitry. In one aspect, the invention includes a method which includes: a) forming at least one second conductivity type diffusion region beneath at least one of an SRAM cell pull-down device drain of a first conductivity type and an SRAM cell access device source of the first conductivity type; and b) not forming a second conductivity type diffusion region beneath at least one of a source of the SRAM cell pull-down device and a drain of the SRAM cell access device.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. In order to abut the gate conductors together, the upper level transistor is inverted relative to the lower level transistor.

Abstract: A process for manufacturing a MOS-technology power device chip and package assembly, the MOS-technology power device chip comprises a semiconductor material layer in which a plurality of elementary functional units is integrated, each elementary functional unit contributing a respective fraction to an overall current and including a first doped region of a first conductivity type formed in the semiconductor layer, and a second doped region of a second conductivity type formed inside the first doped region; the package comprises a plurality of pins for the external electrical and mechanical connection; the plurality of elementary functional its is composed of sub-pluralities of elementary functional units, the second doped regions of all the elementary functional units of each sub-plurality being contacted by a same respective metal plate electrically insulated from the metal plates contacting the second doped regions of all the elementary functional units of the other sub-pluralities; each of the metal plates

Abstract: Methods of forming thin-film transistors include the steps of forming an amorphous silicon (a-Si) layer of predetermined conductivity type on a face of an electrically insulating substrate and then forming a first insulating layer on the amorphous silicon layer. The first insulating layer and amorphous silicon layer are then patterned to define spaced amorphous source and drain regions having exposed sidewalls. An amorphous silicon channel region is then deposited in the space between the source and drain regions and in contact with the sidewalls thereof. An annealing step is then performed to convert the amorphous source, drain and channel regions to polycrystalline silicon, prior to the step of forming an insulated gate electrode on the channel region.

Abstract: A process for manufacturing a thin film transistor for use in a CMOS SRAM circuit is described. A key feature is the formation of two different photoresist masks from the same optical mask. The first photoresist mask is generated using a normal amount of actinic radiation during exposure and is used to protect the gate region during source and drain formation through ion implantation. The second photoresist mask is aligned relative to the gate in exactly the same orientation as the first mask but is given a reduced exposure of actinic radiation. This results, after development, in a slightly larger mask which is used during etching to form the oxide cap that will protect the channel area during the subsequent silicidation step. Making the cap slightly wider than the channel ensures that small lengths of the source and the drain regions that abut the channel are not converted to silicide. Thus, the finished device continues to act as a thin film transistor, but has greatly reduced source and drain resistances.

Abstract: A method for forming a bipolar transistor comprises the following steps. A collector region of a first conductivity type is formed in a substrate adjacent a surface thereof. A base region of a second conductivity type is then formed in the collector region adjacent the surface of the substrate. A base electrode is formed on a first portion of the substrate adjacent the base region wherein the base electrode comprises a dopant of the second conductivity type. Next, an emitter electrode is formed on a second portion of the substrate adjacent the base region wherein the emitter electrode comprises a dopant of the first conductivity type. The dopant of the second conductivity type from the base electrode is diffused into the first portion of the base region to increase a dopant concentration of the first portion of the base region adjacent the base electrode.

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract: A method is achieved for making TFT-load static random access memory (SRAM) cells where the thin film transistor (TFT) gate electrodes are made from an electrical conductor. At the same time, portions of the conductor between P and N doped polysilicon interconnections eliminate the P/N junction. Ohmic contacts are formed while avoiding additional processing steps. N-channel FET gate electrodes are formed from an N.sup.+ doped first polysilicon layer having a first insulating layer thereon. Second polySi interconnections are formed with a second insulating layer thereon. First contact openings are etched in the first and second insulating layers to the N.sup.+ doped FET gate electrodes, and a patterned conductor (TiN, TiSi.sub.2) forms the P-channel TFT gate electrodes and concurrently forms portions over and in the first contact openings. A TFT gate oxide is formed and second contact openings are etched over the first contact openings to the conductor. An N.sup.

Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type with a first insulating layer formed on the semiconductor substrate and a thin film field effect transistor with a control gate containing a refractory metal silicide formed on the semiconductor substrate over the first insulating layer. A second insulating layer covers the control gate electrode. A semiconductor film is formed on the semiconductor substrate over the first and second insulating layers and having a first region of a second conductivity type opposite to the first conductivity type. A second region of the first conductivity type is formed in contact with a first end of the first region. A third region of the first conductivity type is formed in contact with a second end of the first region. The control gate electrode and a part of the first region are overlapped with each other over the second insulating layer.