Abstract: The present invention discloses a thin film transistor and a method for manufacturing the same, an array substrate and a display device. The performance of the thin film transistor can be improved and thereby the image quality can be improved by an increase in the width of the conducting area of a thin film transistor without change of the capacitance of the source electrode. The thin film transistor comprises a substrate, a gate electrode, a source electrode, at least two drain electrodes, a semiconductor layer, a gate electrode protection layer located between the gate electrode and the semiconductor layer and an etch stopping layer located between the semiconductor layer and the source electrode with the drain electrode, wherein the source electrode and the drain electrodes are respectively connected with the semiconductor layer by a via hole.

Abstract: A method and system for setting the direction of pinned layers in a magnetic junction are described. In one aspect, a magnetic field greater than the coercivity of the layers in a pinned layer but less than the coupling field between the layers is applied. In another aspect the pinned layers are switched from an anti-dual state to a dual state using a spin transfer torque current. In another aspect, a magnetic junction having a partial perpendicular anisotropy (PPMA) layer in the pinned layer is provided. In some aspects, the PPMA layer is part of a synthetic antiferromagnetic structure. In some embodiments, a decoupling layer is provided between the PPMA layer and another ferromagnetic layer in the pinned layer.

Abstract: A method of manufacturing an organic thin film transistor, comprising: providing a substrate comprising source and drain electrodes defining a channel region; subjecting at least the channel region to a cleaning treatment step; and depositing organic semiconductive material from solution into the channel region by inkjet printing.

Abstract: A thin-film transistor (TFT) pixel structure and manufacturing method thereof are described. The TFT pixel structure includes a substrate, first conducting layer, gate insulation layer, channel layer, second conducting layer, contact holes, passivation layer and transparent conducting layer.

Abstract: Embodiments of the disclosed technology disclose manufacture methods of a thin film transistor and an array substrate and a mask therefor are provided. The manufacture method of the thin film transistor comprises: patterning a wire layer by using a exposure machine and a mask with a first exposure amount larger than a normal exposure amount during formation of source and drain electrodes; forming a semiconductor layer on the patterned wire layer; patterning the semiconductor layer by using the exposure machine and the mask with a second exposure amount smaller than the first exposure amount. The mask comprises a source region for forming the source electrode, a drain region for forming the drain electrode and a slit provided between the source region and the drain region, and the width of the slit is smaller than the resolution of the exposure machine.

Abstract: Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.

Abstract: A thin film transistor array panel includes a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, a source electrode and a drain electrode on the semiconductor layer and facing each other, a floating metal layer between the source electrode and the drain electrode, and a passivation layer covering the source electrode, the drain electrode, and the floating metal layer. The floating metal layer is electrically floating.

Abstract: Provided are a thin film transistor and a method for manufacturing the same. The thin film transistor manufacturing method includes forming a gate electrode on a substrate, forming an active layer that is adjacent to the gate electrode and includes an oxide semiconductor, forming an oxygen providing layer on the active layer, forming a gate dielectric between the gate electrode and the active layer, forming source and drain electrodes coupled to the active layer, forming a planarizing layer covering the gate electrode and the gate dielectric, forming a hole exposing the active layer, and performing a heat treatment process onto the planarizing layer in an atmosphere of oxygen.

Abstract: A method of forming a thin film poly silicon layer includes following steps. Firstly, a substrate is provided. A thin film silicon layer is then formed on the substrate by a silicon thin film deposition process. A heating treatment is then applied to the substrate so as to convert the thin film silicon layer into a thin film poly silicon layer. A method of forming a thin film transistor includes following steps. A first patterning process is performed on the thin film poly silicon layer on the substrate to form a semiconductor pattern. Subsequently, a gate insulation layer, a gate electrode, a source electrode and a drain electrode are formed.

Abstract: An active device array substrate includes a flexible substrate, a gate electrode, a dielectric layer, a channel layer, a source electrode, a drain electrode, and a pixel electrode. The flexible substrate has at least one transistor region and at least one transparent region adjacent to each other. The gate electrode is disposed on the transistor region of the flexible substrate. The dielectric layer covers the flexible substrate and the gate electrode. A portion of the dielectric layer disposed on the gate electrode has a first thickness. Another portion of the dielectric layer disposed on the transparent region of the flexible substrate has a second thickness. The second thickness is less than the first thickness. The channel layer is disposed above the gate electrode. The source electrode and the drain electrode are disposed on opposite sides of the channel layer and are electrically connected to the channel layer.

Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.

Abstract: A thin film transistor includes: an insulating layer; a gate electrode provided on the insulating layer; a gate insulating film provided on the gate electrode; a semiconductor layer provided on the gate insulating film, the semiconductor layer being formed of oxide; source and drain electrodes provided on the semiconductor layer; and a channel protecting layer provided between the source and drain electrodes and the semiconductor layer. The source electrode is opposed to one end of the gate electrode. The drain electrode is opposed to another end of the gate electrode. The another end is opposite to the one end. The drain electrode is apart from the source electrode. The channel protecting layer covers at least a part of a side face of a part of the semiconductor layer. The part of the semiconductor layer is not covered with the source and drain electrodes above the gate electrode.

Abstract: Disclosed is a method of forming array substrates having a peripheral wiring area and a display area. The method is processed by only three lithography processes with two multi-tone photomasks and one general photomask. In the peripheral wiring area, the top conductive line directly contacts the bottom conductive line without any other conductive layer. The conventional lift-off process is eliminated, thereby preventing a material (not dissolved by a stripper) from suspending in the stripper or remaining on the array substrate surface.

Abstract: A method of manufacturing a thin-film transistor array includes: forming a gate insulating layer on gate electrodes; forming an amorphous silicon layer on the gate insulating layer; generating a crystalline silicon layer by crystallizing the amorphous silicon layer; and forming source electrodes and drain electrodes. The thicknesses of the gate insulating layer on the gate electrode is within a range in which there is a positive correlation between light absorbances of the amorphous silicon layer above the gate electrodes for the laser light and equivalent oxide thicknesses of the gate insulating layer on the gate electrodes. The thicknesses of the amorphous silicon layer above the gate electrodes is within a range in which variation of the light absorbances according to variation of the thicknesses of the amorphous silicon layer is within a predetermined range from a first standard.

Abstract: A method of forming TFT is provided. The TFT includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.

Abstract: A manufacturing method of an electronic device simplifies the process by performing a patterning process by using an imprinting technology. An electronic device manufactured by the manufacturing method is also disclosed.

Abstract: Embodiments of the present invention provide a TFT array substrate and a manufacturing method thereof, and a display apparatus. The TFT array substrate comprises upper and lower layer electrodes insulating from each other, wherein the upper layer electrode has slits, the slits comprising at least one pair of angles of less than or equal to 90°; the lower layer electrode is a whole-plane electrode. The lower layer electrode has absent regions, and each of the absent regions corresponds to the corresponding angle of less than or equal to 90° of the slits of the upper layer electrode.

Abstract: Embodiments of the present invention provide a thin film transistor (TFT) array substrate and a method for manufacturing the same and a display device. The TFT array substrate improves a structure of a TFT array substrate and has a small thickness, and process flow is simplified. The method for manufacturing a thin film transistor (TFT) array substrate comprises: obtaining a gate line and a gate electrode through a first patterning process on a glass substrate; forming a gate insulating layer on the gate line and the gate electrode; forming a graphene layer on the gate insulating layer, and obtaining a semiconductor active layer over the gate electrode by a second patterning process and a hydrogenation treatment; obtaining a data line, a source electrode, a drain electrode and a pixel electrode which are located on the same layer by a third patterning process; and forming a protection layer on the data line, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode.

Abstract: Embodiments of the present invention relate to an array substrate and a manufacturing method thereof. The manufacturing method comprises: step 1: forming a gate line, a gate electrode, a first insulating layer, an active layer and ohmic contact layers on a base substrate by a first patterning process using a gray-tone or half-tone mask, in which the active layer between the ohmic contact layers corresponds to a channel region; step 2: forming a second insulating layer and a pixel electrode film on the base substrate obtained after the step 1 by a second patterning process using a gray-tone or half-tone mask; and step 3: forming a drain electrode, a source electrode, a data line and a passivation layer on the base substrate obtained after the step 2 by a third patterning process using a gray-tone or half-tone mask.

Abstract: There is provided a thin film transistor, comprising a substrate (1) and a gate layer (3), a gate insulating layer (4), an active layer (5), an electrode metal layer (8) and a passivation layer (9) which are formed on the substrate (1) in sequence; the electrode metal layer (8) comprises a source electrode (8a) and a drain electrode (8b), which are separated from each other with a channel region being defined therebetween; between the gate layer (3) and the substrate (1), there is formed a first transparent conductive layer (2); between the active layer (5) and the electrode metal layer (8), there is formed a second transparent conductive layer (7). The transparent conductive layers (2, 7) are added so that adhesive force between the gate metal layer (3) and the substrate (1) is enhanced, diffusion of the electrode metal to the active layer (5) is prevented.

Abstract: A display apparatus including: a plurality of thin film transistors; and an interconnect region, wherein each of the thin film transistors includes a first protective film held in contact with a channel layer and disposed remotely from a gate electrode, a second protective film disposed on the first protective film, and a source and drain electrode assembly including a pair of electrodes held in contact with the channel layer, and the interconnect region includes a first interconnect, a second interconnect disposed in alignment with the first interconnect, and an insulating layer interposed between the first interconnect and the second interconnect and having a stacked structure including a first insulating film joined to the gate insulating film and a second insulating film joined to the second protective film.

Abstract: A display device and method for fabricating includes patterning a field shield dielectric layer to expose conductors and form a cavity over the conductors. InkJet printing a semiconductor material fills a portion of the cavity in contact with the conductors. An insulation material is deposited on the semiconductor material. A pixel pad is formed over the insulation material and the field shield dielectric layer. A pixel is formed which includes a thin film transistor with an ink jet printed semiconductor layer.

Abstract: A thin film transistor array panel includes a passivation layer formed on a plurality of end portions of a plurality of gate lines. A portion of the passivation layer has a porous structure formed between a connection portion of a flexible printed circuit substrate and a thin film transistor substrate such that when the flexible printed circuit substrate and the thin film transistor array panel are connected to each other, the passivation layer having a porous structure and which is formed at the connection portion therebetween connects the flexible printed circuit substrate with the thin film transistor array panel thereby minimizing an exposed area of the metal of the connection portion to improve a corrosion resistance thereof.

Abstract: Self-aligned carbon nanostructure field effect transistor structures are provided, which are foamed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.

Abstract: A TFT stack for a liquid crystal display is provided. The TFT stack includes a silicon layer that includes a heavily doped region, a non-doped region, and a lightly doped region between the heavily doped region and the non-doped region. The heavily doped region is hydrogenated. The TFT stack also includes an insulation layer that includes a first portion formed over the lightly doped region and a second portion disposed over the non-doped region and a gate metal electrode layer formed over the second portion of the non-doped region. The TFT stack also includes a first dielectric layer disposed over the gate metal electrode and over the first portion of the insulation layer. The heavily doped region is hydrogenated to reduce the dependence of the capacitance between the gate metal electrode and the conductive layer Cgd upon a bias voltage being applied between the gate metal electrode and the conductive layer.

Abstract: The disclosure discloses a thin film transistor and a manufacturing method thereof, an array substrate, and a display device, which can manufacture a thin film transistor with lower contents of impurity at a low temperature. The thin film transistor comprises: a substrate, and an active layer disposed on the substrate, the active layer comprising a source region, a drain region and a channel region, wherein the active layer is formed by depositing an inducing metal on an amorphous silicon layer on the substrate by an atomic layer deposition (ALD) method and then conducting heat treatment on the amorphous silicon layer deposited with the inducing metal so that metal induction crystallization and metal induction lateral crystallization take place in the amorphous silicon layer.

Abstract: This document relates to a method of forming low-resistance metal gate and data wirings and a method of manufacturing a thin film transistor using the same. The method of the wiring includes depositing a metal layer on a base layer; exposing a portion of the base layer by removing a portion of the metal layer; forming grooves in the base layer; forming a seed layer in the grooves of the base layer; and forming a wire consisting of the seed layer and a plated layer by plating a plating material on the seed layer formed in the grooves of the base layer.

Abstract: A thin-film transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, a channel layer, and a passivation layer. The channel layer has a first surface and an opposed second surface, where the first surface is disposed over at least a portion of the gate dielectric. The channel layer also has a first oxide composition including at least one predetermined cation. The passivation layer is disposed adjacent to at least a portion of the opposed second surface of the channel layer. The passivation layer has a second oxide composition including the at least one predetermined cation of the first oxide composition and at least one additional cation that increases a bandgap of the passivation layer relative to the channel layer.

Abstract: There are provided a substrate including an oxide TFT having improved initial threshold voltage degradation characteristics included in a driving circuit of a liquid crystal display (LCD) device, a method for fabricating the same, and a driving circuit for an LCD device using the same. The substrate including an oxide thin film transistor (TFT) includes: a base substrate divided into a pixel region and a driving circuit region; and a plurality of TFTs formed on the base substrate, wherein an initial threshold voltage of at least one of the plurality of TFTs formed in the driving circuit region is positive-shifted to have a predetermined level.

Abstract: An oxide semiconductor layer with excellent crystallinity is formed to enable manufacture of transistors with excellent electrical characteristics for practical application of a large display device, a high-performance semiconductor device, etc. By first heat treatment, a first oxide semiconductor layer is crystallized. A second oxide semiconductor layer is formed over the first oxide semiconductor layer. By second heat treatment, an oxide semiconductor layer including a crystal region having the c-axis oriented substantially perpendicular to a surface is efficiently formed and oxygen vacancies are efficiently filled. An oxide insulating layer is formed over and in contact with the oxide semiconductor layer. By third heat treatment, oxygen is supplied again to the oxide semiconductor layer. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer.

Abstract: An embodiment of the invention provides a manufacturing method of a thin-film transistor includes: providing a substrate; sequentially forming a gate electrode, a gate insulating layer, and an active layer on the substrate; forming an insulating metal oxide layer covering the active layer, wherein the insulating metal oxide layer including a metal oxide of a first metal; forming a metal layer covering the active layer, wherein the metal layer includes a second metal; forming a source electrode and a drain electrode on the metal layer with a trench separating therebetween; removing the metal layer exposed by the trench; and performing an annealing process to the metal layer and the insulating metal oxide layer, such that the metal layer reacts with the insulating metal oxide layer overlapping the metal layer to form a conducting composite metal oxide layer including the first metal and the second metal.

Abstract: A thin-film semiconductor device includes: a gate electrode; a channel layer; a first amorphous semiconductor layer; a channel protective layer; a pair of second amorphous semiconductor layers formed on side surfaces of the channel layer; and a pair of contact layers which contacts the side surfaces of the channel layer via the second amorphous semiconductor layers. The gate electrode, the channel layer, the first amorphous semiconductor layer, and the channel protective layer are stacked so as to have outlines that coincide with one another in a top view. The first amorphous semiconductor layer has a density of localized states higher than those of the second amorphous semiconductor layers. The second amorphous semiconductor layers have band gaps larger than that of the first amorphous semiconductor layer.

Abstract: A thin film transistor substrate includes a base substrate, an active pattern, a gate insulation pattern and a gate electrode. The active pattern is disposed on the base substrate. The active pattern includes a source electrode, a drain electrode, and a channel disposed between the source electrode and the drain electrode. The gate insulation pattern and the gate electrode overlap with the channel. The gate insulation pattern is disposed between the channel and the gate electrode. The source electrode and the drain electrode each include a fluorine deposition layer.

Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a cap layer-free method for forming a silicide is provided. The method includes the following steps. A semiconductor material selected from: silicon and silicon germanium is provided. At least one silicide metal is deposited on the semiconductor material. The semiconductor material and the at least one silicide metal are annealed at a temperature of from about 400° C. to about 800° C. for a duration of less than or equal to about 10 milliseconds to form the silicide. A FET device and a method for fabricating a FET device are also provided.

Abstract: An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost.

Abstract: A conductive layer to be a gate electrode, an insulating layer to be a gate insulating layer, a semiconductor layer, and an insulating layer to be a channel protective layer, which are each included in a transistor, are successively formed without exposure to the air. A gate electrode (including another electrode or a wiring which is formed in the same layer) and an island-like semiconductor layer are formed through one photolithography step. A display device is manufactured through four photolithography steps including the photolithography step, a photolithography step of forming a contact hole, a photolithography step of forming a source electrode and a drain electrode (including another electrode or a wiring which is formed in the same layer), and a photolithography step of forming a pixel electrode (including another electrode or a wiring which are formed in the same layer).

Abstract: A method of forming a semiconductor structure on a substrate is provided. The method may include preparing a continuous active layer on a region of the substrate and depositing a first raised epitaxial layer on a first region of the continuous active layer. A second raised epitaxial layer is also deposited on a second region of the continuous active layer such that the first raised epitaxial layer is in close proximity to the second raised epitaxial layer. A mask may be used to etch a trench structure into the continuous active layer at both the first and the second raised epitaxial layer, whereby the etched trench structure is filled with isolation material for electrically isolating the first raised epitaxial layer from the second raised epitaxial layer.

Abstract: A thin-film semiconductor device having two thin-film transistors, wherein each of the two thin-film transistors includes: a gate electrode; a gate insulating film; a semiconductor layer; a channel protection layer; an intrinsic semiconductor layer; a contact layer in contact with a portion of sides of the channel region; a source electrode on the contact layer; and a drain electrode opposite to the source electrode on the contact layer, wherein the contact layer of one of the two thin-film transistors has a conductivity type different from a conductivity type of the contact layer of the other of the two thin-film transistors.

Abstract: In an organic light emitting diode (OLED) display and a manufacturing method thereof, the OLED display includes a substrate main body; an insulation layer pattern formed on the substrate main body, and including a first thickness layer and a second thickness layer thinner than the first thickness layer; a metal catalyst that is scattered on the first thickness layer of the insulation layer pattern; and a polycrystalline semiconductor layer formed on the insulation layer pattern, and divided into a first crystal area corresponding to the first thickness layer and to a portion of the second thickness layer adjacent to the first thickness layer and a second crystal area corresponding to the remaining part of the second thickness layer. The first crystal area of the polycrystalline semiconductor layer is crystallized through the metal catalyst, and the second crystal area of the polycrystalline semiconductor layer is solid phase crystallized.

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Abstract: The organic thin-film transistor according to the present invention includes: a gate electrode line on a substrate in a first region: a first signal line layer in a second region; a gate insulating film covering the gate electrode line and the first signal line layer; bank layers on the gate insulating film; a second signal line layer on the bank layer over the first signal line; a drain electrode and a source electrode line which are located on the bank layers and in at least one opening between the bank layers in the first region; a semiconductor layer located at least in the opening and banked up by the bank layers, the drain electrode, and the source electrode line; and a protection film covering the semiconductor layer.

Abstract: Disclosed is a thin film transistor substrate which facilitates to improve output and transfer characteristics of thin film transistor, wherein the thin film transistor substrate comprises a thin film transistor comprising a lower gate electrode on a substrate, an active layer on the lower gate electrode, source and drain electrodes on the active layer, and an upper gate electrode on the source electrode, drain electrode and active layer, the upper gate electrode for covering a channel region defined by the source and drain electrodes; and a contact portion for electrically connecting the lower gate electrode with the upper gate electrode.

Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Abstract: Disclosed are an array substrate, a method for fabricating the same and a display device. The array substrate comprises: a substrate, a gate electrode, a gate insulating layer as well as an active layer, and a source/drain metal layer formed on the substrate, the source/drain metal layer is configured for forming a source electrode, a drain electrode and a channel region, wherein a region of the S/D metal layer for forming the channel region is at a lower height than other region of the S/D metal layer for forming the source electrode and the drain electrode.

Abstract: A thin film transistor (TFT) including a gate, a gate insulator, an oxide semiconductor channel layer, a source, and a drain is provided. The gate insulator covers the gate, while the oxide semiconductor channel layer is configured on the gate insulator and located above the gate. The oxide semiconductor channel layer includes a first sub-layer and a second sub-layer located on the first sub-layer. An oxygen content of the first sub-layer is lower than an oxygen content of the second sub-layer. The source and the drain are configured on a portion of the second sub-layer. In addition, a fabricating method of the above-mentioned TFT is also provided.

Abstract: It is an object to provide a method for manufacturing a display device suitable for mass production without complicating a manufacturing process of a thin film transistor. A microcrystalline semiconductor film is formed by use of a microwave plasma CVD apparatus with a frequency of greater than or equal to 1 GHz using silicon hydride or silicon halide as a source gas, and a thin film transistor using the microcrystalline semiconductor film and a display element connected to the thin film transistor are formed. Since plasma which is generated using microwaves with a frequency of greater than or equal to 1 GHz has high electron density, silicon hydride or silicon halide which is a source gas can be easily dissociated, so that mass productivity of the display device can be improved.

Abstract: A thin film transistor substrate includes a base substrate, a gate electrode, a gate insulating layer, a surface treating layer, an active layer, a source electrode and a drain electrode. The gate electrode is formed on the base substrate. The gate insulating layer is formed on the base substrate to cover the gate electrode. The surface treating layer is formed on the gate insulating layer by treating the gate insulating layer with a nitrogen-containing gas to prevent leakage current. The active layer is formed on the surface treating layer to cover the gate electrode. The source electrode and the gate electrode that are spaced apart from each other by a predetermined distance are formed on the active layer.

Abstract: A method of manufacturing an array substrate for a liquid crystal display device includes forming gate and data lines crossing each other on a substrate; forming a thin film transistor connected to the gate and data lines; forming a passivation layer on the substrate having the gate lines, data lines and the thin film transistor; forming a first conductive material layer on the passivation layer and connected to a drain electrode of the thin film transistor; oxidizing a surface of the first conductive material layer; forming a second conductive material layer on the oxidized first conductive material layer; forming a photoresist pattern on the second conductive material layer; etching the first and second conductive material layers using the photoresist pattern to form pixel and common electrodes which are alternately arranged in the pixel region and produces an in-plane electric field; and removing the photoresist pattern.

Abstract: A thin film transistor (TFT) including a gate, a dielectric layer, a metal-oxide semiconductor channel, a source, and a drain is provided. The gate and the metal-oxide semiconductor channel are overlapped. The gate, the source, and the drain are separated by the dielectric layer. Besides, the source and the drain are respectively located on two opposite sides of the metal-oxide semiconductor channel. The metal-oxide semiconductor channel includes a metal-oxide semiconductor layer and a plurality of nano micro structures disposed in the metal-oxide semiconductor layer and separated from one another. In another aspect, a display panel including the TFT and a method of fabricating the TFT are also provided.

Abstract: A display device includes a substrate, a first conductive film pattern including a gate electrode and a first capacitor electrode on the substrate, a gate insulating layer pattern on the first conductive film pattern, a polycrystalline silicon film pattern including an active layer and a second capacitor electrode on the gate insulating layer pattern, an interlayer insulating layer on the polycrystalline silicon film pattern, a plurality of first contact holes through the gate insulating layer pattern and the interlayer insulating layer to expose a portion of the first conductive film pattern, a plurality of second contact holes through the interlayer insulating layer to expose a portion of the polycrystalline silicon film pattern, and a second conductive film pattern including a source electrode, a drain electrode, and a pixel electrode on the interlayer insulating layer.