Abstract: A simplified tri-layer process for forming a thin film transistor matrix for a liquid crystal display is disclosed. By using a backside exposure technique twice, two masking steps for patterning an etch stopper layer, and an upper doped and a lower intrinsic semiconductor layers, respectively, can be omitted. Further, owing to the back-exposing energy for patterning the semiconductor layers is less than that for patterning the etch stopper layer, the resulting etch stopper layer is enclosed with the resulting semiconductor layers, and the contact of the two semiconductor layers can be achieved.

Abstract: The present invention discloses a method for manufacturing thin film transistor liquid crystal display including the following steps so as to form simultaneously a via hole for contacting a drain electrode and a pixel electrode mutually and the channel of thin film transistor:

Abstract: A top gate, self-aligned polysilicon (poly-Si) thin film transistor (TFT) is formed using a single laser anneal to crystallize the active silicon and to activate the source-drain region. The poly-Si TFT includes a substrate, dummy gate, a barrier oxide layer, a polysilicon pattern having a source region and a drain region, a gate oxide, and a gate.

Abstract: In order to promote an effect of laser annealing in respect of a semiconductor film, moisture is intentionally included in an atmosphere in irradiating laser beam to the semiconductor film by which a temperature holding layer comprising water vapor is formed on the surface of the semiconductor film in irradiating the laser beam and the laser annealing operation can be performed effectively.

Abstract: The present invention relates to a thin film transistor and a fabricating method thereof wherein a source/drain region and a gate electrode are formed in the same layer, which improves the degree of planarization. Because source/drain electrodes and a gate electrode are formed by patterning the same layer with a single mask, the invention reduces the number of fabrication steps. The TFT includes an insulated substrate which is transparent, a source electrode and a drain electrode on the insulated substrate. The source and drain electrodes are separated from each other, and a gate electrode is between the source and drain electrodes on the insulated substrate. A gate insulating layer covers the source and drain electrodes and the gate electrodes on the gate insulating layer. An active layer is then formed on the gate insulating layer. Source and drain regions are formed at each end of the active layer corresponding to the gate electrode and a channel region is formed between the source and drain regions.

Abstract: An amorphous semiconductor film is etched so that a width of a narrowest portion thereof is 100 &mgr;m or less, thereby forming island semiconductor regions. By irradiating an intense light such as a laser into the island semiconductor regions, photo-annealing is performed to crystallize it. Then, of end portions (peripheral portions) of the island semiconductor regions, at least a portion used to form a channel of a thin film transistor (TFT), or a portion that a gate electrode crosses is etched, so that a region that the distortion is accumulated is removed. By using such semiconductor regions, a TFT is produced.

Abstract: A metal surface having optimized reflectance is created utilizing the following process steps alone or in combination: 1) performing alloy/sintering of the metal-silicon interface prior to a chemical mechanical polish of the intermetal dielectric before the reflective metal electrode is formed; 2) chemical-mechanical polishing the intermetal dielectric layer again after vias are formed; 3) forming a metal adhesion layer composed of collimated titanium over the underlying dielectric; 4) depositing metal upon the adhesion layer at as low a temperature as feasible to maintain small grain size; 5) depositing at least the first layer of the reflectance enhancing coating on top of the freshly deposited metal prior to etching the metal; and 6) depositing the initial layer of the reflective enhancing coating at a temperature as close as possible to the temperature of formation of the metal electrode layer in order to suppress hillock formation in the metal. Deposition of the REC serves two distinct purposes.

Abstract: In order to provide a method for fabricating semiconductor devices and a heat treatment apparatus in which stable annealing can be performed without causing harmful effects such as thermal stresses on an insulating substrate and the surface of a semiconductor thin film formed on the insulating substrate, in a heat treatment method for a substrate provided with an amorphous silicon film in the heating step, the substrate is preheated by irradiating the substrate from the side of one surface of the substrate with intermediate infrared rays having a wavelength band of 2.5 to 5 &mgr;m, and then, in the heat-treating step, the amorphous silicon film is annealed for crystallization at temperatures between 800 to 1,000° C. by irradiating the substrate from the side of the other surface of the substrate with near infrared rays having a wavelength band of 2.5 &mgr;m or less.

Abstract: A crystal growth 301 is carried out by diffusing a metal element, and a nickel element is moved into regions 108 and 109 which has been doped with phosphorus. An axis coincident with the moving directions 302 and 303 of the nickel element at this time is made to coincide with an axis coincident with the direction of the crystal growth, and a TFT having the regions as channel forming regions is manufactured. In the path of the region where nickel moved, since high crystallinity is obtained in the moving direction, the TFT having high characteristics can be obtained by this way.

Abstract: A catalyst element for accelerating crystallization is added to an amorphous silicon film containing an impurity element for threshold voltage control, and a heat treatment is then performed to obtain a crystalline silicon film. Thereafter, the catalyst element is gettered by performing a heat treatment in an atmosphere containing a halogen element. In this step, a chemical equilibrium state is established for the impurity element for threshold voltage control by mixing a compound gas containing the impurity element into the atmosphere, thereby preventing the impurity element from escaping into the vapor phase.

Abstract: There are disclosed techniques for providing a simplified process sequence for fabricating a semiconductor device. The sequence starts with forming an amorphous film containing silicon. Then, an insulating film having openings is formed on the amorphous film. A catalytic element is introduced through the openings to effect crystallization. Thereafter, a window is formed in the insulating film, and P ions are implanted. This process step forms two kinds of regions simultaneously (i.e., gettering regions for gettering the catalytic element and regions that will become the lower electrode of each auxiliary capacitor later).

Abstract: A method of manufacturing an active matrix substrate is provided that uses a technique of transferring a thin film device. In forming thin film transistors and pixel electrodes on an original substrate before transfer, an insulator film such as an interlayer insulation film or the like, is previously removed before the pixel electrodes are formed. Further, the original substrate is separated by exfoliation to transfer the device to a transfer material to cause the pixel electrodes to partially appear in the surface or the vicinity of the surface of the device. This portion permits application of a voltage to a liquid crystal through the pixel electrode.

Abstract: A method of fabricating silicon TFTs (thin-film transistors) is disclosed. The method comprises a crystallization step by laser irradiation effected after the completion of the device structure. First, amorphous silicon TFTs are fabricated. In each of the TFTs, the channel formation region, the source and drain regions are exposed to laser radiation illuminated from above or below the substrate. Then, the laser radiation is illuminated to crystallize and activate the channel formation region, and source and drain regions. After the completion of the device structure, various electrical characteristics of the TFTs are controlled. Also, the amorphous TFTs can be changed into polysilicon TFTs.

Abstract: First through fourth film formation chambers PC1 to PC4 are disposed in the periphery of a transfer chamber TC. If, for example, the ratio of the time required to form gate insulating films to the time required to form the silicon film as a semiconductor film is 1:3, a silicon nitride film and silicon oxide film are formed in the first through third film formation films PC1 to PC3 to become gate insulating films, and an amorphous silicon layer is formed in the fourth film formation chamber PC4 to become an active region. This makes it possible to perform formation of the amorphous silicon layer, which requires film cleaning, in a film formation chamber different from the film formation chamber for other films, and to manufacture thin-film transistors at high productivity.

Abstract: Amorphous silicon thin-film transistors on glass foil are made using exclusively electrophotographic printing for pattern formation, contact hole opening, and device isolation. Toner etch masks are applied by feeding the glass substrate through a laser printer or photocopier, or from laser-printed patterns on transfer paper. This all-printed patterning is a low-cost, large-area circuit processing technology, suitable for producing backplanes for active matrix liquid crystal displays.

Abstract: The present invention includes patterning a metal layer on a glass substrate. A dielectric layer is formed on the metal layer. An amorphous silicon layer is subsequently formed on the dielectric layer. A first positive photoresist is formed on the amorphous silicon layer. Then, a back-side exposure is used by using the gate electrodes as a mask. A bake step is performed to expand the lower portion of the photoresist. Next, a second positive photoresist layer is formed on the amorphous silicon layer and the residual first positive photoresist layer. A further back-side exposure is employed again from the back side of the substrate using the gate electrode as the mask. A second back step is applied to expand the lower portion of the second positive photoresist layer. An ion implantation is performed by using the second positive photoresist as a mask. Next, the substrate is then annealed. Amorphous silicon layer is then patterned.

Abstract: A liquid crystal transducer pixel cell includes support pillars separating a top and bottom plate of the cell. During the process for forming the pixel cell, the support pillars are formed prior to formation of the pixel electrode. This process flow obviates the need for depositing a thick dielectric layer on top of the pixel electrode. This process flow also prevents exposure of the surface of the pixel electrode to etching during subsequent processing, preserving the reflectance of the pixel cell electrode. Finally, the process flow in accordance with the present invention eliminates the creation of keyhole voids within the support pillars by forming the support pillars over a flat upper level intermetal dielectric rather than over narrow trenches formed in the pixel electrode layer.

Abstract: A thin semiconductor film device according to the present invention includes an insulative substrate, a metal layer formed on the insulative substrate, and a metal oxide layer formed on the metal layer. The metal oxide layer is obtained from anodization of the metal layer. In a preferred embodiment, an insulation film of silicon oxide or silicon nitride is formed on the metal oxide layer, and a semiconductor layer obtained by crystallizing the amorphous silicon layer is formed on the insulation film.

Abstract: An ITO (indium tin oxide) layer and a negative photoresist are deposited sequentially on the substrate 100 having a gate wire, a storage wire, a data wire and a storage electrode. The negative photoresist is developed through front exposure and the ITO layer is etched to form a pixel electrode. Because the portions of negative photoresist exposed to light remain after development, pixel defects due to particles placed between pixel regions are reduced. Both the rear exposure and the front exposure may be used. In the rear exposure, it is difficult to remain the portions of the ITO layer at the positions corresponding to the contact portion of the drain electrode and the pixel electrode, the storage line, the gate pads and the data pads. Accordingly, the front exposure is then executed by using the first mask having openings thereon. The negative photoresist is developed, and the ITO layer is patterned.

Abstract: The present invention discloses a technology for forming a thin film transistor. There is provided an insulating substrate having a gate electrode and a gate insulating layer for protecting the gate electrode thereon. A first semiconductor layer is then formed on the substrate. An insulating layer for etch stopper is formed on the first semiconductor layer and the gate insulating layer. A photoresist film is coated on the whole surface of the resultant structure. A selected portion of the photoreist film is exposed to light by projecting a linear light to a section starting from the backside of the substrate to the photoresist film, the substrate being moved horizontally. Etch stopper layer is formed by developing the exposed photoresist film and then removing the remaining photoresist film.

Abstract: In a large-sized liquid crystal display panel formed through multiple time exposure using a single mask, the storage capacity between a gate and a source of TFT is adjusted by making an offset for exposure at the exposure connecting portion to decrease variations in the feedthrough voltage in a screen. Further, by preparing the layout of an exposure mask such that the overlap area between a gate signal wire or a storage wire and a pixel electrode is made smaller the farther the overlap area is from a gate signal input part. By making the overlap area smaller, the storage capacity is made smaller, which decreases the variation of the feedthrough voltage in the single exposure area.

Abstract: The present invention includes forming a conductive layer on a substrate. Portions of the conductive layer are removed using a first photoresist layer as a mask. A first oxide layer is formed over the conductive layer and the substrate, and an amorphous silicon layer is then formed on the first oxide layer. After annealing the amorphous silicon layer, thereby transforming amorphous silicon layer to a polysilicon layer, a second oxide layer is formed on the polysilicon layer. The second oxide layer is removed using a second photoresist layer as a mask. An amorphous silicon carbon layer is formed over the second oxide layer and the polysilicon layer, and a heavily-doped amorphous silicon carbon layer is formed on the amorphous silicon carbon layer.

Abstract: A method of manufacturing an inverse-staggered self-aligned thin film transistor on a substrate having a front surface and a back surface is provided. The method includes the steps of (a) forming a gate electrode over the front surface of the substrate,(b) forming a gate insulating layer over the gate electrode,(c) forming a semiconductor active layer over the gate insulating layer adjacent the gate electrode. The method further includes the steps of (d) forming an impurity-doped semiconductor layer over the active layer and (e) radiating a laser beam from the back side of the substrate using the gate electrode as a mask to substantially crystallize portions of the active layer and the impurity-doped semiconductor layer to define source and drain regions in the active layer.

Abstract: The present invention relates to a method for manufacturing TFTs in which a gate electrode is first formed on a transparent glass substrate by depositing and patterning a first metal layer. Next, a first insulating layer, a semiconductor layer, impurity-containing semiconductor layer and a second insulating layer are deposited over the first metal layer and the substrate surface. The insulating layer is patterned followed by deposition of a second metal layer. First portions of the second metal layer and the impurity-containing semiconductor layer along with part of the second insulating layer are etched over the gate electrode (thereby forming source and drain electrodes) at the same time second portions of the second metal layer and impurity-containing semiconductor layer and portions of the semiconductor layer laterally spaced from the gate electrode are etched. As a result, the number of etching steps is reduced, and the second insulating layer controls the etching speed.

Abstract: Method of fabricating semiconductor devices such as thin-film transistors by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron, cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.

Abstract: This invention relates to a method for fabricating a thin film transistor used for LCD which can improve performance and productivity of an element by forming it with atmospheric pressure CVD method including processes for forming a gate electrode having sloped sides on an insulation substrate, forming a gate insulation film, a semiconductor layer and a channel protection layer successively with atmospheric pressure chemical vapor deposition method on all over the insulation substrate, patterning the channel protection layer such that the channel protection layer is to have a narrower pattern width than the pattern width of the gate electrode remaining the channel protection layer only on the semiconductor layer over the gate electrode, forming an impurity injected semiconductor layer for making resistive contact by injecting impurities into the semiconductor layer using the channel protection layer as a mask, and forming source and drain electrodes over the channel protection layer, the impurity injected sem

Abstract: In a method of fabricating a high resolution low voltage flat panel radiation imaging sensor having a radiation transducer having a radiation conversion layer of amorphous semiconductor and an electrode on one side thereof and an array of pixels arranged in rows and columns on an opposite side thereof, each pixel including a pixel electrode and storage capacitor and a charge readout device connected to the pixel electrode and the storage capacitor, the improvement comprising the step of shining light on selected regions of the radiation conversion layer which are aligned with the pixel electrodes to thereby crystallize the regions, resulting in a plurality of low resistivity and high charge mobility crystallized regions where the semiconductor material has been exposed to the light surrounded by high resistivity and low charge mobility regions where the semiconductor material has not been exposed to the light, for preventing lateral charge diffusion between respective ones of the low resistivity and high char

Abstract: A laser processing process which comprises laser annealing a silicon film 2 .mu.m or less in thickness by irradiating a laser beam 400 nm or less in wavelength and being operated in pulsed mode with a pulse width of 50 nsec or more, and preferably, 100 nsec or more.A laser processing apparatus which comprises a laser generation device and a stage for mounting thereon a sample provided separately from said device, to thereby prevent transfer of vibration attributed to the movement of the stage to the laser generation device and the optical system. A stable laser beam can be obtained to thereby improve productivity.

Abstract: The present invention is related to a method for manufacturing a thin film transistor which can improve the yield, characteristics and reliability of the thin film transistor by selectively forming a semiconductor layer on a desired portion using a of a substrate using a temperature difference of the surface of a substrate achieve by heating the substrate with a lamp. The method comprises the steps of forming a black matrix layer of metal on a portion of the whole surface of an insulating glass substrate, forming an insulating layer for protecting the substrate on the whole substrate including the black matrix layer, forming source/drain electrodes on the insulating layer over the black matrix, selectively forming a semiconductor layer on the insulating layer including the source/drain electrodes, forming a gate insulating layer and forming a gate electrode.

Abstract: Method for forming a polycrystalline silicon (ploy-Si) film of a semiconductor device includes forming the gate electrode on a substrate and depositing a dielectric layer on the substrate and the conductive layer. Then a first layer (microcrystalline silicon:.mu.c-Si) is formed on the dielectric layer and a second layer (hydrogenated amorphous silicon:a-Si:H) is deposited on the first layer. Noted that the polycrystalline silicon (poly-Si) can be fabricated by applying the laser annealing to the first layer and the second layer to transform them to poly-Si. Annealing the first layer and the second layer by laser, followed by fabricating the source and drain electrodes, thus the TFT with good electrical characteristics is fabricated.

Abstract: A process for manufacturing a thin film transistor for use in a CMOS SRAM circuit is described. A key feature is the formation of two different photoresist masks from the same optical mask. The first photoresist mask is generated using a normal amount of actinic radiation during exposure and is used to protect the gate region during source and drain formation through ion implantation. The second photoresist mask is aligned relative to the gate in exactly the same orientation as the first mask but is given a reduced exposure of actinic radiation. This results, after development, in a slightly larger mask which is used during etching to form the oxide cap that will protect the channel area during the subsequent silicidation step. Making the cap slightly wider than the channel ensures that small lengths of the source and the drain regions that abut the channel are not converted to silicide. Thus, the finished device continues to act as a thin film transistor, but has greatly reduced source and drain resistances.

Abstract: A method for crystallizing a portion of a semiconductor thin film while forming a semiconductor device comprises providing a transparent substrate supporting a metallic gate electrode and an amorphous semiconductor thin film which are separated from each other by a gate insulating film, heating the gate electrode by subjecting it to light rays, and applying a laser beam to the amorphous semiconductor thin film so that the portion of the semiconductor thin film adjacent the metallic gate electrode is heated by both the laser beam and the heat of the gate electrode to cause a crystallization of a portion of the amorphous thin film and then processing the remaining amorphous portions of the thin film to form the transistor structure.

Abstract: A composite-layer semiconductor device includes a gate above a host substrate, an n++ contact layer above the gate, and source and drain ohmic contacts applied to the n++ contact layer. The source and drain ohmic contacts define a central gate location which is recessed through the n++ contact layer toward the gate. The source and drain ohmic contacts create a barrier to chemical etching so that a current path below the central gate location can be incrementally recessed in repeated steps to precisely tailor the operating mode of the device for depletion or enhancement applications. The composite-layer semiconductor device is fabricated by depositing a gate on an n++ contact layer above a semi-insulating substrate. The semi-insulating substrate and gate are flipped onto an epoxy layer on the host substrate so that the gate is secured to the epoxy layer and the semi-insulating substrate presents an exposed backside. A portion of the exposed backside is removed.

Abstract: The present invention includes forming a conductive layer on a substrate. Portions of the conductive layer are removed using a first photoresist layer as a mask. A first oxide layer is formed over the conductive layer and the substrate, and an amorphous silicon layer is then formed on the first oxide layer. After annealing the amorphous silicon layer, thereby transforming amorphous silicon layer to a polysilicon layer, a second oxide layer is formed on the polysilicon layer. The second oxide layer is removed using a second photoresist layer as a mask. An amorphous silicon carbon layer is formed over the second oxide layer and the polysilicon layer, and a heavily-doped amorphous silicon carbon layer is formed on the amorphous silicon carbon layer.

Abstract: An amorphous silicon thin film transistor (a-Si TFT) or other a-Si device is produced by depositing and lithographically patterning a layer of doped semiconductor material such as microcrystalline or polycrystalline silicon to produce a conductive lead. The semiconductor material is deposited over an insulating region and over an exposed part of an amorphous silicon layer. The insulating region has an edge that is over and approximately aligned with an edge of a gate region. The doped semiconductor layer therefore forms a junction to the amorphous silicon layer at the edge of the insulating region, approximately aligned with the edge of the gate region. Self-aligned lithographic patterning is performed in such a way that the conductive lead overlaps the insulating region by a distance that is no more than a maximum overlap distance. The maximum overlap distance can, for example, be no more than 1.0 .mu.m, and can be 0.5 .mu.m.

Abstract: A method for making a completely self-aligned thin film transistor panel of a liquid crystal display includes the steps of: forming a gate electrode on a transparent substrate; depositing sequentially a first insulating layer, a semiconductor protecting layer aligned with the gate electrode by patterning the second insulating layer; implanting ions into the semiconductor layer; depositing a conductive layer; patterning the conductive layer together with the semiconductor layer; forming a passivation layer including both a first opening and a second opening, forming a pixel electrode connected to the conductive layer through the second opening; etching the conductive layer by using both the pixel electrode and the passivation layer as a mask to form a source electrode and a drain electrode. The conductive layer and semiconductor layer are patterned in a single process step in the present invention, while the conductive layer and semiconductor layer are separately patterned in the conventional method.

Abstract: A manufacturing method for a semiconductor device is preferably used for a semiconductor device using SOI (Silicon on Insulation) technology. At minimum, the method includes the following steps: the step of forming a gate electrode on a substrate by using a light-intercepting material; of forming a gate insulating film on the substrate including the gate electrode; of forming a semiconductor layer on the gate insulating film; and of forming a source region and a drain region by virtue of the fact that light, having a wavelength such that the light is absorbed into the semiconductor layer while not being absorbed into the substrate, is irradiated from the back of the substrate, before supplying impurities into the semiconductor layer.

Abstract: A method of fabricating a lightly doped drain thin-film transistor having an inverted staggered structure is disclosed. The transistor has a glass substrate and a gate formed by a Cr layer on the substrate. An insulating layer and a semiconductor layer are deposited on the substrate and the gate. A first photo-resist layer is coated on top of the semiconductor layer. Back-side exposure and self-aligned technique are used to form an unexposed area slightly smaller than the gate area with high energy light. Low energy ion implantation is then performed on the exposed semiconductor layer to produce the lightly doped region. After removing the first photo-resist layer, another photo-resist process including a second photo-resist coating, back-side exposure and self-aligned technique is performed to form an unexposed area slightly larger than the gate area with low energy light. High energy ion implantation is then performed on the exposed semiconductor layer.