Abstract: A method of fabricating metal oxide TFTs on transparent substrates includes the steps of positioning an opaque gate metal area on the front surface of the substrate, depositing transparent gate dielectric and transparent metal oxide semiconductor layers overlying the gate metal and a surrounding area, depositing transparent passivation material on the semiconductor material, depositing photoresist on the passivation material, exposing and developing the photoresist to remove exposed portions, etching the passivation material to leave a passivation area defining a channel area, depositing transparent conductive material over the passivation area, depositing photoresist over the conductive material, exposing and developing the photoresist to remove unexposed portions, and etching the conductive material to leave source and drain areas on opposed sides of the channel area.

Abstract: A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact.

Abstract: Methods of fabricating a TFT and an OLED using the same are provided. The method of fabricating a CMOS TFT includes: preparing a substrate having first and second TFT regions; forming a gate electrode on the substrate; forming a gate insulating layer on the entire surface of the substrate including the gate electrode; forming a semiconductor layer on a predetermined region of the gate insulating layer using a mask; exposing the back of the mask using the gate electrode; injecting n-type impurity ions into the semiconductor layers of the first and second TFT regions using the back-exposed mask and forming a channel region and source and drain regions; ashing both sides of the back-exposed mask; injecting low concentration impurity ions into the semiconductor layers of the first and second TFT regions using the ashed mask and forming an LDD region; and injecting p-type impurity ions into the semiconductor layer of the second TFT region and forming source and drain regions.

Abstract: A method of TFT (Thin Film Transistor) manufacturing and a substrate structure are provided. The structure includes a substrate and a self-alignment mask. A self-alignment mask on a substrate is first manufactured and then the self-alignment mask may synchronously extend with the substrate during the thermal process. When an exposure light source is provided on the side without a TFT formed, the self-alignment mask can overcome the problem that when a plastic substrate extends, the positions of the source and drain to be formed on the plastic substrate are incorrect, which has a great effect on the accuracy of alignment. As the result, the positions of the source and drain can be defined accurately.

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract: The present invention relates to a thin film transistor substrate and a fabricating method thereof. The thin film transistor according to one embodiment of the present invention comprises: a gate wire and a data wire formed to cross each other on an insulating substrate and define a pixel area; a thin film transistor formed on the intersection of the gate wire and the data wire; an inorganic insulating layer covering the thin film transistor and having a surface that a prominence and depression pattern formed on; and a reflective layer provided on the prominence and depression pattern. Thus, the present invention provides a thin film transistor substrate and a fabricating method thereof, which reduce the time required in the process and enhance the productivity.

Abstract: A method for fabricating a pixel structure of a liquid crystal device is provided. The method comprises providing a substrate defining a thin film transistor (TFT) region and a display region thereon. An opaque conductive layer is formed on the TFT region, and a transparent pixel electrode is formed on the display region. A patterned photoresist passivation layer is formed by backside exposure process on the TFT region, wherein the opaque conductive layer serves as the photo-mask during the backside exposure process. The photoresist passivation layer is subjected to a middle bake process to be reflowed, resulting in a complete covering of the opaque conductive layer.

Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

Abstract: In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.

Abstract: An exposure mask is provided, which includes: a light blocking opaque area blocking incident light; a translucent area; and a transparent area passing the most of incident light, wherein the translucent area generates the phase differences in the range of about ?70° to about +70°.

Abstract: It is made possible to form a silicon nitride film, an aluminum oxide film and a transition metal high-k insulation film of high quality. A manufacturing method includes: forming an insulation film having at least one kind of bonds selected out of silicon-nitrogen bonds, aluminum-oxygen bonds, transition metal-oxygen-silicon bonds, transition metal-oxygen-aluminum bonds, and transition metal-oxygen bonds on either a film having a semiconductor as a main component or a semiconductor substrate, and irradiating the insulation film with pulse infrared light having a wavelength corresponding to a maximum intensity in a wavelength region depending upon the insulation film and having a wavelength absorbed by the insulation film.

Abstract: The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.

Abstract: A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.

Abstract: A manufacturing method of a thin film transistor array substrate incorporating the manufacture of a photo-sensor is provided. In the manufacturing method, a photo-sensing dielectric layer is formed between a transparent conductive layer and a metal electrode for detecting ambient light. Since the transparent conductive layer is adopted as an electrode, the ambient light can pass through the transparent conductive layer and get incident light into the photo-sensing dielectric layer. Therefore, the sensing area of the photo-sensor can be enlarged and the photo-sensing efficiency is improved. In addition, the other side of the photo sensitive dielectric layer may be a metal electrode. The metal electrode can block the backlight from getting incident into the photo-sensing dielectric layer and thus reduce the background noise. A manufacturing method of a liquid crystal display panel adopting the aforementioned thin film transistor array substrate is also provided.

Abstract: A pixel structure fabricating method is provided. A gate and a gate insulation layer covering the gate are formed on a substrate. A channel layer is formed on the gate insulation layer. A conductive layer is formed on the channel layer and gate insulation layer. A black matrix having a color filer layer accommodating opening is formed on the conductive layer. The black matrix includes a first block and a second block which is thicker than the first block. The conductive layer is patterned with the black matrix as a mask to form a source and a drain on the channel layer. A color filter layer is formed within the color filter layer accommodating opening through inkjet printing. A dielectric layer is formed on the black matrix and color filter layer. The dielectric layer is patterned to expose the drain. A pixel electrode electrically connected to the drain is formed.

Abstract: A semiconductor device having a crystalline semiconductor film with production of a cavity suppressed and a manufacturing method thereof A manufacturing method of a semiconductor device according to the invention comprises the steps of forming an amorphous silicon film on a substrate having an insulating surface, adding a metal element such as Ni for promoting crystallization to the amorphous silicon film, applying heat treatment to crystallize the amorphous silicon film, so that a crystalline silicon film is formed on the substrate, removing a silicon oxide film formed on the surface of the crystalline silicon film due to the heat treatment by a solution containing organic solvent and fluoride, and irradiating laser light or strong light to the crystalline silicon film.

Abstract: There is provided a new method of obtaining the dopant activation rate of a device accurately and simply in a different way from a method of obtaining a carrier density with use of a Hall measurement or CV measurement, and also provided a production method of a device performed with a proper threshold voltage control, that is, a dose amount control, according to the obtained activation rate. The inventor devised a method in which the activated dopant density (first dopant density) in a semiconductor film is obtained from the threshold voltage and the flat band voltage of a device, then the dopant activation rate is obtained from the ratio of the obtained activated dopant density to the added dopant density (second dopant density) obtained by SIMS analysis. The invention allows easily obtaining the dopant activation rate in the channel region and the impurity region of the device.

Abstract: A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.

Abstract: A thin film transistor substrate and a method for manufacturing the same are provided. The thin film transistor substrate has a display area and a pad area defined in the vicinity of the display area, and includes a signal line formed in the display area and a signal pad formed in the pad area, and at least one connecting line which connects the signal line and the signal pad and includes a first line and a second line disposed on the first line. In addition, at least one of the first line and the second line has centrally isolated, spaced apart stepped structures.

Abstract: A thin film transistor (TFT) array substrate for a liquid crystal display comprises a gate line and a data line formed in a display region, a gate connecting line and a data connecting line formed in a PAD region, and a TFT formed at an intersection between the gate line and the data line. The TFT comprises a gate electrode on a base substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, a doped semiconductor layer on the semiconductor layer, and a source electrode and a drain electrode that are on the doped semiconductor layer, and a TFT channel is defined in the semiconductor layer between the source electrode and the drain electrode. The array substrate further comprises a passivation layer that is formed on the source electrode and the drain electrode and a pixel electrode, a portion of which is formed under the drain electrode and connected with the drain electrode.

Abstract: A disclosed technology is a method for exposing a photo-sensitive SAM film, wherein a self-assembled-monolayer (photo-sensitive SAM film) having photo-sensitivity, exhibiting hydrophobicity before exposure, and exhibiting hydrophilicity after exposure is formed on a substrate, exposure is performed to the substrate in a state in which a surface of the substrate on which the film has been formed is dipped in liquid or in a state in which a light-sensitive surface of the substrate faces downward to be in contact with liquid, exposure light is ultraviolet light, visible light, or light with an exposure-wavelength of 350 nm or more to 800 nm or less, and the liquid is at least one of organic solvent containing an aromatic group and organic solvent of alcohols, ethers, or ketones.

Abstract: A method of fabricating a TFT array substrate and a metal layer thereof is provided. First, a substrate having a first patterned metal layer disposed thereon is provided, wherein the first patterned metal layer is formed by an electroplating method. Then, a gate insulating layer is formed on the substrate, wherein the gate insulating layer covers the first metal layer. Next, a semiconductive layer is formed on the gate insulating layer over the first metal layer. Then, a patterned second metal layer is formed on the semiconductive layer. The first metal layer, the second metal layer and the semiconductive layer constitute a plurality of thin film transistors, a plurality of scanning lines and a plurality of data lines, wherein the scanning lines and the data lines are coupled to the thin film transistors.

Abstract: A fabrication method of an active device array substrate is disclosed. A first metal material layer, a gate insulation material layer, a channel material layer, a second metal material layer, and a first photoresist layer are formed over a substrate sequentially. The first photoresist layer is patterned with a multi-tone mask to form a first patterned photoresist layer with two thicknesses. A first and second removing processes are performed sequentially using the first patterned photoresist layer as a mask to form a gate, a gate insulation layer, a channel layer, and a source/drain. The first patterned photoresist layer is removed. A passivation layer and a second patterned photoresist layer are formed over the substrate. A third removing process is performed to form a plurality of contact holes. A pixel electrode material layer is formed over the substrate. The second patterned photoresist layer is lifted off to form a pixel electrode.

Abstract: A method of making a source-gated transistor is described, in which a gate (4) is provided on substrate (2) followed by gate insulator (6) and semiconductor layer (8). The layer is patterned to align the source with the gate (4) using photoresist (12) and back illumination through the substrate (2) with the gate (4) acting as a mask. The distance between source and drain may also be self-aligned using a spacer technique.

Abstract: A method of manufacturing a display substrate is described. In the method, a gate line and a gate electrode are formed on a base substrate. A source metal layer is formed on the base substrate having the gate line and the gate electrode. A data line, a source electrode and a drain electrode are formed by etching the source metal layer by using an etching gas. An additive gas is provided to the base substrate having the drain electrode so that the additive gas reacts with an etching component of the etching gas to remove a by-product formed at an exposed portion of the data line, the source electrode and drain electrode. Thus, corrosion of the fine pattern due to an etching gas may be prevented and/or reduced.

Abstract: A pixel structure including a gate, a gate dielectric layer, a patterned semiconductor layer having a channel area disposed above the gate, a patterned dielectric layer having an etching-stop layer disposed above the gate and a number of bumps, a patterned metal layer having a reflective pixel electrode, a source and a drain, an overcoat dielectric layer, and a transparent pixel electrode sequentially disposed on a substrate is provided. The source and the drain respectively cover portions of the channel area. The reflective pixel electrode connects the drain and covers the bumps to form an uneven surface. The overcoat dielectric layer disposed on a transistor constituted by the gate, the gate dielectric layer, the patterned semiconductor layer, the source and the drain has a contact opening exposing a portion of the reflective pixel electrode. The transparent pixel electrode is electrically connected to the reflective pixel electrode through the contact opening.

Abstract: A liquid crystal display unit structure and the manufacturing method thereof are provided. The method comprises the following steps: forming a patterned first metal layer with a first data line segment and a lower gate pad on a substrate; forming a patterned dielectric layer covering the first data line and the lower gate pad having a plurality of first openings and a second opening therein, forming a patterned second metal layer including a common line, a second data line segment and a upper gate pad, wherein the upper gate pad is electrically connected to the lower gate pad through the first openings, and the second data line segment is electrically connected to the first data line segment through the first openings; finally forming a patterned passivation layer and a patterned transparent conductive layer.

Abstract: A method for manufacturing a bottom substrate of a liquid crystal display device is disclosed. The method is achieved by proceeding two lithography processes cycles with a single mask. Therefore, the method of the present invention can manufacture a bottom substrate through five lithography processes cycles with only four masks. Thus, the cost of a liquid crystal display device can be reduced due to the absence of the manufacturing cost of one mask.

Abstract: The present invention provides a liquid crystal display device including a substrate, a first conductive layer disposed on the substrate, a gate insulating layer covering the first conductive layer, and a second conductive layer disposed on the gate insulating layer, wherein the first conductive layer including a first sub-data line and a gate line, the second conductive layer including a source electrode and a common electrode, and the common electrode is disposed opposite to the first conductive electrode, and a method of making the same with five photolithographic and etching processes.

Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

Abstract: A method of manufacturing a thin film transistor array substrate according to the present invention includes: forming a pattern made of a first conductive film; stacking a gate insulating film, a semiconductor layer, and a resist in the stated order; forming a resist pattern having a step structure in a thickness direction; forming an exposed area of the first conductive film and a pattern of the semiconductor layer by using the resist pattern; forming a pattern made of a second conductive film in contact with the first conductive film in the exposed area of the first conductive film; and forming a pattern made of a third conductive film. The first conductive film forms a gate electrode, and the second conductive film forms each of a source electrode and a drain electrode. The third conductive film forms a pixel electrode, and the second conductive film is coated with an upper-layer film.

Abstract: The present invention provides production methods of a pattern thin film, a semiconductor element and a circuit substrate, capable of eliminating the number of photolithography processes needed for patterning; and a semiconductor element, a circuit substrate, and an electron device obtained by the production methods. The production method of the pattern thin film of the present invention is a production method of a pattern thin film, comprising the steps of: forming a first resist pattern film on a thin film formed on a substrate; forming a second resist pattern film; patterning the thin film using at least the second resist pattern film, wherein in the step of forming the second resist pattern film, a fluid resist material or an organic solvent is applied on a groove of a bank pattern formed using the first resist pattern film.

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched.

Abstract: The embodiment of the invention discloses an exemplary method, in which a gate line, a gate electrode, and a pixel electrode are formed in a first step; a multilayer structure is formed on the gate line and the gate electrode in a second step; and a data line and source/drain electrodes are formed in a third step.

Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

Abstract: In a semiconductor device, a first interlayer insulating layer made of an inorganic material and formed on inverse stagger type TFTs, a second interlayer insulating layer made of an organic material and formed on the first interlayer insulating layer, and a pixel electrode formed in contact with the second interlayer insulating layer are disposed on a substrate, and an input terminal portion that is electrically connected to a wiring of another substrate is provided on an end portion of the substrate. The input terminal portion includes a first layer made of the same material as that of the gate electrode and a second layer made of the same material as that of the pixel electrode. With this structure, the number of photomasks used in the photolithography method can be reduced to 5.

Abstract: An exposure mask is provided, which includes: a light blocking opaque area blocking incident light; a translucent area; and a transparent area passing the most of incident light, wherein the translucent area generates the phase differences in the range of about ?70° to about +70°.

Abstract: Provided are a chip, a chip stack, and a method of manufacturing the same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in a via hole exposing the bottom of the pad are stacked such that the pad and the metal layer of adjacent chips are bonded. This leads to a simplified manufacturing process, high chip performance and a small footprint for a chip stack.

Abstract: To provide a display device having a thin film transistor with high electric characteristics and excellent reliability and a manufacturing method thereof. A gate electrode, a gate insulating film provided over the gate electrode, a first semiconductor layer provided over the gate insulating film and having a microcrystalline semiconductor, a second semiconductor layer provided over the first semiconductor layer and having an amorphous semiconductor, and a source region and a drain region provided over the second semiconductor layer are provided. The first semiconductor layer has high crystallinity than the second semiconductor layer. The second semiconductor layer includes an impurity region having a conductivity type different from a conductivity type of the source region and the drain region between the source region and the drain region.

Abstract: An object of the present invention is to provide a structure of a thin film circuit portion and a method for manufacturing a thin film circuit portion by which an electrode for connecting to an external portion can be easily formed under a thin film circuit. A stacked body including a first insulating film, a thin film circuit formed over one surface of the first insulating film, a second insulating film formed over the thin film circuit, an electrode formed over the second insulating film, and a resin film formed over the electrode, is formed. A conductive film is formed adjacent to the other surface of the first insulating film of the stacked body to be overlapped with the electrode. The conductive film is irradiated with a laser.

Abstract: There are provided two subpixels opposite each other with respect to each data line. A pair of gate lines are provided for each row of pixels. A plurality of subsidiary signal lines are provided between the adjoining columns of the pixels. The data lines and the subsidiary signal lines are alternately arranged between the adjoining columns of the pixels. A storage wire is provided between the adjoining rows of the pixel 12+66s.

Abstract: A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode, forming a gate insulating layer on the gate line, forming a semiconductor stripe on the gate insulating layer; forming ohmic contacts on the semiconductor stripe, forming a data line including a source electrode and a drain electrode on the ohmic contacts, depositing a passivation layer on the data line and the drain electrode, and forming a pixel electrode connected to the drain electrode.

Abstract: A method for making a semiconductor apparatus including the steps of: forming a laminate structure of an insulating film made of a metal oxide and a semiconductor thin film on a substrate; forming a light absorption layer on top of the laminate structure; and irradiating an energy beam of a wavelength capable of being absorbed by the light absorption layer on the light absorption layer and simultaneously crystallizing the insulating film and the semiconductor thin film by means of heat generated in the light absorption layer.

Abstract: A display substrate includes a base substrate, a first metal pattern, a gate insulating layer, a second metal pattern, a channel layer and a pixel electrode. The first metal pattern is formed on the base substrate, and includes a gate line and a gate electrode of a switching element. The gate insulating layer is formed on the base substrate including the first metal pattern. The second metal pattern is formed on the gate insulating layer, and includes a source electrode, a drain electrode and a source line. The channel layer is formed under the second metal pattern, and is patterned to have substantially a same side surface as a side surface of the second metal pattern. The pixel electrode is electrically connected to the drain electrode. Therefore, an afterimage on a display panel, thus improving display quality.

Abstract: A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.

Abstract: A method of fabricating an array substrate for a liquid crystal display device comprises forming a gate line, a data line that crosses the gate line and a thin film transistor connected to the gate line and the data line on a substrate, and forming an organic insulating material layer on the gate line, the data line and the thin film transistor. The organic insulating material layer has photo curability, flexibility and dynamic stability. The method further comprises forming a passivation layer that has a drain contact hole from the organic insulating material layer by using a stamp that has a convex portion. The drain contact hole exposes a drain electrode of the thin film transistor. The method also comprises forming a pixel electrode on the passivation layer. The pixel electrode is connected to the drain electrode through the drain contact hole.

Abstract: Fabrication methods for making thin film devices on transparent substrates are described. Gate, source, and drain electrodes of a transistor are formed on a transparent substrate. The widths of the drain electrode and source electrodes are greater than a width of the gate electrode. A dielectric layer is formed on the gate electrode. A semiconductor layer is deposited proximate to the gate, source and drain electrodes. Photoresist is deposited on the semiconductor. The photoresist is exposed to light directed through the transparent substrate so that the gate electrode masks the photoresist from the light. The semiconductor layer is removed in regions exposed to the light.

Abstract: According to various exemplary embodiments of this invention, a method of producing a semiconductor structure is provided that includes providing a layered structure on a first substrate, the layered structure including a silicon layer that is provided over a first dielectric layer, a first dielectric layer that is provided over an etch-stop layer, the etch-stop layer provided over a buffer layer, the buffer layer provided over a sacrificial layer, and a sacrificial layer provided over a first substrate. Moreover, various exemplary embodiments of the methods of this invention provide for a second substrate over the layered structure, separating the first substrate and the sacrificial layer from the buffer layer, separating the buffer layer and the etch-stop layer from the first dielectric layer and providing a drain electrode and a source electrode over the layered structure.

Abstract: A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain embodiments two or more matched devices, such as in a common centroid layout, are fabricated in the interior area. The guard ring is formed on at least one particular layer for a particular processing step. By the guard ring overwhelming the effect of local features' elevation differences, photoresist thereafter applied consequently has a more uniform height across the interior area, resulting in more uniform devices. In some embodiments, a plurality of guard rings enclosing respective arrays of matched devices are arranged over the surface of a semiconductor wafer, spaced apart so as to be not local to one another. Based on the equalizing effect by each of the guard rings, the respective devices arranged in the interior areas are more evenly matched to equivalent devices in far-spaced guard rings. Thus, both local and global matching are achieved.

Abstract: An ITO (indium tin oxide) layer and a negative photoresist are deposited sequentially on the substrate 100 having a gate wire, a storage wire, a data wire and a storage electrode. The negative photoresist is developed through front exposure and the ITO layer is etched to form a pixel electrode. Because the portions of negative photoresist exposed to light remain after development, pixel defects due to particles placed between pixel regions are reduced. Both the rear exposure and the front exposure may be used. In the rear exposure, it is difficult to remain the portions of the ITO layer at the positions corresponding to the contact portion of the drain electrode and the pixel electrode, the storage line, the gate pads and the data pads. Accordingly, the front exposure is then executed by using the first mask having openings thereon. The negative photoresist is developed, and the ITO layer is patterned.