Semiconductor Islands Formed Upon Insulating Substrate Or Layer (e.g., Mesa Formation, Etc.) Patents (Class 438/164)
  • Patent number: 10312105
    Abstract: A method of fabricating a semiconductor device includes forming a linear preliminary mask pattern in a first direction on a substrate. The preliminary mask pattern is patterned to provide a plurality of mask patterns that are aligned end-to-end with one another on the substrate and are separated by an exposed portion of the substrate between respective facing ends of the plurality of mask patterns. An auxiliary layer is formed to cover at least sidewalls of the facing ends to reduce a size of the exposed portion to provide a reduced exposed portion of the substrate and the reduced exposed portion of the substrate is etched to form a trench defining active patterns in the substrate aligned end-to-end with one another.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-Sic Yoon, Jiung Pak, Kiseok Lee, Chan Ho Park, Hyeonok Jung
  • Patent number: 10312347
    Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10242947
    Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: March 26, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony K. Stamper, Mukta G. Farooq, John A. Fitzsimmons
  • Patent number: 10217848
    Abstract: A thin film transistor (TFT) structure is provided herein, which comprises a substrate, a light-shielding resin, a polysilicon, a gate electrode insulator, a gate electrode, an interlayer dielectric layer, a source electrode, and a drain electrode. The light-shielding resin has functions of light-shielding and insulation. With doping through two through holes at two sides, the manufacturing process is simplified, the exposure process is simplified, the production time is shortened, the usage of masks is decreased, and the production cost is lowered.
    Type: Grant
    Filed: June 12, 2016
    Date of Patent: February 26, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventors: Wanghua Tu, Wanting Yin
  • Patent number: 10177037
    Abstract: A method includes providing a semiconductor structure having a substrate and a plurality of fins extending upwards from the substrate. A CT pillar layer is disposed over the semiconductor structure. A CT mask is lithographically patterned over the CT pillar layer. The CT mask is anisotropically etched to remove exposed portions of the CT pillar layer and to form a CT pillar between the fins. A dummy gate structure is disposed across the CT pillar. The dummy gate structure is replaced with first and second metal gate structures that are electrically isolated from each other by the CT pillar.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: January 8, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Josef Watts
  • Patent number: 10128333
    Abstract: A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the substrate in the source and drain regions while those in the channel region remain. The gaps created by the separation in the source and drain are filled with electrically insulating material. Prior to filling the gaps, defects created by the separation may be reduced.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: November 13, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hoong Shing Wong, Min-hwa Chi, Tae-Hoon Kim
  • Patent number: 10032911
    Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Robert S. Chau, Sansaptak Dasgupta, Marko Radosavljevic, Benjamin Chu-Kung, Seung Hoon Sung, Sanaz Gardner, Ravi Pillarisetty
  • Patent number: 9985112
    Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 9929182
    Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a bottom substrate having a first region and a second region, and forming a trench in the first region by patterning the bottom substrate. The method also includes forming an insulation layer in the trench in the first region, wherein the insulation layer exposes part of side surface of the trench, and forming a top substrate on the exposed side surface of the trench and the insulation layer. Further, the method includes forming a first fin portion in the first region, and forming a gate structure crossing the first fin portion, wherein the gate structure covers part of side and top surfaces of the first fin portion.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: March 27, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Ji Quan Liu, Chun Lei Gong
  • Patent number: 9812604
    Abstract: A photosensing device with a photovoltage sensing mechanism, a graphene layer and a semiconductor layer. The graphene layer is sandwiched between the semiconductor layer and a substrate. The photovoltage sensing mechanism senses the photovoltage created by light impinging on the graphene-semiconductor heterojunction. The strength of the photovoltage is used to indicate the level of illumination of the impinging light.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: November 7, 2017
    Assignees: Wispro Technology Consulting Corporation Limited
    Inventor: Klaus Y. J. Hsu
  • Patent number: 9812603
    Abstract: A photosensing device with a photovoltage sensing mechanism, a graphene layer and a semiconductor layer. The graphene layer is sandwiched between the semiconductor layer and a substrate. The photovoltage sensing mechanism senses the photovoltage created by light impinging on the graphene-semiconductor heterojunction. The strength of the photovoltage is used to indicate the level of illumination of the impinging light.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: November 7, 2017
    Assignees: Wispro Technology Consulting Corporation Limited
    Inventor: Klaus Y. J. Hsu
  • Patent number: 9728535
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Patent number: 9704994
    Abstract: A fin field effect transistor (finFET) and a method of fabricating the finFET. The method includes forming one or more fins above a substrate in a channel region, depositing a first insulating material conformally on the one or more fins and the substrate, and depositing a second insulating material over the first insulating material in non-channel regions adjacent to the channel region. A selective etch of the first insulating material in the channel region is performed to form a trench. The trench is filled with the second insulating material. The second insulating material in the channel region is adjacent to the first insulating material in the non-channel regions.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu, Chen Zhang
  • Patent number: 9698175
    Abstract: An LCD panel, an array substrate and a manufacturing method for TFT are disclosed. The method includes: providing a substrate; forming a first metal layer on the substrate, wherein the first metal layer includes an aluminum metal layer, an aluminum oxide layer and a molybdenum metal layer stacked sequentially; patterning the first metal layer to form a gate electrode of a TFT; sequentially forming a gate insulation layer, a semiconductor layer and an ohmic contact layer on the gate electrode; forming a second metal layer on the ohmic contact layer; and patterning the second metal layer to form a source electrode and a drain electrode of the TFT. The present invention can inhibit hillock generated by the aluminum metal layer in a high temperature environment, avoid the short circuit generated among the gate, the source and the drain electrodes of the TFT to ensure the display quality of an image.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: July 4, 2017
    Assignee: Shenzhen China Star Optoelectionics Technology Co., Ltd
    Inventor: Dongzi Gao
  • Patent number: 9691627
    Abstract: A method of fabricating a semiconductor device includes forming a linear preliminary mask pattern in a first direction on a substrate. The preliminary mask pattern is patterned to provide a plurality of mask patterns that are aligned end-to-end with one another on the substrate and are separated by an exposed portion of the substrate between respective facing ends of the plurality of mask patterns. An auxiliary layer is formed to cover at least sidewalls of the facing ends to reduce a size of the exposed portion to provide a reduced exposed portion of the substrate and the reduced exposed portion of the substrate is etched to form a trench defining active patterns in the substrate aligned end-to-end with one another.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: June 27, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-Sic Yoon, Jiung Pak, Kiseok Lee, Chan Ho Park, Hyeonok Jung
  • Patent number: 9691850
    Abstract: A vertical transistor has a first air-gap spacer between a gate and a bottom source/drain region, and a second air-gap spacer between the gate and the contact to the bottom source/drain region. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: June 27, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Tak H. Ning
  • Patent number: 9679954
    Abstract: The EL substrate includes semiconductor layers of TFTs, a pixel electrode, and an upper part electrode of a Cs section which are provided on a gate insulating film. The semiconductor layers are covered with a protective film which has openings via which the pixel electrode and the upper part electrode are exposed. The semiconductor layers are an oxide semiconductor layer, and the pixel electrode and the upper part electrode are reduction electrodes of the oxide semiconductor layer.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: June 13, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yutaka Takamaru
  • Patent number: 9633907
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 9607995
    Abstract: A method for forming a semiconductor having a plurality of FinFETs. The method includes providing a semiconductor substrate having a surface; and forming a plurality of first fins and a plurality of second fins on the surface of the semiconductor substrate. Further, the method also includes forming a mask layer on top surfaces of the plurality of first fins and the plurality of second fins; and forming an insulation material layer covering side surfaces of the first fins, the second fins and the mask layer. Further, the method includes removing a portion of the mask layer on the first fins; and forming a continuous first gate structure covering side and top surfaces of a plurality of first fins and a discontinuous second gate structure covering only the side surfaces of the second fins and the side surfaces of the mask layer.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: March 28, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Jianhua Ju, Shaofeng Yu
  • Patent number: 9601638
    Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an implant mask (81) to implant ions (91) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode (111) from contacting the peripheral edge and sidewalls of the mesa structures.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: March 21, 2017
    Assignee: NXP USA, INC.
    Inventors: Jenn Hwa Huang, Weixiao Huang
  • Patent number: 9595611
    Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.
    Type: Grant
    Filed: April 26, 2014
    Date of Patent: March 14, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Hoon Kim, Bon-Young Koo, Nam-Kyu Kim, Woo-Bin Song, Byeong-Chan Lee, Su-Jin Jung
  • Patent number: 9472446
    Abstract: One method disclosed includes, among other things, forming an overall fin structure having a stepped cross-sectional profile, the fin structure having an upper part and a lower part positioned under the upper part, wherein the upper part has a first width and the lower part has a second width that is less than the first width, forming a layer of insulating material in trenches adjacent the overall fin structure such that the upper part of the overall fin structure and a portion of the lower part of the overall fin structure are exposed above an upper surface of the layer of insulating material, and forming a gate structure around the exposed upper part of the overall fin structure and the exposed portion of the lower part of the overall fin structure.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: October 18, 2016
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 9425317
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending above the substrate. The FinFET device structure includes an isolation structure, and the fin structure is embedded in the isolation structure. The FinFET device structure also includes a gate structure formed on a middle portion of the fin structure. The gate structure has a top portion and bottom portion, and the bottom portion is wider than the top portion. The FinFET device structure further includes a source/drain (S/D) structure formed adjacent to the gate structure.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: August 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Tsung-Yao Wen, Yao-De Chiou, Sheng-Chen Wang, Sai-Hooi Yeong
  • Patent number: 9406545
    Abstract: A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9390925
    Abstract: Constructing an SiGe fin by: (i) providing an intermediate sub-assembly including a silicon-containing base layer and a silicon-containing first fin structure extending in an upwards direction from the base layer; (ii) refining the sub-assembly by covering at least a portion of the top surface of the base layer and at least a portion of the first and second lateral surfaces of the first fin structure with a pre-thermal-oxidation layer that includes Silicon-Germanium (SiGe); and (iii) further refining the sub-assembly by thermally oxidizing the pre-thermal oxidation layer to migrate Ge content from the pre-thermal-oxidation layer into at least a portion of the base layer and at least a portion of first fin structure.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: July 12, 2016
    Assignee: Globalfoundries, Inc.
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 9373694
    Abstract: A device and method for integrated circuits with surrounding gate structures are disclosed. The device includes a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure is doped with a first conductivity type and includes a source region at one distal end and a drain region at the opposite distal end. The device further includes a gate structure overlying a channel region disposed between the source and drain regions of the fin structure. The fin structure has a rectangular cross-sectional bottom portion and an arched cross-sectional top portion. The arched cross-sectional top portion is semi-circular shaped and has a radius that is equal to or smaller than the height of the rectangular cross-sectional bottom portion. The source, drain, and the channel regions each are doped with dopants of the same polarity and the same concentration.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: June 21, 2016
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: De Yuan Xiao, Guo Qing Chen, Roger Lee, Chin Fu Yen, Su Xing, Xiao Lu Huang, Yong Sheng Yang
  • Patent number: 9362307
    Abstract: An object of the present invention is to provide a method for manufacturing a thin film transistor which enables heat treatment aimed at improving characteristics of a gate insulating film such as lowering of an interface level or reduction in a fixed charge without causing a problem of misalignment in patterning due to expansion or shrinkage of glass. A method for manufacturing a thin film transistor of the present invention comprises the steps of heat-treating in a state where at least a gate insulating film is formed over a semiconductor film on which element isolation is not performed, simultaneously isolating the gate insulating film and the semiconductor film into an element structure, forming an insulating film covering a side face of an exposed semiconductor film, thereby preventing a short-circuit between the semiconductor film and a gate electrode.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: June 7, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuji Yamaguchi, Kengo Akimoto, Hiroki Kayoiji, Toru Takayama
  • Patent number: 9343582
    Abstract: An embodiment of the invention provides a manufacturing method of a thin film transistor substrate including: sequentially forming a gate electrode, a gate insulating layer covering the gate electrode, an active material layer, and a photo-sensitive material layer on a first substrate; performing a photolithography process by using a half tone mask to form a photo-sensitive protective layer which is above the gate electrode and has a first recess and a second recess; etching the active material layer by using the photo-sensitive protective layer as a mask to form an active layer; removing a portion of the photo-sensitive protective layer at bottoms of the first recess and the second recess to expose a first portion and a second portion of the active layer respectively; forming a first electrode connecting to the first portion; and forming a second electrode connecting to the second portion.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: May 17, 2016
    Assignees: INNOCOM TECHNOLOGY (SHENZHEN) CO., LTD., INNOLUX CORPORATION
    Inventor: Kuan-Feng Lee
  • Patent number: 9331165
    Abstract: The present invention discloses a thin-film transistor (TFT), a manufacturing method thereof, an array substrate and a display device. The present invention is used for improving the electrical properties of the TFT and the image quality of the display device. The TFT provided by the present invention comprises: a gate electrode, a source electrode, a drain electrode, a semiconductor layer, a gate electrode insulating layer and a first metal barrier layer, which are disposed on a substrate; the gate electrode insulating layer is disposed between the gate electrode and the semiconductor layer; and the first metal barrier layer is disposed between the source/drain electrodes and the gate electrode insulating layer, and the first metal barrier layer is arranged on the same layer as the semiconductor layer and configured to prevent interdiffusion between the material for forming the source/drain electrodes and the material for forming the gate electrode.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: May 3, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiang Liu, Gang Wang
  • Patent number: 9324869
    Abstract: The present disclosure provides, in various aspects, a method of forming a semiconductor device and accordingly formed semiconductor devices. In accordance with some illustrative embodiments herein, a fin is provided in an upper surface of a substrate, the fin having a height dimension and an initial width dimension. After forming a mask on the fin, wherein the mask only partially covers an upper surface of the fin, the fin is exposed to an etch process for removing material in accordance with the mask such that a channel portion connecting end portions of the fin is formed. Herein, a width dimension of the channel portion is smaller than a width dimension of the end portions. In accordance with some illustrative embodiments of the present disclosure, the channel portion may substantially have a cross-section of one of a triangular shape and a double-sigma shape.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: April 26, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ran Yan, Alban Zaka, Jan Hoentschel
  • Patent number: 9263585
    Abstract: Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Daniel T. Pham, Robert J. Miller, Kungsuk Maitra
  • Patent number: 9263554
    Abstract: Transistors and methods for fabricating the same include forming one or more semiconductor fins on a substrate; covering source and drain regions of the one or more semiconductor fins with a protective layer; annealing uncovered channel portions of the one or more semiconductor fins in a gaseous environment to reduce fin width and round corners of the one or more semiconductor fins; and forming a dielectric layer and gate over the thinned fins.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: February 16, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Shogo Mochizuki, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 9252157
    Abstract: A method includes providing a structure having a substrate, a first electrically insulating layer overlying the substrate, a first semiconductor layer comprised of a first semiconductor material overlying the first electrically insulating layer, a second electrically insulating layer overlying the first semiconductor layer in a first portion of the structure and a second semiconductor layer comprised of a second, different semiconductor material overlying the second electrically insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure to form a regrown semiconductor layer; forming fins; forming gate structures orthogonal to the fins and removing at least a portion of the first semiconductor layer in the first portion of the structure to form a void and filling the void with insulating material. Structures formed by the method are also disclosed.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: February 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Lukas Czornomaz, Jean Fompeyrine, Effendi Leobandung
  • Patent number: 9219116
    Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFET, as compared to a FinFET including fins that do not include a dielectric disposed within a furrow.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Zhiqiang Wu, Carlos H. Diaz
  • Patent number: 9214565
    Abstract: Provided is a miniaturized transistor having high electrical characteristics. The transistor includes a source electrode layer in contact with one side surface of the oxide semiconductor layer in the channel-length direction and a drain electrode layer in contact with the other side surface thereof. The transistor further includes a gate electrode layer in a region overlapping with a channel formation region with a gate insulating layer provided therebetween and a conductive layer having a function as part of the gate electrode layer in a region overlapping with the source electrode layer or the drain electrode layer with the gate insulating layer provided therebetween and in contact with a side surface of the gate electrode layer. With such a structure, an Lov region is formed with a scaled-down channel length maintained.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: December 15, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata
  • Patent number: 9196612
    Abstract: A semiconductor device includes a plurality of first semiconductor fins formed on a semiconductor substrate to define first fin trenches. At least one second semiconductor fin is formed on the semiconductor substrate to define second fin trenches. A first work function metal layer is formed in the first and second fin trenches. The first work function metal layer formed in the second trenches has a first cavity formed therein such that the at least one second semiconductor fin realizes a different concentration of the first work function metal layer with respect to the plurality of first semiconductor fins.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: November 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 9190419
    Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: November 17, 2015
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 9177888
    Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: November 3, 2015
    Assignee: IXYS Corporation
    Inventors: Thomas Spann, Holger Ostmann, Kang Rim Choi
  • Patent number: 9159807
    Abstract: The reliability of a semiconductor device including a MOSFET formed over an SOI substrate is improved. A manufacturing method of the semiconductor device is simplified. A semiconductor device with n-channel MOSFETsQn formed over an SOI substrate SB includes an n+-type semiconductor region formed as a diffusion layer over an upper surface of a support substrate under a BOX film, and a contact plug CT2 electrically coupled to the n+-type semiconductor region and penetrating an element isolation region, which can control the potential of the support substrate. At a plane of the SOI substrate SB, the n-channel MOSFETsQn each extend in a first direction, and are arranged between the contact plugs CT2 formed adjacent to each other in the first direction.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: October 13, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Komaki Inoue, Yutaka Hoshino
  • Patent number: 9147741
    Abstract: A thin film transistor display panel according to an exemplary embodiment of the present invention includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed on the first insulating layer, a second insulating layer formed on the semiconductor layer, and a gate electrode formed on the second insulating layer, in which the first insulating layer includes a light blocking material, and a thickness of the first insulating layer is greater than or equal to a thickness of the second insulating layer.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: September 29, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyun Jae Na, Yoon Ho Khang, Sang Ho Park, Dong Hwan Shim, Se Hwan Yu, Yong Su Lee, Myoung Geun Cha
  • Patent number: 9147680
    Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a beveled surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 29, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Kristina Trevino, Yuan-Hung Lin, Gabriel Padron Wells, Chang Ho Maeng, Taejoon Han, Hoong Shing Wong
  • Patent number: 9142653
    Abstract: The present invention provides a method for manufacturing a thin-film transistor (TFT) array substrate. The TFT array substrate is of a top-gate structure. The method for manufacturing a thin-film transistor array substrate applies three times of masking operation to manufacture the TFT array substrate, wherein IGZO is used to manufacture a TFT of the TFT array substrate so as to greatly increase the charging speed of the TFT with respect to a pixel electrode, improve the response speed of the pixel, and achieve a relatively high refresh rate. Further, the fast response also help improving row scanning rate of pixels to make it possible to achieve ultra-high definition of a TFT LCD. Further, the manufacturing method applies only three times of masking operation so as to significantly reduce the manufacturing steps, shortening the manufacturing time, effectively lowering down the manufacturing cost, and increasing throughput.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: September 22, 2015
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Jun Wang
  • Patent number: 9130045
    Abstract: The present invention relates to a thin film transistor and a method of manufacturing the same. More particularly, the present invention relates to a thin film transistor that includes a zinc oxide material including Si as a channel material of a semiconductor layer, and a method of manufacturing the same.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: September 8, 2015
    Assignee: LG Chem, Ltd.
    Inventor: Jung-Hyoung Lee
  • Patent number: 9117877
    Abstract: Disclosed herein are various methods of forming isolation structures on FinFETs and other semiconductor devices, and the resulting devices that have such isolation structures. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define a fin for a FinFET device, forming a layer of insulating material in the trenches, wherein the layer of insulating material covers a lower portion of the fin but not an upper portion of the fin, forming a protective material on the upper portion of the fin, and performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: August 25, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiuyu Cai, Ruilong Xie, Jin Cho, John Iacoponi
  • Patent number: 9105661
    Abstract: The present disclosure provides for methods of fabricating a semiconductor device and such a device. A method includes providing a substrate including at least two isolation features, forming a fin substrate above the substrate and between the at least two isolation features, forming a silicon liner over the fin substrate, and oxidizing the silicon liner to form a silicon oxide liner over the fin substrate.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: August 11, 2015
    Assignee: Taiwan Semconductor Manufacturing Company, Ltd.
    Inventors: Gin-Chen Huang, Neng-Kuo Chen, Hsingjen Wann
  • Patent number: 9093534
    Abstract: An array of stacks containing a semiconductor fins and an oxygen-impermeable cap is formed on a semiconductor substrate with a substantially uniform areal density. Oxygen-impermeable spacers are formed around each stack, and the semiconductor substrate is etched to vertically extend trenches. Semiconductor sidewalls are physically exposed from underneath the oxygen-impermeable spacers. The oxygen-impermeable spacers are removed in regions in which semiconductor fins are not needed. A dielectric oxide material is deposited to fill the trenches. Oxidation is performed to convert a top portion of the semiconductor substrate and semiconductor fins not protected by oxygen-impermeable spacers into dielectric material portions. Upon removal of the oxygen-impermeable caps and remaining oxygen-impermeable spacers, an array including semiconductor fins and dielectric fins is provided.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Bruce B. Doris, Ali Khakifirooz, Edward J. Nowak, Kern Rim
  • Patent number: 9093517
    Abstract: A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region. A body contact is disposed in the p-type isolation ring.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: July 28, 2015
    Assignee: Microsemi SoC Corporation
    Inventors: Ben A. Schmid, Fethi Dhaoui, John McCollum
  • Patent number: 9087869
    Abstract: A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9064963
    Abstract: A semiconductor structure includes a substrate, an undoped GaP insulating layer formed over the substrate, and a semiconductor layer formed over the GaP layer.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: June 23, 2015
    Assignee: Infineon Technologies AG
    Inventor: Muhammad Nawaz
  • Patent number: 9059043
    Abstract: A gate cavity is formed over a semiconductor fin by forming a disposable gate structure and a planarization dielectric layer over the semiconductor fin, and by removing the disposable gate structure. A doped silicate glass spacer including an electrical dopant is formed on sidewalls of the gate cavity by deposition and an anisotropic etch of a conformal doped silicate glass layer. A gate spacer including a diffusion barrier material is formed on inner sidewalls of the doped silicate glass spacer. A replacement gate structure is formed within the gate cavity, and source/drain regions are formed in portions of the semiconductor fin by outdiffusion of the electrical dopant during an anneal. The source/drain regions are formed within the semiconductor fin, and are self-aligned to the replacement gate electrode.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Tenko Yamashita