Abstract: A GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure are provided wherein, stacked upon a GaAs single-crystal substrate are at least a buffer layer, a GaZIn1−ZAs (0<Z≦1) channel layer, and a GaYIn1−YP (0<Y≦1) electron-supply layer joined to the channel layer, wherein the GaInP epitaxial stacking structure includes a region within the electron-supply layer wherein the gallium composition ratio (Y) decreases from the side of the junction interface with the channel layer toward the opposite side.

Abstract: There is provided a compound semiconductor device having a MESFET whic comprises a channel layer made of InxGa1-xPySb1-y (where 0.3<x<0.7, 0.9<y<0.999999) formed by doping an impurity onto a substrate, a barrier layer formed on the channel layer, a gate layer formed on the barrier layer, and a source electrode and a drain electrode formed separately on both sides of the gate electrode on the barrier layer. Accordingly, the mutual conductance of the compound semiconductor device having the MESFET can be increased rather than the prior art.

Abstract: Two or more coupled sub-wells are inserted in the quantum well region of a MODFET to move the electron/hole gas away from the interface between the spacer layer and the well region. The channel can be constructed with a wire cross-section to confine the electron/hole gas in two dimensions, thereby reducing the scattering and improving the device performance. Structures with supply layer contacts, along with their application are described. Laterally coupled quantum wire MODFETs are also disclosed. The insertion of a coupled-well transport channel is applicable for Si MOSFETs in improving the high frequency performance.

Abstract: A high-sensitivity Pd/InP hydrogen sensor was made by a) forming an n-type or p-type semiconductor film on a semiconductor substrate; b) forming a patterned first metal electrode on said semiconductor film, wherein said first metal electrode forms an Ohmic contact with said semiconductor film; and c) forming a second metal electrode on said semiconductor film, said second metal electrode being isolated from said first metal electrode, wherein said second metal electrode forms a Schottky contact with said semiconductor film, wherein a thickness of said second metal electrode and a material of which said second metal electrode is made enable a Schottky barrier height of said Schottky contact to decrease when hydrogen contacts said second metal electrode. The second metal electrode can be physical vapor deposited or electroless plated.

Abstract: The monolithically integrated Enhancement/Depletion mode HEMT (high-electron-mobility transistor) of the present invention comprises: a buffer layer, a channel layer, a spacer layer, a first barrier layer, a second barrier layer, a third barrier layer, and an ohmic layer consecutively formed on a semiconductor substrate from bottom to top; the first exposed region (a gate region for a Depletion-mode HEMT) formed by selective etching of the ohmic layer to expose the third barrier layer; a second exposed region (a gate region for an Enhancement-mode HEMT) formed by selective etchings of the ohmic layer and the third barrier layer to expose the second barrier layer; and gate electrodes formed on the first and second exposed gate regions. According to the present invention, a monolithically integrated Enhancement/Depletion mode HEMT having a uniform threshold voltage can easily be fabricated.

Abstract: A method of fabricating a thin-film transistor on an insulation substrate. A first conductive layer, a gate dielectric layer, a silicon layer and a doped silicon layer are formed on the insulation substrate. These four layers are patterned to form a gate and a gate line. A second conductive layer is formed over the insulation substrate. The second conductive layer and the doped silicon layer are patterned to form a source/drain region, a source/drain conductive layer and a source/drain line on both sides of the gate line. A protection layer is formed over the insulation layer, followed by a patterning step to form openings on the source/drain conductive layer and the source/drain line. A transparent conductive layer is formed on the protection layer and in the openings. After being patterned, a pixel electrode is formed, and a portion of the transparent conductive layer remains to electrically connect the source/drain line and the source/drain conductive layer.

Abstract: A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.

Abstract: The illumination energy of an excimer laser is measured and adjusted to always effect illumination at constant energy. A laser beam output from an optics is reflected by a mirror, and applied to a sample. A beam profiler is disposed behind the mirror to measure the energy of an illumination laser beam. An energy attenuating device disposed between another mirror and the optics is operated based on the measurement value so that the energy of the laser beam applied to the sample is kept constant.

Abstract: The invention relates to a method for the production of a monocrystalline layer on a substrate with a non-adapted lattice. To this end, a monocrystalline substrate with a buried amply defective layer and a monocrystalline layer produce thereon are used. The buried amply defective layer can be produced by hydrogen implantation.

Abstract: A method of selective molecular beam epitaxy for fabricating monolithically integrated circuit devices on a common substrate including combinations of PIN diode devices, HBT devices, HEMT devices and MESFET devices. The method includes depositing a profile layer of one of the devices on an appropriate substrate and then depositing a first dielectric layer over the profile layer. The profile layer and the dielectric layer are then etched to define a first device profile. A second profile layer for defining a second device is then deposited over the exposed substrate. The second profile is then selectively etched to define a second device profile. This process can be extended to more than two different device types monolithically integrated on a common substrate as long as the first developed devices are robust enough to handle the temperature cycling involved with developing the subsequent devices.

Abstract: A high frequency semiconductor device includes a ground plate, an insulating layer, a power-supply conductor, an insulating interlayer, and a strip line as a line conductor. The power-supply conductor is disposed above the ground plate, with the insulating layer provided therebetween. The ground plate and the power-supply conductor have a capacitance formed therebetween. Thus, the line conductor regards the power-supply conductor as having a potential identical to that of the ground plate. This makes it possible to lay out the line conductor without considering the arrangement of the power-supply conductor. In other words, by two-dimensionally overlapping a microstrip line and a power-supply conductor in an MMIC, the degree of freedom in the device layout can be increased.

Abstract: The invention relates to a semiconductor component which is capable of blocking such as an (IGBT), a thyristor, a GTO or diodes, especially schottky diodes. An insulator profile section (10a, 10b, 10c, 10d, 11) provided in the border area of an anode metallic coating (1, 31) is fixed (directly in the edge area) on the substrate (9) of the component. The insulator profile has a curved area (KB) and a base area (SB), said curved area having a surface (OF) which begins flat and curves outward and upward in a steadily increasing manner. A metallic coating (MET1; 30a, 30b, 30c, 30d, 31b) is deposited on the surface (OF). Said coating directly follows the surface curvature and laterally extends the inner anode metallic coating. The upper end of the curved metallic coating (MET1; 30a, 30b . . . ) is distanced and insulated from one of these surrounding outer metallic coatings (MET2; 3) by the surrounding base area (SB) of the insulator profile (10a, . . .

Abstract: A MESFET has a conduction channel provided with a first doping profile in a first portion which extends between the source and the gate, and a second doping profile in a second portion which extends between the gate and the drain. A background p-type region is provided beneath the first portion, but not necessarily behind the second portion.

Abstract: A totally self-aligned transistor with a tungsten gate. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. A mid-gap electrode is also self-aligned to the transistor. The electrode is preferably formed from tungsten metal.

Abstract: Disclosed is a method of reducing the conductivity/charge of a layer of group III-V semiconductor doped with Sn. The method includes the steps of: forming an region of SiO2 on the semiconductor layer; annealing at least the semiconductor layer and the region of SiO2 at a temperature sufficiently high to cause atoms of the Sn dopant to leach from the semiconductor layer into the region of SiO2; and removing the region of SiO2 after the annealing step is performed. The method can be used, for example, during the manufacture of HEMT, PHEMT, MESFET and HBT devices.

Abstract: A switching circuit device has a first FET and a second FET, and operates with single control terminal. The device also has a common input terminal connected to the drain or source electrode of the two FETs, a first output terminal and a second output terminal connected to the source or the drain electrode of the respective FET, a bias element applying an bias to the first output terminal, a first connection connecting the control terminal to the second FET, a second connection connecting the gate of the second FET to the ground, and a direct current isolation element placed between the two FETs. The device is housed in a MCP6 package with six pins.

Abstract: An insulating-gate semiconductor device has a first nitride semiconductor layer formed over a substrate and an insulating oxidation layer obtained by oxidizing a second nitride semiconductor layer formed on the first nitride semiconductor layer. A gate electrode is formed on the insulating oxidation layer.

Abstract: The present invention relates to the fabrication of a boron carbide/boron semiconductor devices. The results suggest that with respect to the approximately 2 eV band gap pure boron material, 0.9 eV band gap boron carbide (B5C) acts as a p-type material. Both boron and boron carbide (B5C) thin films were fabricated from single source borane cage molecules using plasma enhanced chemical vapor deposition (PECVD). Epitaxial growth does not appear to be a requirement. We have doped boron carbide grown by plasma enhanced chemical vapor deposition. The source gas close-1,2-dicarbadecaborane (orthocarborane) was used to grow the boron carbide while nickelocene (Ni(C5H5)2) was used to introduce nickel into the growing film. The doping of nickel transformed a B5C material p-type relative to lightly doped n-type silicon to an n-type material. Both p-n heterojunction diodes and n-p heterojunction diodes with n- and p-type Si [1,1,1] respectively.

Abstract: An integrated circuit is composed of a substrate, a first conductor formed on the substrate, an insulating film formed on the first conductor and the substrate, a second conductor formed on the insulating film, a first interconnection formed in the insulating film and a second interconnection formed on the insulating film. The first conductor and the second conductor constitute a pair of transmission lines. The first interconnection and the second interconnection constitute a circuit. The pair of transmission lines and the circuit are separated such that the circuit does not substantially interfere electrically with the pair of transmission lines.

Abstract: An integrated semiconductor circuit device comprising a diode bridge circuit formed of a Schottky barrier diode and a periphery circuit formed of a MOS transistor which are formed on a single silicon substrate, wherein a Schottky barrier, which is a component of the Schottky barrier diode, is made of a silicide layer.

Abstract: A strained Si CMOS structure is formed by steps which include forming a relaxed SiGe layer on a surface of a substrate; forming isolation regions and well implant regions in said relaxed SiGe layer; and forming a strained Si layer on said relaxed SiGe layer. These processing steps may be used in conjunction with conventional gate processing steps in forming a strained MOSFET structure.

Abstract: A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate.

Abstract: A semiconductor device operable with a single positive power source, enabling an increase in efficiency, and improved in high-frequency characteristics by lowering the resistivity of a gate contact, including a carrier run layer formed on a substrate for running of carriers; a carrier supply layer formed on the carrier run layer, having a larger bandgap than the carrier run layer, and containing a first conductivity type impurity; a barrier layer formed on the carrier supply layer and having a smaller bandgap than the carrier supply layer; a source electrode and a drain electrode formed on the barrier layer at a predetermined distance from each other; a gate electrode formed on the barrier layer between the source electrode and the drain electrode away from the source electrode and the drain electrode; and a first low resistivity region formed at least below the gate electrode in the barrier layer and containing a second conductivity type impurity opposite in conductivity to the first conductivity type, and a

Abstract: A field effect transistor has a preselected build up resistance with respect to an I-V characteristic of the transistor. In this event, a first GaAs layer is formed on a GaAs substrate. Further, an AlGaAs layer is formed on the first GaAs layer and has a predetermined impurity concentration and a preselected Al composition ratio. Moreover, a gate electrode is placed on the AlGaAs layer to form a schottky contact with the AlGaAs layer. In addition, a second GaAs layers are arranged on both sides of the gate electrode via a recess and are formed on said AlGaAs layer. Finally, source and drain electrodes are formed on the second GaAs layers. With such a structure, the Al composition ratio is determined within a preselected range defined by a relationship between the impurity concentration and the build up resistance.

Abstract: There is disclosed a field effect transistor having a two-stage recess structure formed upon an InP substrate and showing stable device characteristics and a low contact resistance. The FET is manufactured as follows. Upon an InP substrate 101, a channel layer 103, electron supply layers 104 and 105, an undoped InAlAs Schottky layer 106, an n-type InAlAs first cap layer 107 and an n-type InGaAs second cap layer 108 are formed in succession, following which a second recess opening 111 is formed by etching from the surface of the second cap layer to just the surface of said Schottky layer or further to a level to remove a part of the Schottky layer. A first recess opening 110 is formed by side-etching the second cap layer using an etchant of which etching selectively of InGaAs over InAlAs is 30 or more.

Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least {fraction (1/100)} of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.

Abstract: A method of fabricating a semiconductor device, capable of forming a pattern more finely and more variously without depending on the performance of an exposing device. Aluminum is vapor deposited on a spacer film from an oblique direction to form a metal film etching guard. Specifically, Al is vapor deposited from a direction inclined from the direction of the normal line of the surface of the spacer film by 85° (angle of vapor deposition). For example, when the depth of a recess is 0.10 &mgr;m and the opening width is 0.4 &mgr;m, Al is not vapor deposited on the bottom surface of the recess. After performing anisotropic etching on the spacer film by using the metal film etching guard as a mask, the metal film etching guard is removed. A gate electrode is formed in the recess.

Abstract: A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of the gate conductor. Extension regions are provided in the substrate which extend under the spacer and the gate conductor. Source and drain diffusion regions are implanted into the substrate adjacent to the extension regions. The disposable part of the spacer is then removed to expose a portion of the extension region. A metal layer is formed at least in the extension regions, resulting in the Schottky contact.

Abstract: A gate oxide film and a first layer of a multilayered gate electrode are stacked on a substrate and by a gate prefabrication technique, an oxide layer of an element isolation region is formed in a self-alignment manner using the first layer of the gate electrode as a mask, impurities for a transistor channel control are doped by ion implantation via the first layer of the gate electrode and the gate oxide film, and the doped impurities are activated by a heating step, whereby an impurity profile at the transistor channel portion is precisely formed.

Abstract: The present invention relates to a field-effect transistor which is improved such that the linearity of mutual conductance gm is flattened over a wider range of gate bias. This field-effect transistor is a MESFET comprising a channel layer and a cap layer in Schottky-contact with a gate electrode. In particular, between the channel layer and the cap layer, one or more auxiliary layers having a doping concentration lower than that of the channel layer and higher than that of the cap layer are provided. The doping concentration of one or more auxiliary layers is set such that the doping profile of a laminated structure constituted by the channel layer, one or more auxiliary layers, and cap layer exponentially lowers from the channel layer toward the cap layer. According to this configuration, the depletion layer can effectively be controlled over a wider range of gate bias, the long gate effect and the like are suppressed, and the linearity of mutual conductance gm is improved.

Abstract: A semiconductor device includes a gate structure formed on a substrate in which an LDD structure is formed, wherein gate structure includes a Schottky electrode making a Schottky contact with a channel region in the substrate, a low-resistance layer provided above the Schottky electrode, and a stress-relaxation layer interposed between the Schottky electrode and the stress-relaxation layer. The low-resistance layer and said stress-relaxation layer form an overhang structure with respect to the Schottky electrode.

Abstract: An active element has first and second regions and a control electrode. Carriers move between the first and second regions in a first direction. A motion of carriers is controlled by an electric signal applied to the control electrode. The first and second regions and control electrode extend in a second direction crossing the first direction from an input terminal to an output terminal. A conductive region is electrically connected to the first region from the input terminal to the output terminal. A trigger line extending in the second direction propagates an electric signal from the input terminal to the output terminal. The electric signal propagating the trigger line is applied to the control electrode at a corresponding position in the second direction. An output line extending in the second direction propagates an electric signal from the input terminal to the output terminal.

Abstract: A high-sensitivity Pd/InP hydrogen sensor was made by a) forming an n-type or p-type semiconductor film on a semiconductor substrate; b) forming a patterned first metal electrode on said semiconductor film, wherein said first metal electrode forms an Ohmic contact with said semiconductor film; and c) forming a second metal electrode on said semiconductor film, said second metal electrode being isolated from said first metal electrode, wherein said second metal electrode forms a Schottky contact with said semiconductor film, wherein a thickness of said second metal electrode and a material of which said second metal electrode is made enable a Schottky barrier height of said Schottky contact to decrease when hydrogen contacts said second metal electrode. The second metal electrode can be physical vapor deposited or electroless plated.

Abstract: There is provided a hetero-junction field effect transistor including (a) a first semiconductor layer composed of InP, (b) a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer having a smaller electron affinity than that of the first semiconductor layer, (c) a third semiconductor layer formed on the second semiconductor layer, the third semiconductor layer having a greater electron affinity than that of the second semiconductor layer, and being formed at a surface thereof with an opening, the third semiconductor layer being composed of InP, (d) source and drain electrodes formed on the third semiconductor layer, and (e) a gate electrode formed on the second semiconductor layer in the opening of the third semiconductor layer. In accordance with the hetero-junction field effect transistor, it is possible to enhance noise characteristic and high power characteristic.

Abstract: The present invention provides a compact structure for the above-discussed SRAM cell as well as a method for fabricating the structure. The structure is preferably implemented in silicon. The standby power consumption of the cell is only approximately 0.5 nanowatts. The cell structure allows an SRAM cell to be fabricated in only a 16 feature-square area using planar technology. The structure of the cell according to one embodiment of the present invention is comprised of two bus bars of minimum feature size width, each of which has a tunnel diode implanted therein, and an elongated center land area (also of minimum feature size width) between the two bus bars. The transistor is constructed along the elongated center land area. In a preferred embodiment, transistors of neighboring cells share a common drain area and bit line contact. A corresponding method for fabricating the structure is also provided.

Abstract: The method for fabricating a semiconductor device comprises the steps of forming on a semiconductor substrate a gate electrode, and an eave-shaped film of an inorganic material formed on the upper surface of the gate electrode and having a eave-shaped portion projected beyond the edge of the gate electrode; and ion-implanting a dopant with the gate electrode as a mask and with the eave-shaped portion of the eave-shaped film as a through film to form a first diffusion layer in the semiconductor substrate immediately below the eave-shaped portion and a second diffusion layer which is connected to the first diffusion layer, and is deeper and has a higher dopant concentration than the first diffusion layer, in the semiconductor substrate in a region where the eave-shaped film is not formed.

Abstract: A Schottky diode, and a method of making the same, which is fabricated on InP material and employs a Schottky layer including InxAl1−xAS with x>0.6, or else including a chirped graded superlattice in which successive periods of the superlattice contain progressively less GaInAs and progressively more AlInAs, the increase in AlInAs being terminated before the proportion of AlInAs within the last period (adjacent the anode metal) exceeds 80%.

Abstract: The invention is a Pseudomorphic transistor structure having a semiconductor layer having a 2DEG layer therein, a Schottky layer, a transition layer and an ohmic contact layer on the transition layer, wherein a double recess structure is disposed through the ohmic layer onto the transition layer in which one or two layers of InyGa1−yP are used as etch-stop layers to define the depth of the recess.

Abstract: A high electron mobility transistor includes a channel layer for developing therein an electron gas layer having a substantially uniform electron gas density, and upper and lower high-resistance wide-band gap layers disposed respective over and beneath the channel layer, each of the upper and lower high-resistance wide-band gap layers having a silicon-doped planar layer disposed therein. A contact layer is disposed on the upper wide-band gap layer for contact with source and drain electrodes, the contact layer having a recess defined therein which divides the contact tact layer. A gate electrode of substantially T-shaped cross section is disposed in the recess, and a passivation film is disposed on an inner wall surface of the recess and a lower leg portion of the gate electrode, exposing an upper head portion of the gate electrode.

Abstract: The invention relates to a method of manufacturing an integrated semiconductor device on a substrate (1), comprising steps to manufacture a stack of layers (2, 3, 4, 5) on the substrate, and steps to manufacture circuit elements by means of photolithography including the formation of a centering mask, the formation of a reference pattern through an opening in this mask, and the formation of masks for defining circuit elements centered on the reference pattern.

Abstract: A method of reducing the specific contact resistivity of a metal to semiconductor interface between a metal contact and an InP semiconductor compound. The method includes the step of increasing the amount of the group V element (P) in the semiconductor compound so that the semiconductor compound is non-stoichiometric having an excess concentration of the group V element in an amount of at least 0.1% above stoichiometric levels.

Abstract: In a semiconductor device, a first semiconductor layer is formed on a semiconductor substrate. A second semiconductor layer is formed on a part of the first semiconductor layer, and a third semiconductor layer is formed on a part of the second semiconductor layer. A first electrode is formed on the third semiconductor layer, and a second electrode is formed on the first semiconductor layer in contact with the second semiconductor layer and apart from the semiconductor layer, thus forming a diode.

Abstract: A method of forming an improved Schottky diode structure as part of an integrated circuit fabrication process that includes the introduction of a selectable concentration of dopant into the surface of an epitaxial layer so as to form a barrier-modifying surface dopant layer. The epitaxial layer forms the cathode of the Schottky diode and a metal-silicide layer on the surface of the epitaxial layer forms the diode junction. The surface dopant layer positioned between the cathode and the diode junction is designed to raise or lower the barrier height between those two regions either to reduce the threshold turn-on potential of the diode, or to reduce the reverse leakage current of the transistor. The particular dopant conductivity used to form the surface dopant layer is dependent upon the conductivity of the epitaxial layer and the type of metal used to form the metal-silicide junction.

Abstract: A transistor structure with a degradation-stop layer that prevents degradation of underlying semiconductor layers while minimizing any increase in the gate leakage current is disclosed. In one embodiment, a transistor structure includes: a substrate; a channel layer formed of a charge transport material over the substrate; a Schottky barrier layer formed of an aluminum-containing material over the channel layer; a degradation-stop layer formed of a substantially aluminum-free material over the Schottky barrier layer; and a source, a drain and a gate. The source and the drain being formed over or alloyed through the degradation-stop layer, and a lower portion of the gate extends down through an exposed portion of the degradation-stop layer and is in physical and electrical contact with the Schottky barrier layer.

Abstract: The invention is a method for fabricating a pseudomorphic HEMT transistor structure with a semiconductor layer having a 2DEG layer therein, a Schottky layer, a transition layer, and an ohmic contact layer on the transition layer. A double recess structure is disposed through the ohmic layer into the transition layer in which one or two layers of INYGa1−YAs are used as etch-stop layers to define the depth of the recess(es).

Abstract: The present invention provides a method of forming a gate recess in an insulating film on a substrate for depositing a gate electrode film being in contact with a part of the substrate and also extending at least within the gate recess.

Abstract: There is provided a field effect transistor including (a) an amorphous semiconductor layer made of amorphous silicon hydride containing impurities doped therein, (b) a semiconductor layer made of single crystal silicon having electron affinity greater than that of the amorphous silicon hydride, formed on the amorphous semiconductor layer, (c) a gate insulating film formed on the semiconductor layer, and (d) a gate electrode formed on the gate insulating film. The amorphous semiconductor layer and the semiconductor layer cooperate with each other to thereby form a potential well at a junction therebetween. The above mentioned field effect transistor utilizes a difference in electron affinity between the amorphous semiconductor layer and the semiconductor layer to thereby make it possible to operate at a higher speed because carriers are not influenced by scattering of doped ions.

Abstract: A process for oxidizing the silicon layer into a device-isolating field oxide having a radiation-hardened reduced bird's beak. An angled and rotated field implant prior to oxidation is used to increase the doping concentration in the edge region of the MOS transistors to compensate for boron leaching during oxidation. The field oxide is grown at a low temperature by high pressure oxidation which increases total dose hardness by making a silicon-rich oxide film.

Abstract: An infrared optical field effect transistor has been developed using a thin film of Lead Titanate (PbTiO3) deposited on a n/p+ Si substrate by RF magnetron sputtering. This transistor possesses excellent pyroelectric properties and can, therefore, be operated even at room temperature. The infrared optical field effect transistor has the following features associated with rapid bulk channel structure and higher mobility: 1. Can be operated at room temperature, unlike quantum type IR sensors which can only operate at very low temperature (−100° C.˜−200° C.), which results in higher costs. 2. High speed response with only 2.3 &mgr;s of rise time. This is much faster than other types of thermal infrared optical field effect transistors. 3. Easy to fabricate an integrated sensor device.

Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least {fraction (1/100)} of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.