Including Insulated Gate Field Effect Transistor Having Gate Surrounded By Dielectric (i.e., Floating Gate) Patents (Class 438/201)
  • Patent number: 10483273
    Abstract: A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: November 19, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideaki Yamakoshi, Takashi Hashimoto, Shinichiro Abe, Yuto Omizu
  • Patent number: 10460824
    Abstract: A semiconductor apparatus includes a semiconductor chip, with the semiconductor chip including a modular region and a test circuit. The modular region includes a plurality of modular areas each including a memory cell array with redundant bit lines and a peripheral memory area storing at least redundant addresses. The test circuit retrieves the redundant addresses intrinsic to the semiconductor chip. The distribution of the redundant addresses is randomly formed related to a part or an entirety of the modular area of the modular region. The distribution of the retrieved redundant addresses is irreversible, with a random number representing physical properties intrinsic to the semiconductor chip and providing copy protection. When another semiconductor chip uses the distribution of the retrieved redundant addresses the another semiconductor chip will malfunction.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: October 29, 2019
    Inventor: Hiroshi Watanabe
  • Patent number: 10217669
    Abstract: In an embodiment, a method comprises: forming a fin feature on a portion of a surface of a substrate; forming a first region of polycrystalline silicon over a first portion of the fin feature; forming a second region of polycrystalline silicon over a second portion of the fin feature; forming a third region of polycrystalline silicon over a third portion of the fin feature, wherein the third region of polycrystalline silicon is disposed between (i) the first region and (ii) the second region; forming a first spacer region between the first region and the third region; forming a second spacer region between the second region and the third region; removing the third region and at least a portion of the fin feature formed under the third region to thereby form a gap; and disposing a second dielectric material into the gap to form an isolation component.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: February 26, 2019
    Assignee: Marvell World Trade Ltd.
    Inventors: Runzi Chang, Chuan-Cheng Cheng
  • Patent number: 10062767
    Abstract: Memory cells and fabrication methods thereof are provided. An exemplary method includes providing a substrate having a well region; forming a select gate structure, a floating gate structure and a dummy gate structure on a surface of the well region; forming a first lightly doped region, a second lightly doped region and a third lightly doped region in the well region, the first lightly doped region and the second lightly doped region being at two sides of the select gate structure respectively, the second lightly doped region being in between the select gate structure and the floating gate structure, and the third lightly doped region being in between the floating gate structure and the dummy gate structure; and forming bit line region in the first lightly doped region and a source region in the third lightly doped region, the source region being enclosed by the third lightly doped region.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: August 28, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Bo Hong, Shuai Zhang
  • Patent number: 10032675
    Abstract: The present invention further provides a method for forming a semiconductor device, comprising: first, a substrate having a fin structure disposed thereon is provided, wherein the fin structure has a trench, next, a first liner in the trench is formed, a first insulating layer is formed on the first liner, afterwards, a shallow trench isolation is formed in the substrate and surrounding the fin structure, wherein a bottom surface of the shallow trench isolation is higher than a bottom surface of the first insulating layer, and a top surface of the shallow trench isolation is lower than a top surface of the first insulating layer, and a dummy gate structure is formed on the first insulating layer and disposed above the trench, wherein a bottom surface of the dummy gate structure and a top surface of the fin structure are on a same level.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 24, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: I-Ming Tseng, Wen-An Liang, Chen-Ming Huang
  • Patent number: 9876019
    Abstract: Methods of producing integrated circuits and integrated circuits produced by those methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming first and second shallow trench isolations within a substrate, where the first and second shallow trench isolations have an initial shallow trench height. A base well is formed in the substrate, where the base well is positioned between the first and second shallow trench isolations. A gate dielectric is formed overlying the base well, and a floating gate is formed overlying the gate dielectric. An initial shallow trench height is reduced to a reduced shallow trench height shorter than the initial shallow trench height after the floating gate is formed.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: January 23, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xiong Zhang, Sunny Sadana, Yudi Setiawan, Yoke Leng Lim, Siow Lee Chwa
  • Patent number: 9858995
    Abstract: A memory device includes N word lines, wherein the word lines include an ith word line coupled to an ith memory cell and an (i+1)th word line coupled to an (i+1)th memory cell which is disposed adjacent to the ith memory cell and is a programmed memory cell, and i is an integer from 0 to (N?2). A method of operating such a memory device method includes a reading step. In the reading step, a read voltage is provided to the ith word line, a first pass voltage is provided to the (i+1)th word line, and a second pass voltage is provided to the others of the word lines, wherein the second pass voltage is lower than the first pass voltage.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 2, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Tao-Yuan Lin, I-Chen Yang, Yao-Wen Chang
  • Patent number: 9653402
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device including a fin structure, a first liner, a first insulating layer and a dummy gate structure. The fin structure is disposed on a substrate, where the fin structure has a trench. The first liner disposed in the trench. The first insulating layer disposed on the first liner. The dummy gate structure is disposed on the first insulating layer and disposed above the trench, where a bottom surface of the dummy gate and a top surface of the fin structure are on a same level.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: May 16, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: I-Ming Tseng, Wen-An Liang, Chen-Ming Huang
  • Patent number: 9647082
    Abstract: A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type; and a second contact region disposed at the surface, laterally spaced from the first contact region, and having a second conductivity type. The diode also includes a buried region disposed in the semiconductor substrate vertically adjacent to the first contact region, having the second conductivity type, and electrically connected with the second contact region; and an isolation region disposed at the surface between the first and second contact regions. The diode also includes a separation region disposed at the surface between the first contact region and the isolation region, the separation region formed from a portion of a first well region disposed in the semiconductor substrate that extends to the surface.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: May 9, 2017
    Assignee: NXP USA, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 9634018
    Abstract: A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: April 25, 2017
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chien-Sheng Su, Jeng-Wei Yang, Man-Tang Wu, Chun-Ming Chen, Hieu Van Tran, Nhan Do
  • Patent number: 9576848
    Abstract: A method of treating a porous dielectric layer includes preparing a substrate on which the porous dielectric layer including an opening and pores exposed by the opening is formed, supplying a first precursor onto the substrate to form a first sub-sealing layer sealing the exposed pores, and supplying a second precursor onto the first sub-sealing layer to form a second sub-sealing layer covering the first sub-sealing layer. Each of the first and second precursors includes silicon, and a molecular weight of the second precursor is smaller than that of the first precursor.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taejin Yim, Thomas Oszinda, Byunghee Kim, Sanghoon Ahn, Naein Lee, Keeyoung Jun
  • Patent number: 9543454
    Abstract: A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type; and a second contact region disposed at the surface, laterally spaced from the first contact region, and having a second conductivity type. The diode also includes a buried region disposed in the semiconductor substrate vertically adjacent to the first contact region, having the second conductivity type, and electrically connected with the second contact region; and an isolation region disposed at the surface between the first and second contact regions. The diode also includes a separation region disposed at the surface between the first contact region and the isolation region, the separation region formed from a portion of a first well region disposed in the semiconductor substrate that extends to the surface.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 10, 2017
    Assignee: NXP USA, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 9478531
    Abstract: A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: October 25, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jean Philippe Laine, Patrice Besse
  • Patent number: 9472462
    Abstract: A method of manufacturing a semiconductor integrated circuit device is provided. The method includes forming a plurality of pillars in a semiconductor substrate, forming an insulating layer between the plurality of pillars in such a manner that an upper region of each pillar protrudes, forming a silicide layer on an exposed surface of the pillar, and forming an insulating layer for planarization in a space between pillars.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: October 18, 2016
    Assignee: SK Hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 9466535
    Abstract: A method of forming target patterns is disclosed. A substrate with multiple fins is provided. A plurality of mask patterns is formed across the fins and in at least a part of non-target areas. Target patterns are formed respectively in trenches between the mask patterns. The mask patterns are removed. With the disclosed method, the target patterns can be formed with substantially equal thickness. In the case that the target patterns are dummy gates, the conventional defects such as dummy gate residues or gate trench widening caused by uneven thicknesses are not observed upon the dummy gate removal step.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: October 11, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Po-Cheng Huang, Kun-Ju Li, Yu-Ting Li, Chih-Hsun Lin
  • Patent number: 9343537
    Abstract: A device and method of forming the device using a split gate embedded memory technology are presented. The device includes two polysilicon layers, one for floating gate poly and the other for logic, HV and stack gate and split gate. An oxide-nitride-oxide process of the manufacturing method results in low reliability risk and good uniformity in the device. Moreover, embodiments of the manufacturing method have good controllability of the profile and critical dimension of select gates in production. Furthermore, there is no need to provide non-volatile memory and high-voltage protection for devices manufactured by embodiments of the manufacturing method of the present disclosure.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: May 17, 2016
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Yanzhe Tang
  • Patent number: 9337085
    Abstract: Air gaps are formed between bit lines by etching to remove sacrificial material from between bit lines. Bit lines are protected from etch damage. Sacrificial material may be selectively oxidized prior to deposition of bit line metal so that protective oxide lies along sides of bit lines during etch. Portions of protective material may be selectively formed on tops of bit lines prior to etching sacrificial material.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: May 10, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Jong Sun Sel, Marika Gunji-Yoneoka, Naoki Takeguchi, Chan Park, Tuan D. Pham, Kazuya Tokunaga
  • Patent number: 9330969
    Abstract: Air gaps are formed between bit lines by etching to remove sacrificial material from between bit lines. Bit lines are protected from etch damage. Sacrificial material may be selectively oxidized prior to deposition of bit line metal so that protective oxide lies along sides of bit lines during etch. Portions of protective material may be selectively formed on tops of bit lines prior to etching sacrificial material.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: May 3, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Jong Sun Sel, Marika Gunji-Yoneoka, Naoki Takeguchi, Chan Park, Tuan D. Pham, Kazuya Tokunaga
  • Patent number: 9269706
    Abstract: Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer. The flash memory region and the bipolar transistor are formed by depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: February 23, 2016
    Assignee: NXP, B.V.
    Inventors: Evelyne Gridelet, Hans Mertens, Michiel Jos van Duuren, Tony Vanhoucke, Viet Thanh Dinh
  • Patent number: 9177658
    Abstract: An one-transistor-one-bit (1T1b) Flash-based EEPROM cell is provided along with improved key operation schemes including applying a negative word line voltage and a reduced bit line voltage for perform erase operation, which drastically reduces the high voltage stress on each cell for enhancing the Program/Erase cycles while reducing cell size. An array made by the 1T1b Flash-based EEPROM cells can be operated with Half-page or Full-page divided programming and pre-charging period for each program cycle. Utilizing PGM buffer made of Vdd devices in the cell array further save silicon area. Additionally, a two-transistor-two-bit (2T2b) EEPROM cell derived from the 1T1b cell is disclosed with additional cell size reduction but with the operation of program and erase the same as that for the 1T1b cells with benefits of no process change but much enhanced storage density, superior Program/Erase endurance cycle, and capability for operating in high temperature environment.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: November 3, 2015
    Inventors: Peter Wung Lee, Hsing-Ya Tsao
  • Patent number: 9123778
    Abstract: For certain three dimensionally stacked memory devices, bit lines or word lines for memory cells are stacked in spaced apart ridge like structures arranged to extend in a first direction. In such structures, complementary wordlines or bit lines, can be damascene features between the spaced apart. The damascene conductors can be formed using double patterned masks to etch sub-lithographic sacrificial lines, forming a fill over the sacrificial lines, and then removing the sacrificial lines to leave trenches that act as the damascene molds in the fill. Then the trenches are filled with the conductor material. The 3D memory array can include dielectric charge trapping memory cells, which have a high-K blocking dielectric layer, and in which the conductor material comprises a high work function material.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: September 1, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, Yen-Hao Shih, Guanru Lee
  • Patent number: 9117689
    Abstract: The light-emitting device has a plurality of light-emitting elements that is mounted on one or more wiring patterns on a substrate. A new light-emitting element that replaces a defective element is mounted on the same wiring pattern on which the defective element is mounted. The defective element or a trace that remains after removal of the defective element is sealed by a same sealing member by which the new light-emitting element is sealed.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 25, 2015
    Assignee: NICHIA CORPORATION
    Inventor: Tadaaki Miyata
  • Patent number: 9117695
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a memory region and a periphery region; forming a memory cell on the memory region; forming a first polysilicon layer on the periphery region and the memory cell; forming a patterned cap layer on the periphery region; forming a second polysilicon layer on the first polysilicon layer and the patterned cap layer; and performing a chemical mechanical polishing (CMP) process to remove the second polysilicon layer, wherein the chemical mechanical polishing process comprises an abrasive of greater than 13% and a remove rate of less than 30 Angstroms/second.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: August 25, 2015
    Assignee: UNITED MIRCOELECTRONICS CORP.
    Inventors: Ji Gang Pan, Han Chuan Fang, Boon-Tiong Neo
  • Patent number: 9099325
    Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: August 4, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sung Kim, Tae-Young Chung, Soo-Ho Shin
  • Patent number: 9099334
    Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: August 4, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasushi Ishii, Hiraku Chakihara, Kentaro Saito
  • Patent number: 9093317
    Abstract: Semiconductor devices and fabrication methods are provided. A semiconductor substrate includes a first region and a second region. A gate dielectric material layer is formed to cover the first region, and a control gate dielectric layer is formed over a surface portion of the second region. The control gate dielectric layer has a top surface higher than the gate dielectric layer. A gate material layer is conformally formed to cover an entire surface of the semiconductor substrate and has a top surface in the second region higher than a top surface in the first region. A first filling material layer is formed on the gate material layer. A first patterned mask layer is formed on the first filling material layer to form a gate on a gate dielectric layer in the first region. A control gate is formed on the control gate dielectric layer of the second region.
    Type: Grant
    Filed: March 30, 2014
    Date of Patent: July 28, 2015
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Xinpeng Wang, Jing Pan, Qi Wang, Xianjie Ning
  • Patent number: 9093375
    Abstract: A semiconductor structure comprises a metal gate structure formed in a substrate, wherein the metal gate structure comprises a first film formed of a first material and formed on a bottom and sidewalls of a gate trench, a second film formed of a second material and formed over the first film and a gate electrode formed over the second film. The semiconductor structure further comprises a resistor structure formed in the substrate, where the resistor structure comprises a third film formed of the first material and formed on a bottom and sidewalls of a resistor trench and a fourth film formed of the second material and formed over the third film.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Jung Yen, Jen-Pan Wang
  • Patent number: 9087871
    Abstract: Nonvolatile memory devices and methods of fabricating the same, include, forming a transistor in a first region of a substrate, forming a contact which is connected to the transistor, forming an information storage portion, which is disposed two-dimensionally, in a second region of the substrate, sequentially forming a stop film and an interlayer insulating film which cover the contact and the information storage portion, forming a first trench, which exposes the stop film, on the contact, and forming a second trench which extends through the stop film to expose the contact, wherein a bottom surface of the first trench is lower than a bottom surface of the information storage portion.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: July 21, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kil-Ho Lee, Ki-Joon Kim, Se-Woong Park
  • Patent number: 9070564
    Abstract: A metal gate electrode and a poly-silicon resistance element are mixedly mounted in the same semiconductor substrate. The metal gate electrode is formed on a first gate insulating film and includes a first gate metal film and a first gate silicon film. The poly-silicon resistance element includes a silicon film pattern formed on a laminated pattern which includes a first laminate insulating film, a first laminate metal film, and a second laminate insulating film. The first laminate insulating film and the first gate insulating film are formed from a common insulating film; the first laminate metal film and the first gate metal film are formed from a common metal film, and the silicon firm pattern and the first gate silicon film are formed from a common silicon film. In a planar view, a footprint of the silicon film pattern is included within the second laminate insulating film.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: June 30, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Masaaki Shinohara
  • Patent number: 9054135
    Abstract: Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: June 9, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bing Li, Sung Mun Jung, Yi Tat Lim
  • Patent number: 9041092
    Abstract: A semiconductor device includes a pillar-shaped silicon layer including a first diffusion layer, a channel region, and a second diffusion layer formed in that order from the silicon substrate side, floating gates respectively disposed in two symmetrical directions so as to sandwich the pillar-shaped silicon layer, and a control gate line disposed in two symmetrical directions other than the two directions so as to sandwich the pillar-shaped silicon layer. A tunnel insulating film is formed between the pillar-shaped silicon layer and each of the floating gates. The control gate line is disposed so as to surround the floating gates and the pillar-shaped silicon layer with an inter-polysilicon insulating film interposed therebetween.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 26, 2015
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 8981449
    Abstract: A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8975114
    Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 10, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Dipankar Pramanik, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8962416
    Abstract: A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: February 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Cheong Min Hong, Sung-Taeg Kang, Konstantin V. Loiko, Jane A. Yater
  • Patent number: 8952444
    Abstract: A semiconductor storage device according to an embodiment comprises active areas on a semiconductor substrate. An element isolation is arranged between the active areas and filled by an insulating film. A plurality of memory cells configured to store data are formed on the active areas. Air gaps are arranged between upper-end edge parts of the active areas where the memory cells are formed and an insulating film in the element isolation.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideto Takekida
  • Patent number: 8946024
    Abstract: A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventor: Nam-Jae Lee
  • Patent number: 8946017
    Abstract: Numerous other aspects are provided a method for making a nonvolatile memory cell. The method includes forming a non-planar dielectric structure, and conformally depositing a semiconductor layer over the dielectric structure. A portion of the semiconductor layer serves as a channel region for a transistor, and the channel region is non-planar in shape.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: February 3, 2015
    Assignee: SanDisk 3D LLC
    Inventor: Roy E. Scheuerlein
  • Patent number: 8940623
    Abstract: A process for obtaining an array of nanodots (212) for microelectronic devices, characterized in that it comprises the following steps: deposition of a silicon layer (210) on a substrate (100, 132), formation, above the silicon layer (210), of a layer (240) of a material capable of self-organizing, in which at least one polymer substantially forms cylinders (242) organized into an array within a matrix (244), formation of patterns (243) in the layer (240) of a material capable of self-organizing by elimination of the said cylinders (242), formation of a hard mask (312) by transfer of the said patterns (243), production of silicon dots (212) in the silicon layer (210) by engraving through the hard mask (312), silicidation of the silicon dots (212), comprising deposition of a metal layer (510).
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: January 27, 2015
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, CNRS-Centre National de la Recherche Scientifique, Universite Joseph Fourier
    Inventors: Guillaume Gay, Thierry Baron, Eric Jalaguier
  • Patent number: 8936984
    Abstract: A three-dimensional (3-D) nonvolatile memory device includes channel layers protruding perpendicular to a surface of a substrate, interlayer insulating layers and conductive layer patterns alternately formed to surround each of the channel layers, a slit formed between the channel layers, the slit penetrating the interlayer insulating layers and the conductive layer patterns, and an etch-stop layer formed on the surface of the substrate at the bottom of the slit.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: January 20, 2015
    Assignee: SK Hynix Inc.
    Inventor: Joo Hee Han
  • Patent number: 8928062
    Abstract: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoki Yasuda
  • Patent number: 8927353
    Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Wang Hsu, Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai
  • Patent number: 8921175
    Abstract: An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: December 30, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Thierry Coffi Herve Yao, Gregory James Scott
  • Patent number: 8921136
    Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 8921922
    Abstract: This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Young-Jin Lee, Sung-Jin Whang
  • Patent number: 8895390
    Abstract: Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 25, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Dipankar Pramanik
  • Patent number: 8871585
    Abstract: A manufacturing method of a semiconductor device includes: forming a first gate insulating film on a semiconductor substrate in first and second regions in an active area; forming first gate electrodes on the first gate insulating film in the first and second regions; forming source/drain regions by introducing impurities at both sides of the first gate electrode in the first and second regions; performing heat treatment of activating the impurities; forming a stress liner film so as to cover the whole surface of first gate electrodes in the first and second regions; removing the stress liner film at an upper portion of the first gate electrode in the second region while allowing the stress liner film at least at a portion in the first region to remain to expose the upper portion of the first gate electrode in the second region; forming a groove by removing the first gate electrode in the second region; and forming a second gate electrode in the groove.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: October 28, 2014
    Assignee: Sony Corporation
    Inventor: Masanori Tsukamoto
  • Patent number: 8865536
    Abstract: As for a bypass capacitor, a first capacitor insulating film, together with a tunnel insulating film of a storage element, is formed of a first insulating film, a first electrode being a lower electrode, together with floating gate electrodes of the storage element, is formed of a doped·amorphous silicon film (a crystallized one), a second capacitor insulating film, together with a gate insulating film of transistors of 5 V in a peripheral circuit, is formed of a second insulating film, and a second electrode being an upper electrode, together with control gate electrodes of the storage element and gate electrodes of the transistors in the peripheral circuit, is formed of a polycrystalline silicon film.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: October 21, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tatsuya Sugimachi
  • Patent number: 8836009
    Abstract: A MONOS Charge-Trapping flash (CTF), with record thinnest 3.6 nm ENT trapping layer, has a large 3.1 V 10-year extrapolated retention window at 125° C. and excellent 106 endurance at a fast 100 ?s and ±16 V program/erase. This is achieved using As+-implanted higher ? trapping layer with deep 5.1 eV work-function of As. In contrast, the un-implanted device only has a small 10-year retention window of 1.9 V at 125° C. A MoN—[SiO2—LaAlO3]—[Ge—HfON]—[LaAlO3—SiO2]—Si CTF device is also provided with record-thinnest 2.5-nm Equivalent-Si3N4-Thickness (ENT) trapping layer, large 4.4 V initial memory window, 3.2 V 10-year extrapolated retention window at 125° C., and 3.6 V endurance window at 106 cycles, under very fast 100 ?s and low ±16 V program/erase. These were achieved using Ge reaction with HfON trapping layer for better charge-trapping and retention.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: September 16, 2014
    Assignee: National Chiao Tung University
    Inventors: Albert Chin, Chun-Yang Tsai
  • Patent number: 8828884
    Abstract: A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: September 9, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Yao-Sheng Lee, Zhen Chen, Syo Fukata
  • Patent number: 8823098
    Abstract: The invention discloses a manufacture method and structure of a power transistor, comprising a lower electrode, a substrate, a drift region, two first conductive regions, two second conductive regions, two gate units, an isolation structure and an upper electrode. The two second conductive region are between the two first conductive regions and the drift region; the two gate units are on the two second conductive regions; the isolation structure covers the two gate units; the upper electrode covers the isolation structure and connects to the two first conductive regions and the two second conductive regions electrically. When the substrate is of the first conductive type, the structure can be used as MOSFET. When the substrate is of the second conductive type, the structure can be used as IGBT. This structure has a small gate electrode area, which leads to less Qg, Qgd and Rdson and improves device performance.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: September 2, 2014
    Assignee: Wuxi Versine Semiconductor Corp. Ltd.
    Inventors: Qin Huang, Yuming Bai