Abstract: A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor comprising gate oxide and having a wide active area and/or a long channel, and the second transistor type may comprise a NAND comprising tunnel oxide and having a narrow active area and/or short gate length. The transistors are exposed to a nitridation ambient. Various process embodiments and completed structures are disclosed.

Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.

Abstract: In a non-volatile memory cell, a single poly SOI technology is used to save space and achieve low current programming by providing two capacitors formed in an n-material over an NBL, forming a inverter in an n-material over a PBL, and isolating the NBL from the PBL by means of a lightly doped region or a deep trench isolation region.

Abstract: A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.

Abstract: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18) and running in a length direction of the trenches (11). According to the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, in which higher memory capacity can be achieved.

Abstract: A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.

Abstract: A semiconductor memory includes memory cell transistors including a tunnel insulating film, a floating gate electrode, a first insulating film, a control gate electrode, and a first metal salicide film; low-voltage transistors having a first p-type source region and a first p-type drain region, a first gate insulating film, and a first gate electrode of an n conductivity type having the same dose of a first p-type impurity as with the first p-type source region; and high-voltage transistors having a second p-type source region and a second p-type drain region, a second gate insulating film thicker than the first gate insulating film, and a second gate electrode of an n conductivity type having the same dose of a second p-type impurity as with the second p-type source region.

Abstract: A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.

Abstract: A semiconductor device manufacturing method includes forming a first insulating film on a semiconductor substrate containing silicon, the first insulating film having a first dielectric constant and constituting a part of a tunnel insulating film, forming a floating gate electrode film on the first insulating film, the floating gate electrode film being formed of a semiconductor film containing silicon, patterning the floating gate electrode film, the first insulating film, and the semiconductor substrate to form a first structure having a first side surface, exposing the first structure to an atmosphere containing an oxidizing agent, oxidizing that part of the floating gate electrode film which corresponds to a boundary between the first insulating film and the floating gate electrode film using the oxidizing agent, to form a second insulating film having a second dielectric constant smaller than the first dielectric constant and constituting a part of the tunnel insulating film.

Abstract: A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.

Abstract: A high voltage transistor exhibiting an improved breakdown voltage and related methods are provided. For example, a method of manufacturing an integrated circuit includes etching a poly silicon layer to provide a gate stacked above a floating gate of a flash memory cell. A source and a drain of the flash memory cell are implanted in a substrate. The poly silicon layer is etched to provide a gate of a high voltage transistor. Lightly doped drain (LDD) implants are provided in source/drain regions of the high voltage transistor in the substrate. An annealing operation is performed on the integrated circuit, wherein the annealing causes each of the LDD implants to form a graded junction in relation to a channel in the substrate between the LDD regions, and further causes sidewalls to oxidize on the gates of the flash memory cell and on the gate of the high voltage transistor.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.

Abstract: A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.

Abstract: Embodiments of the invention provide a method to form a high-k dielectric layer on a group III-V substrate with substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer. Oxide may be removed from the substrate. An organometallic compound may form a capping layer on the substrate from which the oxide was removed. The high-k dielectric layer may then be formed, resulting in a thin transition layer between the substrate and high-k dielectric layer and substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer.

Abstract: An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack.

Abstract: A semiconductor device includes a fin-shaped semiconductor layer, a gate electrode section formed in a widthwise direction of the semiconductor layer with a gate insulation film interposed therebetween, the gate electrode section including a plurality of electrode materials having different work functions and stacked one another, and a channel section formed adjacent to the gate insulation film in the semiconductor layer. The semiconductor device further includes source and drain regions formed adjacent to the channel section.

Abstract: A polysilicon layer provided for a polysilicon electrode (8) is patterned by means of a resist mask (5) and an auxiliary layer (4) made of a material that is suitable as an antireflection layer, the auxiliary layer (4) being provided with lateral hollowed-out recesses in such a way that the polysilicon electrode is formed with rounded edges (7) during etching. The auxiliary layer is preferably produced from a soluble material and with a thickness of 70 nm to 80 nm. A base layer (2) may be provided as a gate dielectric of memory cell transistors and additionally as an etching stop layer.

Abstract: A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.

Abstract: A low resistance contact is formed to a metal gate or a transistor including a High-? gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.

Abstract: Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming a cup-shaped electrode on sidewalls of an opening in an insulation layer and through the opening on an ohmic layer that is stacked on a conductive structure. An insulation filling member is formed that at least partially fills an interior of the electrode. The insulation filling member is formed within a range of temperatures that is sufficiently low to not substantially change resistance of the ohmic layer. A variable resistivity material is formed on the insulation filling member and is electrically connected to the electrode.

Abstract: Methods of manufacturing non-volatile memory devices that can reduce or prevent loss of charges stored in a charge storage layer and/or that can improve charge storage capacity by neutral beam irradiation of an insulating layer are disclosed. The methods include forming a tunneling insulating layer on a substrate, forming a charge storage layer on the tunneling insulating layer, forming a blocking insulating layer on the charge storage layer, irradiating the blocking insulating layer and/or the tunneling insulating layer with a neutral beam, and forming a gate conductive layer on the blocking insulating layer.

Abstract: A semiconductor integrated circuit device includes a substrate, a nonvolatile memory device formed in a memory cell region of the substrate, and a semiconductor device formed in a device region of the substrate. The nonvolatile memory device has a multilayer gate electrode structure including a tunnel insulating film and a floating gate electrode formed thereon. The floating gate electrode has sidewall surfaces covered with a protection insulating film. The semiconductor device has a gate insulating film and a gate electrode formed thereon. A bird's beak structure is formed of a thermal oxide film at an interface of the tunnel insulating film and the floating gate electrode, the bird's beak structure penetrating into the floating gate electrode along the interface from the sidewall faces of the floating gate electrode, and the gate insulating film is interposed between the substrate and the gate electrode to have a substantially uniform thickness.

Abstract: Non-volatile memory is described. The non-volatile memory includes a substrate having a source region, a drain region and a channel region. The channel region separates the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A floating gate electrode is adjacent to the electrically insulating layer. The electrically insulating layer separates the floating gate electrode from the channel region. The floating gate electrode has a floating gate major surface. A control gate electrode has a control gate major surface and the control gate major surface opposes the floating gate major surface. A vacuum layer or gas layer at least partially separates the control gate major surface from the floating gate major surface.

Abstract: Floating-gate memory cells having carbon nanotubes interposed between the substrate and the tunnel dielectric layer facilitate ballistic injection of charge into the floating gate. The carbon nanotubes may extend across the entire channel region or a portion of the channel region. For some embodiments, the carbon nanotubes may be concentrated near the source/drain regions. For some embodiments, the tunnel dielectric layer may adjoin the substrate in at least a portion of the channel region.

Abstract: Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer.

Abstract: A method for manufacturing a nanotube non-volatile memory cell is proposed. The method includes the steps of: forming a source electrode and a drain electrode, forming a nanotube implementing a conduction channel between the source electrode and the drain electrode, forming an insulated floating gate for storing electric charges by passivating conductive nanoparticles with passivation molecules and arranging a disposition of passivated conductive nanoparticles on the nanotube, the conductive nanoparticles being adapted to store the electric charges and being insulated by the passivation molecules from the nanotube, and forming a control gate coupled with the channel.

Abstract: A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.

Abstract: In methods of manufacturing a memory device, a tunnel insulation layer is formed on a substrate. A floating gate having a substantially uniform thickness is formed on the tunnel insulation layer. A dielectric layer is formed on the floating gate. A control gate is formed on the dielectric layer. A flash memory device including the floating gate may have more uniform operating characteristics.

Abstract: A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved.

Abstract: According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a first conductive layer formed as a floating gate on the first insulating layer, a second insulating layer formed as an interelectrode insulating film on the first conductive layer, and comprising three layers of a first film mainly including silicon and oxygen, a second film mainly including silicon and nitrogen, and a third film mainly including silicon and oxygen, wherein a silicon and nitrogen composition ratio of the second film is in a state in which the silicon is in excess of a stoichiometric composition, and a second conductive layer formed as a control gate on the second insulating film.

Abstract: A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion disposed over and insulated from the channel region and a second portion disposed over and insulated from the first region and including a sharpened edge, an electrically conductive P/E gate having a first portion disposed over and insulated from the first region and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material, and an electrically conductive select gate having a first portion disposed laterally adjacent to the floating gate and disposed over and insulated from the channel region.

Abstract: A method of fabricating a flash memory and an isolating structure applied to a flash memory is provided. The feature of the method lies in a T-shaped shallow trench isolation (STI). The T-shaped STI has a widened cap covering on a substrate and a tapered bottom embedded in the substrate. The widened cap of the T-shaped STI can provide a high process widow when fabricating the floating gate wings, and the product yield will thereby be increased.

Abstract: Various embodiments include a substrate and a memory cell coupled to the substrate. The memory cell may include an L-shaped floating gate, a control gate, an insulation layer coupled between the control gate and the first L-shaped floating gate, and a conductive layer coupled between the substrate and the first L-shape floating gate. Other embodiments including additional apparatus, systems, and methods are disclosed.

Abstract: A non-volatile memory transistor with a nanocrystal-containing floating gate formed by nanowires is disclosed. The nanocrystals are formed by the growth of short nanowires over a crystalline program oxide. As a result, the nanocrystals are single-crystals of uniform size and single-crystal orientation.

Abstract: A semiconductor memory device includes a plurality of memory transistors. Each of the memory transistors has: a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The floating gate electrode includes, in a cross section taken along a bit line direction, a first conductive film, first sidewall insulating films opposed to each other across the first conductive film, and a second conductive film provided on the first sidewall insulating films and the first conductive film. The interelectrode insulating film is provided on the second conductive film. The control gate electrode includes a third conductive film provided on the interelectrode insulating film and a fourth conductive film provided on the third conductive film.

Abstract: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a gate insulating film and an active layer on a substrate, forming a data metal layer including a first, second, and third metal layers on the active layer, forming a first photoresist pattern on the data metal layer, dry-etching the third metal layer by using the first photoresist pattern, simultaneously dry-etching the second and first metal layers by using the first photoresist pattern, dry-etching the active layer by using the first photoresist pattern, etching the first photoresist pattern to form a second photoresist pattern by which the channel region is removed and forming a source electrode and a drain electrode by dry-etching the channel region of the data metal layer by using the second photoresist pattern.

Abstract: The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel; the control gate being in contact with the charge storage stack, wherein—an access gate is provided adjacent to one sidewall portion and separated therefrom by an intermediate gate oxide layer, and—the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer.

Abstract: A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches. Furthermore, a method for forming floating-gate electrodes on a semiconductor substrate and an integrated circuit is described.

Abstract: A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film (21a) in the cell array region, gate oxide film (21b) for a high-voltage circuit and gate oxide film (21c) for a low-voltage circuit both in the peripheral circuit to respectively optimum values of thickness, and covering them with a first-layer polycrystalline silicon film (22). After that, device isolation grooves (13) are formed and buried with a device isolation insulating film (14). The first-layer polycrystalline silicon film (24) is a non-doped film, and after device isolation, a second-layer polycrystalline silicon film (24) is doped with phosphorus in the cell array region to form floating gates made of the first-layer polycrystalline silicon film (22) and the second-layer polycrystalline silicon film (24).

Abstract: A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.

Abstract: A method of manufacturing a flash memory device is disclosed. The method includes the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined, etching the semiconductor substrate in the select transistor region so that there is a first step between the cell region and the select transistor region, forming a cell gate in the cell region, and forming a transistor in the select transistor region.

Abstract: In one embodiment, an EEPROM device is formed to include a metal layer having an opening therethrough. The opening overlies a portion of a floating gate of the EEPROM device.

Abstract: Cell gate patterns including first portions separated from each other with a first distance and second portions separated from each other with a second distance less than the first distance, and spacers are formed both sidewalls of the pair of cell gate patterns. The spacers formed on the sidewalls of the second portions are removed using a mask pattern. Accordingly, it is possible to prevent increase of an aspect ratio of a gap between the second portions with the small distance. Since the spacers formed on the sidewalls of the second portions separated from each other with the small distance are selectively removed, it is possible to minimize the increase of the aspect ratio of the gap between the second portions. Thus, it is possible to solve various problems which are caused due to occurrence of a void.

Abstract: A flash memory device and a method of manufacturing the same is disclosed. A gate dielectric film formed between a floating gate and a control gate of a flash memory device is formed by laminating an oxide film and a ZrO2 film. Accordingly, the reliability of the flash memory can be improved while securing a high coupling ratio.

Abstract: A SOI device features a conductive pathway between active SOI devices and a bulk SOI substrate. The conductive pathway provides the ability to sink plasma-induced process charges into a bulk substrate in the event of process charging, such as interlayer dielectric deposition in a plasma environment, plasma etch deposition, or other fabrication provides. A method is also disclosed which includes dissipating electrostatic and process charges from a top of a SOI device to the bottom of the device. The top and bottom of the SOI device may characterize a region of active devices and a semiconductor method respectively. The method further includes a single masking step to create seed regions for an epitaxial-silicon pathway.

Abstract: In a nonvolatile memory using floating gates to store charge, individual floating gates are L-shaped. Orientations of L-shaped floating gates may alternate in the bit line direction and may also alternate in the word line direction. L-shaped floating gates are formed by etching conductive portions using etch masks of different patterns to obtain floating gates of different orientations.

Abstract: A metal line of a semiconductor device comprising contact plugs, a plurality of first trenches, first metal lines, a plurality of second trenches, and second metal lines. The contact plugs are formed over a semiconductor substrate and are insulated from each other by a first insulating layer. The plurality of first trenches are formed in the first insulating layer and are connected to first contact plugs of the contact plugs. The first metal lines are formed within the first trenches and are connected to the first contact plugs. The plurality of second trenches are formed over the first metal lines and the first insulating layer and comprise a second insulating layer connected to second contact plugs of the contact plugs. The second metal lines are formed within the second trenches and are connected to the second contact plugs.

Abstract: A dielectric structure in a nonvolatile memory device and a method for fabricating the same are provided. The dielectric structure includes: a first oxide layer; a first high-k dielectric film formed on the first oxide layer, wherein the first high-k dielectric film includes one selected from materials with a dielectric constant of approximately 9 or higher and a compound of at least two of the materials; and a second oxide layer formed on the first high-k dielectric film.

Abstract: According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate belo

Abstract: In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of second semiconductor portions to prepare a plurality of floating gates with substantially flat surfaces; forming an insulating layer over said plurality of floating gates; and forming a control gate over said insulating layer.