Including Isolation Structure Patents (Class 438/207)
  • Patent number: 10128293
    Abstract: A pixel sensor device is disclosed. The device includes a shallow trench isolation structure, a well region and a backside isolation structure. The well region and diode region is adjacent to the shallow trench isolation structure. The backside isolation structure is self-aligned with and arranged over the shallow trench isolation structure. The backside isolation structure is adjacent to the diode region.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yimin Huang, Jhy-Jyi Sze, Alexander Kalnitsky
  • Patent number: 10128113
    Abstract: A semiconductor structure comprises a substrate comprising an interlayer dielectric (ILD) and a silicon layer disposed over the ILD, wherein the ILD comprises a conductive structure disposed therein, a dielectric layer disposed over the silicon layer, and a conductive plug electrically connected with the conductive structure and extended from the dielectric layer through the silicon layer to the ILD, wherein the conductive plug has a length running from the dielectric layer to the ILD and a width substantially consistent along the length.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Pei Chou, Chen-Fa Lu, Jiech-Fun Lu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 9502283
    Abstract: Electron-beam (e-beam) based semiconductor device features are disclosed. In a particular aspect, a method includes performing a first lithography process to fabricate a first set of cut pattern features on a semiconductor device. A distance of each feature of the first set of cut pattern features from the feature to an active area is greater than or equal to a threshold distance. The method further includes performing an electron-beam (e-beam) process to fabricate a second cut pattern feature on the semiconductor device. A second distance of the second cut pattern feature from the second cut pattern feature to the active area is less than or equal to the threshold distance.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: November 22, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Stanley Seungchul Song, Jeffrey Junhao Xu, Da Yang, Choh Fei Yeap
  • Patent number: 9449635
    Abstract: The embodiments of the present invention generally relate to a method for forming a trench in which a write pole is deposited therein. The trench is formed with a single mask and multiple reactive ion etching (RIE) processes and has substantially straight side walls and a consistent bevel angle along the length of the write pole. The consistent bevel angle along the length of the write pole allows the bevel angle at the ABS to be consistent regardless of where the cut is when defining the ABS.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: September 20, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Wen-Chien David Hsiao, Kyusik Shin, Sue Siyang Zhang
  • Patent number: 9443773
    Abstract: Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate (100) to form a buried region (150, 260) therein; forming a halo implant (134) using an impurity of a second type and a shallow implant (132) using an impurity of the first type, said halo implant enveloping the shallow implant in the substrate and being located over said buried region (150, 250); forming, adjacent to the halo implant (134), a further implant (136) using an impurity of the second type for providing a conductive connection to the halo implant; and providing respective connections (170, 160, 270) to the further implant (136), the shallow implant (132) and the buried region (150, 260) allowing the shallow implant, halo implant and buried region to be respectively operable as emitter, base and collector of the vertical bipolar transistor.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: September 13, 2016
    Assignee: NXP B.V.
    Inventors: Tony Vanhoucke, Anco Heringa, Johannes Josephus Theodorus Martinus Donkers, Jan Willem Slotboom
  • Patent number: 9310643
    Abstract: A liquid crystal on silicon (LCOS) device includes a semiconductor substrate, a metal-oxide semiconductor (MOS) device layer overlying the semiconductor substrate, a planarized interlayer dielectric layer overlying the MOS device layer, a plurality of recessed regions formed within a portion of the interlayer dielectric layer, a metal layer filling each of the recessed regions to form a plurality of respective electrode plates corresponding to each of the recessed regions. The LCOS device further includes a protective layer overlying a surface of each of the plurality of electrode plates, a liquid crystal film overlying the protective layer, and a mirror finish formed on each of the surface of the electrode plates for reflecting light. The mirror finish is substantially free from dishes and scratches from a chemical mechanical polishing process.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: April 12, 2016
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Roger Lee, Guoqing Chen, Lee Chang
  • Patent number: 9099338
    Abstract: A semiconductor device and method of forming the same includes a substrate having a NMOS region and a PMOS region. The method includes forming a dummy gate structure having a stacked sacrificial dielectric layer and a sacrificial gate material layer on the NMOS and PMOS regions. The method further includes concurrently removing the stacked sacrificial dielectric layer and a sacrificial gate material layer to form a groove, and forming a high-K dielectric layer and a first metal gate layer in the grove. The method also includes forming a hard mask over the NMOS region, removing the first metal gate layer and the high-K dielectric layer in the PMOS region to form a channel groove, forming a second high-K dielectric layer and a second metal gate layer in the channel grove, and removing the hard mask. The work function metal layer in the NMOS and PMOS regions can be independently controlled.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: August 4, 2015
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Qiuhua Han
  • Patent number: 9034705
    Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: May 19, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Chin-Cheng Chien, Tien-Wei Yu, Hsin-Kuo Hsu, Yu-Shu Lin, Szu-Hao Lai, Ming-Hua Chang
  • Patent number: 9034712
    Abstract: A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Erik M. Dahlstrom, Robert J. Gauthier, Jr., Ephrem G. Gebreselasie, Richard A. Phelps, Jed H. Rankin, Yun Shi
  • Patent number: 9012279
    Abstract: A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: April 21, 2015
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Donghua Liu, Wenting Duan, Wensheng Qian, Jun Hu, Jing Shi
  • Patent number: 8993394
    Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies AG
    Inventors: Karlheinz Mueller, Robert Gruenberger, Bernhard Winkler
  • Patent number: 8975132
    Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Hyung-Hwan Kim, Bong-Ho Choi, Jin-Yul Lee, Seung-Seok Pyo
  • Patent number: 8975687
    Abstract: An integrated circuit of an array of nonvolatile memory cells has a dielectric stack layer over the substrate, and implanted regions in the substrate under the dielectric stack layer. The dielectric stack layer is continuous over a planar region, that includes locations of the dielectric stack layer that store nonvolatile data, such that these locations are accessed by word lines/bit lines.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: March 10, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Tzu-Hsuan Hsu, Sheng-Chih Lai
  • Patent number: 8956948
    Abstract: A semiconductor device is formed with extended STI regions. Embodiments include implanting oxygen under STI trenches prior to filling the trenches with oxide and subsequently annealing. An embodiment includes forming a recess in a silicon substrate, implanting oxygen into the silicon substrate below the recess, filling the recess with an oxide, and annealing the oxygen implanted silicon. The annealed oxygen implanted silicon extends the STI region, thereby reducing leakage current between N+ diffusions and N-well and between P+ diffusions and P-well, without causing STI fill holes and other defects.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: February 17, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yanxiang Liu, Bin Yang
  • Patent number: 8921195
    Abstract: Methods for fabricating a device structure, as well as device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Peng Cheng, Peter B. Gray, Vibhor Jain, Robert K. Leidy, Qizhi Liu
  • Patent number: 8907429
    Abstract: A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region; a drain diffusion region; a first insulating region contacting a lower end of the source diffusion region; a second insulating region contacting a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region. The first well is disposed below the gate electrode and is electrically connected with the contact region via the silicon substrate under the sub-region. The lower end of the element isolation region except the sub-region is located lower than the lower end of the first well.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: December 9, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Eiji Yoshida, Akihisa Yamaguchi
  • Patent number: 8889506
    Abstract: An integrated circuit die includes a semiconductor substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer. Trenches are formed in the first and second dielectric layers. Metal interconnection tracks are formed on sidewalls of the trench on the exposed portions of the second dielectric layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: November 18, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo
  • Patent number: 8883588
    Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Soo Ahn, O Ik Kwon, Bum-Soo Kim, Hyun-Sung Kim, Kyoung-Sub Shin, Min-Kyung Yun, Seung-Pil Chung, Won-Bong Jung
  • Patent number: 8883544
    Abstract: A method of forming of an image sensor device includes an isolation well formed in a pixel region of a substrate. The isolation well has a first conductivity type. A gate stack is formed over the isolation well on the substrate. A mask layer is formed over the isolation well and covering at least a majority portion of the gate stack. A plurality of dopants is implanted in the pixel region, using the gate stack and the mask layer as masks, to form doped isolation features. The plurality of dopants has the first conductivity type. A source region and a drain region are formed on opposite sides of the gate stack in the substrate. The source region and the drain region have a second conductivity type opposite to the A conductivity.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Min-Feng Kao, Jen-Cheng Liu, Feng-Chi Hung, Dun-Nian Yaung
  • Patent number: 8836075
    Abstract: According to one embodiment, a fabrication method for a semiconductor device includes: injecting an ion into a first substrate; joining the first substrate and a second substrate; irradiating a microwave to agglomerate the ion in a planar state in a desired position in the first substrate and form an agglomeration region spreading in a planar state; separating the second substrate provided with a part of the first substrate from the rest of the first substrate by exfoliating the joined first substrate from the second substrate in the agglomeration region; and grinding a part of the second substrate on a back surface opposite to an exfoliated surface in the second substrate provided with a part of the first substrate.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kyoichi Suguro
  • Patent number: 8828843
    Abstract: A method of manufacturing an isolation structure includes forming a laminate structure on a substrate. A plurality trenches is formed in the laminate structure. Subsequently a pre-processing is effected to form a hydrophilic thin film having oxygen ions on the inner wall of the trenches. Spin-on-dielectric (SOD) materials are filled into the trenches. The hydrophilic think film having oxygen ions changes the surface tension of the inner wall of the trenches and increases SOD material fluidity.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: September 9, 2014
    Assignee: Inotera Memories, Inc.
    Inventors: Yaw-Wen Hu, Jung-Chang Hsieh, Kuen-Shin Huang, Jian-Wei Chen, Ming-Tai Chien
  • Patent number: 8822304
    Abstract: An trench isolation structure and method for manufacturing the trench isolation structure are disclosed. An exemplary trench isolation structure includes a first portion and a second portion. The first portion extends from a surface of a semiconductor substrate to a first depth in the semiconductor substrate, and has a width that tapers from a first width at the surface of the semiconductor substrate to a second width at the first depth, the first width being greater than the second width. The second portion extends from the first depth to a second depth in the semiconductor substrate, and has substantially the second width from the first depth to the second depth.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shiang-Bau Wang
  • Publication number: 20140183655
    Abstract: A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.
    Type: Application
    Filed: December 19, 2013
    Publication date: July 3, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Derek W. ROBINSON, Amitava CHATTERJEE
  • Patent number: 8759175
    Abstract: A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Louis C. Hsu, Xu Ouyang, Ping-Chuan Wang, Zhijian J. Yang
  • Patent number: 8692266
    Abstract: A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: April 8, 2014
    Assignee: Optromax Electronics Co., Ltd
    Inventor: Kuo-Tso Chen
  • Patent number: 8679938
    Abstract: A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sunfei Fang, Oleg Gluschenkov, Byeong Y. Kim, Rishikesh Krishnan, Daewon Yang
  • Patent number: 8673710
    Abstract: When forming sophisticated high-k metal gate electrode structures, the uniformity of the device characteristics may be enhanced by growing a threshold adjusting semiconductor alloy on the basis of a hard mask regime, which may result in a less pronounced surface topography, in particular in densely packed device areas. To this end, in some illustrative embodiments, a deposited hard mask material may be used for selectively providing an oxide mask of reduced thickness and superior uniformity.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Rohit Pal
  • Patent number: 8669590
    Abstract: Methods and apparatus for forming semiconductor structures are disclosed herein. In some embodiments, a semiconductor structure may include a first germanium carbon layer having a first side and an opposing second side; a germanium-containing layer directly contacting the first side of the first germanium carbon layer; and a first silicon layer directly contacting the opposing second side of the first germanium carbon layer. In some embodiments, a method of forming a semiconductor structure may include forming a first germanium carbon layer atop a first silicon layer; and forming a germanium-containing layer atop the first germanium carbon layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: March 11, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Errol Antonio C. Sanchez, Yi-Chiau Huang
  • Patent number: 8669621
    Abstract: A semiconductor device includes a first insulated gate field effect transistor, a second insulated gate field effect transistor, a bipolar transistor, a first element isolation structure formed on a main surface above a pn junction formed between an emitter region and a base region, a second element isolation structure formed on the main surface above a pn junction formed between the base region and a collector region, and a third element isolation structure formed on the main surface opposite to the second element isolation structure relative to the collector region, in which the semiconductor device further includes a bipolar dummy electrode formed on at least one of the first element isolation structure, the second element isolation structure and the third element isolation structure and having a floating potential.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: March 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Keiichi Yamada
  • Patent number: 8642419
    Abstract: Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure in the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: February 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Jorg Radecker, Hans-Juergen Thees, Peter Javorka
  • Patent number: 8642429
    Abstract: A semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD is disclosed. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 4, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Xiaobin Wang, Anup Bhalla, Yeeherg Lee
  • Patent number: 8610239
    Abstract: A semiconductor device including an isolation layer structure including a doped polysilicon layer pattern doped with first and second impurities of first and second conductivity types at lower and upper portions thereof, the doped polysilicon layer pattern being on an inner wall of a first trench on a substrate including an active region in which the first trench is not formed and a field region including the first trench, and an insulation structure filling a remaining portion of the first trench; a gate structure on the active region; a well region at a portion of the active region adjacent to lower portions of the doped polysilicon layer pattern and being doped with third impurities of the second conductivity type; and a source/drain at a portion of the active region adjacent to upper portions of the doped polysilicon layer pattern and being doped with fourth impurities of the first conductivity type.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: December 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Uk Han, Satoru Yamada
  • Patent number: 8609483
    Abstract: Electrical device structures constructed in an isolated p-well that is wholly contained within a core n-well. Methods of forming electrical devices within an isolated p-well that is wholly contained within a core n-well using a baseline CMOS process flow.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: December 17, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Kamel Benaissa, Greg C. Baldwin
  • Patent number: 8603873
    Abstract: A method for forming a bipolar junction transistor comprises forming a first well of a second conductive type for forming a collector region in a substrate including device isolation layers, wherein the substrate comprises a first conductive type, forming a second well of the first conductive type for a metal-oxide-semiconductor transistor of the second conductive type within the first well of the second conductive type, wherein the second well of the first conductive type is formed deeper than the device isolation layers, forming a shallow third well of the first conductive type for a base region within the first well of the second conductive type, wherein the shallow third well of the first conductive type is formed shallower than the device isolation layers, and simultaneously forming an emitter region within the shallow third well of the first conductive type and a plurality of collector contacts within the first well of the second conductive type by performing an ion implantation process for forming sour
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: December 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je-Don Kim
  • Patent number: 8536002
    Abstract: A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: September 17, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroshi Yasuda, Berthold Staufer
  • Patent number: 8530999
    Abstract: A semiconductor component with straight insulation trenches formed in a semiconductor material providing semiconductor areas laterally insulated from each other. Each insulation trench has a uniform width along its longitudinal direction represented by a central line. The semiconductor component has an intersecting area into which at least three of the straight insulation trenches lead. A center of the intersecting area is defined as a point of intersection of the continuations of the center lines. A central semiconductor area disposed in the intersecting area is connected with one of the semiconductor areas and contains the center of the intersecting area.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: September 10, 2013
    Assignee: X-FAB Semiconductor Foundries AG
    Inventors: Ralf Lerner, Uwe Eckoldt
  • Patent number: 8530286
    Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: September 10, 2013
    Assignee: SuVolta, Inc.
    Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachin R. Sonkusale, Weimin Zhang
  • Publication number: 20130175614
    Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor device includes a substrate having a first region including a first element and a second region including a second element and including a lower substrate and an upper substrate bonded to each other, an epitaxial layer and an insulating layer disposed between the lower substrate and the upper substrate, the epitaxial layer disposed in the first region, and the insulating layer disposed in the second region, a device isolation pattern separating the first element from the second element, and a doped pattern disposed between the upper substrate and the insulating layer and between the upper substrate and the epitaxial layer. The first element is electrically connected to the lower substrate through the doped pattern and the epitaxial layer. The second element is electrically insulated from the lower substrate by the doped pattern and the insulating layer.
    Type: Application
    Filed: September 10, 2012
    Publication date: July 11, 2013
    Applicant: Electronics and Telecommunications Research Institute
    Inventor: KYOUNG IL NA
  • Patent number: 8460992
    Abstract: A method of manufacturing a semiconductor device comprises forming a first insulator in the first area of a substrate and a second insulator formed in a second area of the substrate; forming an etching preventing film extending over the first device region surrounded by the first area and the second device region surrounded by the second area removing the etching preventing film from the first device region and first area forming a first gate insulating film over the first device region while the second device region and the second area are covered by the etching preventing film; removing the etching preventing film over the second device region and the second area forming a second gate insulating film over the second device region; and forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: June 11, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Toru Anezaki
  • Patent number: 8432000
    Abstract: High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: April 30, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Thomas E. Grebs
  • Patent number: 8415764
    Abstract: An integrated circuit device includes a semiconductor substrate having a top surface; at least one insulation region extending from the top surface into the semiconductor substrate; a plurality of base contacts of a first conductivity type electrically interconnected to each other; and a plurality of emitters and a plurality of collectors of a second conductivity type opposite the first conductivity type. Each of the plurality of emitters, the plurality of collectors, and the plurality of base contacts is laterally spaced apart from each other by the at least one insulation region. The integrated circuit device further includes a buried layer of the second conductivity type in the semiconductor substrate, wherein the buried layer has an upper surface adjoining bottom surfaces of the plurality of collectors.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: April 9, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tao-Wen Chung, Po-Yao Ke, Wei-Yang Lin, Shine Chung
  • Patent number: 8415214
    Abstract: Transistor devices are formed with a nitride cap over STI regions during FEOL processing. Embodiments include forming a pad oxide layer on a substrate, forming an STI region in the substrate so that the top surface is level with the top surface of the pad oxide, forming a nitride cap on the STI region and on a portion of the pad oxide layer on each side of the STI region, implanting a dopant into the substrate, deglazing the nitride cap and pad oxide layer, removing the nitride cap, and removing the pad oxide layer. Embodiments include forming a silicon germanium channel (c-SiGe) in the substrate prior to deglazing the pad oxide layer. The nitride cap protects the STI regions and immediately adjacent area during processes that tend to degrade the STI oxide, thereby providing a substantially divot free substrate and an STI region with a zero step height for the subsequently deposited high-k dielectric and metal electrode.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: April 9, 2013
    Assignee: Globalfoundries, Inc.
    Inventors: Frank Jakubowski, Peter Baars, Jörg S. Radecker
  • Patent number: 8405156
    Abstract: A semiconductor device includes a substrate (e.g., a P-type semiconductor substrate), and an isolation region formed in the substrate to isolate an element formation region from the other region. The semiconductor device also includes a gate electrode formed over the element formation region. The gate electrode extends over each of first and second regions of the isolation region opposing each other with the element formation region interposed therebetween. The semiconductor device further includes a pair of diffusion regions (e.g., N-type diffusion regions) formed in the element formation region so as to be spaced apart from each other in a channel length direction with reference to the gate electrode. At least a portion of each of upper surfaces of the first and second regions is depressed to a depth of not less than 5% of a channel width to be located under an upper surface of the element formation region. In each of resultant depressions also, a portion of the gate electrode is present.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: March 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Yoshida, Shuichi Ohya
  • Patent number: 8368161
    Abstract: A solid-state image capturing device includes, in a semiconductor substrate, a photoelectric conversion section which performs photoelectric conversion on incident light to obtain signal charges; a pixel transistor section which outputs the signal charges generated in the photoelectric conversion section; a peripheral circuit section which is formed in the periphery of a pixel section including the photoelectric conversion section and the pixel transistor section; and isolation areas which electrically separate the photoelectric conversion section, the pixel transistor section, and the peripheral circuit section from each other. The isolation areas in the periphery of the pixel transistor section each have an insulating section formed higher than a surface of the semiconductor substrate. A first gate electrode of a transistor of the pixel transistor section is formed between the insulating sections and on the semiconductor substrate with a gate insulating film interposed therebetween.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: February 5, 2013
    Assignee: Sony Corporation
    Inventors: Fumihiko Koga, Yoshiharu Kudoh
  • Patent number: 8350336
    Abstract: In a semiconductor device and a method of manufacturing the same, a first insulation layer is removed from a cell area of a substrate and a first active pattern is formed on the first area by a laser-induced epitaxial growth (LEG) process. Residuals of the first insulation layer are passively formed into a first device isolation pattern on the first area. The first insulation layer is removed from the second area of the substrate and a semiconductor layer is formed on the second area of the substrate by a SEG process. The semiconductor layer on the second area is patterned into a second active pattern including a recessed portion and a second insulation pattern in the recessed portion is formed into a second device isolation pattern on the second area. Accordingly, grain defects in the LEG process and lattice defects in the SEG process are mitigated or eliminated.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: January 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Jong-Wook Lee
  • Publication number: 20120299114
    Abstract: The invention is directed to a semiconductor device which is manufactured by a BiCMOS process in which a process of manufacturing a V-NPN transistor is rationalized. Furthermore, the hFE of the transistor is adjusted to a large value. An N type base width control layer is formed being in contact with a bottom portion of a P type base region under an N+ type emitter region. The N type base width control layer shallows a portion of the P type base region under the N+ type emitter region partially. The P type base region is formed by using a process of forming a P type well region, and the N type base width control layer is formed by using a process of forming an N type well region, thereby achieving the process rationalization.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 29, 2012
    Applicant: Semiconductor Components Industrires, LLC
    Inventor: Seiji OTAKE
  • Patent number: 8318581
    Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: November 27, 2012
    Assignee: Infineon Technologies AG
    Inventors: Karl-Heinz Mueller, Bernhard Winkler, Robert Gruenberger
  • Patent number: 8319290
    Abstract: High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: November 27, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Thomas E. Grebs
  • Patent number: 8278710
    Abstract: An LDMOSFET transistor (100) is provided which includes a substrate (101), an epitaxial drift region (104) in which a drain region (116) is formed, a first well region (107) in which a source region (112) is formed, a gate electrode (120) formed adjacent to the source region (112) to define a first channel region (14), and a grounded substrate injection suppression guard structure that includes a patterned buried layer (102) in ohmic contact with an isolation well region (103) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region (107) and from the drain region (116), where the buried layer (102) is disposed below the first well region (107) but not below the drain region (116).
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: October 2, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vishnu K. Khemka, Stephen J. Cosentino, Tahir A. Khan, Adolfo C. Reyes, Ronghua Zhu
  • Patent number: 8273620
    Abstract: Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: September 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-bum Kim, Young-pil Kim, Si-young Choi, Byeong-chan Lee, Jong-wook Lee