Isolation By Pn Junction Only Patents (Class 438/208)
  • Patent number: 9087761
    Abstract: A solid-state imaging device includes a plurality of pixels formed on a semiconductor substrate and include a photoelectric conversion unit; a color filter on the pixels; an on-chip microlens made of an organic film on the color filter, corresponding to each of the pixels; a first inorganic film formed on a surface of the on-chip microlens and having a higher refraction index than the on-chip microlens; and a second inorganic film formed on a surface of the first inorganic film and having a lower refraction index than the on-chip microlens and the first inorganic film, in which at least the second inorganic film includes a non-lens area at an interface of an adjacent second inorganic film.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: July 21, 2015
    Assignee: SONY CORPORATION
    Inventors: Yoichi Otsuka, Akiko Ogino, Kiyotaka Tabuchi, Takamasa Tanikuni
  • Patent number: 9048096
    Abstract: The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: June 2, 2015
    Assignee: Infineon Technologies AG
    Inventors: Jens Schneider, Klaus Roeschlau, Harald Gossner
  • Patent number: 8975637
    Abstract: A thin film diode (100A) includes a semiconductor layer (130) having first, second, and third semiconductor regions, a first insulating layer (122) formed on the semiconductor layer (130), and a second insulating layer (123) formed on the first insulating layer (122). The first semiconductor region (134A) contains an impurity of a first-conductivity type at a first concentration; the second semiconductor region (135A) contains an impurity of a second-conductivity type different from the first conductivity type at a second concentration; and the third semiconductor region (133A) contains the first-conductivity type impurity at a third concentration lower than the first concentration, or contains the second-conductivity type impurity at a third concentration lower than the second concentration. The first semiconductor region (134A) conforms to an aperture pattern in the second insulating layer (123), or the second semiconductor region (135A) conforms to an aperture pattern in the second insulating layer (123).
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: March 10, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Matsukizono, Tomohiro Kimura, Hiroyuki Ogawa
  • Patent number: 8860078
    Abstract: An electronic or electro-optic device includes a p-type semiconductor layer, an n-type semiconductor layer having a region of contact with the p-type semiconductor layer to provide a p-n junction, a first electrical lead in electrical connection with the p-type semiconductor layer, and a second electrical lead in electrical connection with the n-type semiconductor layer. At least one of the p-type and n-type semiconductor layers includes a doped topological-insulator material having an electrically conducting surface, and one of the first and second electrical leads is electrically connected to the electrically conducting surface of the topological-insulator material.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: October 14, 2014
    Assignee: The Johns Hopkins University
    Inventors: Tyrel M. McQueen, Patrick Cottingham, John P. Sheckelton, Kathryn Arpino
  • Patent number: 8828843
    Abstract: A method of manufacturing an isolation structure includes forming a laminate structure on a substrate. A plurality trenches is formed in the laminate structure. Subsequently a pre-processing is effected to form a hydrophilic thin film having oxygen ions on the inner wall of the trenches. Spin-on-dielectric (SOD) materials are filled into the trenches. The hydrophilic think film having oxygen ions changes the surface tension of the inner wall of the trenches and increases SOD material fluidity.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: September 9, 2014
    Assignee: Inotera Memories, Inc.
    Inventors: Yaw-Wen Hu, Jung-Chang Hsieh, Kuen-Shin Huang, Jian-Wei Chen, Ming-Tai Chien
  • Patent number: 8772869
    Abstract: A power semiconductor device includes: a first semiconductor layer; second and third semiconductor layers above and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; and plural fourth semiconductor layers provided on some of immediately upper regions of the third semiconductor layer. An array period of the fourth semiconductor layers is larger than that of the second semiconductor layer. A thickness of part of the gate insulating film in an immediate upper region of a central portion between the fourth semiconductor layers is thicker than a thickness of part of the gate insulating film in an immediate upper region of the fourth semiconductor layers. Sheet impurity concentrations of the second and third semiconductor layers in the central portion are higher than a sheet impurity concentration of the third semiconductor layer in an immediately lower region of the fourth semiconductor layers.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Syotaro Ono
  • Patent number: 8722481
    Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Patent number: 8664741
    Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 8530298
    Abstract: A method of forming an integrated circuit (IC) includes providing a substrate having a topside semiconductor surface, wherein the topside semiconductor surface includes at least one of N+ buried layer regions and P+ buried layer regions. An epitaxial layer is grown on the topside semiconductor surface. Pwells are formed in the epitaxial layer. Nwells are formed in the epitaxial layer. NMOS devices are formed in and over the pwells, and PMOS devices are formed in and over the nwells.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: September 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Richard G. Roybal, Shariq Arshad, Shaoping Tang, James Fred Salzman
  • Patent number: 8481381
    Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: July 9, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Patent number: 8338863
    Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Erik M. Dahlstrom, Qizhi Liu
  • Patent number: 8299532
    Abstract: An ESD protection device structure includes a well having a first conductive type, a first doped region having a second conductive type disposed in the well, a second doped region having the first conductive type, and a third doped region having the second conductive type disposed in the well. The second doped region is disposed within the first doped region so as to form a vertical BJT, and the first doped region, the well and the third doped region forms a lateral BJT, so that pulse voltage that the ESD protection structure can tolerate can be raised.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: October 30, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Tai-Hsiang Lai, Kuei-Chih Fan, Tien-Hao Tang
  • Patent number: 8263472
    Abstract: A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: September 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kerry Bernstein
  • Patent number: 8232156
    Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Erik M. Dahlstrom, Qizhi Liu
  • Patent number: 8232158
    Abstract: An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: July 31, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Kamel Benaissa, Greg C. Baldwin, Vineet Mishra, Ananth Kamath
  • Patent number: 8049278
    Abstract: An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well and the diffusion area has a dopant polarity that is opposite a dopant polarity of the low doped well and the diffusion area. A distance between the low doped well and the diffusion area determines a triggering voltage of the ESD device. A depletion region is formed between the low doped well and the substrate when a reverse bias voltage is applied to the ESD device. A current discharging path is formed between the first contact and the second contact when the depletion region comes in to contact with the diffusion area. The substrate is biased by a connection to the second contact. Alternatively, an additional diffusion area with the same dopant polarity, connected to a third contact, biases the substrate.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: November 1, 2011
    Assignee: Broadcom Corporation
    Inventor: Agnes Neves Woo
  • Patent number: 7998815
    Abstract: Shallow trench isolation methods are disclosed. In a particular embodiment, a method includes implanting oxygen under a bottom surface of a narrow trench of a silicon substrate and performing a high-temperature anneal of the silicon substrate to form a buried oxide layer. The method also includes performing an etch to deepen the narrow trench to reach the buried oxide layer. The method further includes depositing a filling material to form a top filling layer in the narrow trench.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: August 16, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Ming-Chu King
  • Patent number: 7977198
    Abstract: A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: July 12, 2011
    Assignee: Sony Corporation
    Inventors: Koji Onodera, Mitsuhiro Nakamura, Tomoya Nishida
  • Patent number: 7960796
    Abstract: An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration isolation diffusion layer is formed in the silicon substrate so as to surround the buried diffusion layer. An n-type epitaxial layer is formed on the silicon substrate, the buried diffusion layer, and the first high-concentration isolation diffusion layer. A p-type second high-concentration isolation diffusion layer is formed in the epitaxial layer on the first high-concentration isolation diffusion layer. A p-type low-concentration isolation diffusion layer for isolating the epitaxial layer into a plurality of island regions is formed in the epitaxial layer on the second high-concentration isolation diffusion layer.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: June 14, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Satoshi Rittaku
  • Patent number: 7956432
    Abstract: A photodiode includes a substrate having a first semiconductor type surface region on at least a portion thereof, and a second semiconductor type surface layer formed in a portion of the surface region. A multi-layer anti-reflective coating (ARC) is on the second semiconductor type surface layer, wherein the multi-layer ARC comprises at least two different dielectric layers. A layer resistant to oxide etch is above a peripheral portion the multi-layer ARC. Further layers are above the layer resistant to oxide etch, and thereby above the peripheral portion the multi-layer ARC. A window extends down to the multi-layer ARC. A photodiode region is formed by a pn-junction of the first semiconductor type surface region and the second semiconductor type surface layer.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: June 7, 2011
    Assignee: Intersil Americas Inc.
    Inventors: Dong Zheng, Phillip J. Benzel, Joy Jones, Alexander Kalnitsky, Perumal Ratnam
  • Patent number: 7939397
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor pattern which is covered with a first insulating film over a first active region, forming a second semiconductor pattern over a second active region, forming a second insulating film over the first insulating film and the first and second semiconductor patterns, forming an opening whose depth reaches the first semiconductor pattern by etching the second insulating film and the first insulating film, forming sidewalls on side surfaces of the second semiconductor pattern by patterning the second insulating film, forming a metal film over the first and second semiconductor patterns respectively, and forming silicide layers by reacting the first and second semiconductor patterns with the metal film.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: May 10, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Michihiro Onoda, Takayuki Matsumoto
  • Patent number: 7872325
    Abstract: Wirebonds are formed to couple an opto-electronic device chip having two or more opto-electronic devices to a signal processing chip. Two or more mutually adjacent wirebond groups, each corresponding to one of the opto-electronic devices, are formed. For example, each wirebond group can include a first wirebond coupling a P-terminal of the opto-electronic device of the wirebond group to the signal processing chip, a second wirebond coupling an N-terminal of the opto-electronic device of the wirebond group to the signal processing chip, and a third wirebond coupling the opto-electronic device chip to the signal processing chip.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: January 18, 2011
    Assignee: Avago Technologies Fiber IP (Singapore) Pte. Ltd.
    Inventors: Peter Ho, Michael A. Robinson, Zuowei Shen
  • Patent number: 7719080
    Abstract: A semiconductor device includes a drift layer of a first conductivity type having a doping concentration and a conduction layer also of the first conductivity type on the drift layer that has a doping concentration greater than the doping concentration of the drift layer. The device also includes a pair of trench structures, each including a trench contact at one end and a region of a second conductivity type opposite the first conductivity type, at another end. Each trench structure extends into and terminates within the conduction layer such that the second-conductivity-type region is within the conduction layer. A first contact structure is on the drift layer opposite the conduction layer while a second contact structure is on the conduction layer.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: May 18, 2010
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventor: Qingchun Zhang
  • Patent number: 7642154
    Abstract: A biCMOS device including a bipolar transistor and a Polysilicon/Insulator/Polysilicon (PIP) capacitor is disclosed. A biCMOS device may have a relatively low series resistance at a bipolar transistor. A bipolar transistor may have a desirable amplification rate.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: January 5, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Kwang Young Ko
  • Patent number: 7638385
    Abstract: A method of forming a semiconductor device includes forming isolation trenches that are used to isolate some of the electrical elements such as transistors, diodes, capacitors, or resistors on a semiconductor die from other elements on the semiconductor die.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: December 29, 2009
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, Peter J. Zdebel, Diann Dow
  • Patent number: 7485486
    Abstract: A method of a fabricating a multiple wavelength adapted photodiode and resulting photodiode includes the steps of providing a substrate having a first semiconductor type surface region on at least a portion thereof, implanting and forming a second semiconductor type shallow surface layer into the surface region, and forming a multi-layer anti-reflective coating (ARC) on the shallow surface layer. The forming step includes depositing or forming a thin oxide layer on the shallow surface layer and depositing a second dielectric layer different from the thin oxide layer on the thin oxide layer. An etch stop is formed on the second dielectric, wherein the etch stop includes at least one layer resistant to oxide etch. At least one oxide including layer (e.g. ILD) is then deposited on the etch stop. The oxide including layer and etch stop are then removed to expose at least a portion of the ARC to the ambient.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: February 3, 2009
    Assignee: Intersil Americas Inc.
    Inventors: Dong Zheng, Phillip J. Benzel, Joy Jones, Alexander Kalnitsky, Perumal Ratman
  • Patent number: 7462530
    Abstract: An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration isolation diffusion layer is formed in the silicon substrate so as to surround the buried diffusion layer. An n-type epitaxial layer is formed on the silicon substrate, the buried diffusion layer, and the first high-concentration isolation diffusion layer. A p-type second high-concentration isolation diffusion layer is formed in the epitaxial layer on the first high-concentration isolation diffusion layer. A p-type low-concentration isolation diffusion layer for isolating the epitaxial layer into a plurality of island regions is formed in the epitaxial layer on the second high-concentration isolation diffusion layer.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: December 9, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Satoshi Rittaku
  • Patent number: 7173316
    Abstract: An N type semiconductor layer is epitaxially grown on a P type semiconductor substrate of which one end is grounded, and an element isolation layer made of a P type diffusion layer is formed by means of diffusion around the N type semiconductor layer in order to electrically isolate the N type semiconductor layer. The metal layer which is located above the N type semiconductor layer and which forms a wire or a bonding pad is isolated from the N type semiconductor layer in which a diffusion layer or the like has been formed by an insulating film. An N type buried diffusion layer having an impurity concentration higher than that of the N type semiconductor layer is provided between the P type semiconductor substrate and the N type semiconductor layer. In addition, a P type semiconductor layer is formed by means of diffusion between the insulating film and the N type semiconductor layer plus the element isolation layer.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: February 6, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yuichi Tateyama
  • Patent number: 7015084
    Abstract: A gate-overlap-drain structure is obtained by a single pair of a single impurity implantation process and a single laser anneal process, wherein the improved gate-overlap-drain structure includes lightly activated high impurity concentration regions exhibiting substantially the same function as the lightly doped drain regions, wherein the lightly activated high impurity concentration regions are bounded with high impurity concentration regions serving as source and drain regions. The boundaries are self-aligned to edges of a gate electrode. Side regions of the gate electrode overlap the lightly activated high impurity concentration regions.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: March 21, 2006
    Assignee: NEC Corporation
    Inventor: Kenji Sera
  • Patent number: 6974999
    Abstract: It is an object to suppress a change in a characteristic of a semiconductor device with a removal of a hard mask while making the most of an advantage of a gate electrode formed by using the hard mask. A gate electrode (3) is formed by etching using a hard mask as a mask and the hard mask remains on an upper surface of the gate electrode (3) at a subsequent step. In the meantime, the upper surface of the gate electrode (3) can be therefore prevented from being unnecessarily etched. The hard mask is removed after ion implantation for forming a source-drain region. Consequently, the influence of the removal of the hard mask on a characteristic of a semiconductor device can be suppressed. In that case, moreover, a surface of a side wall (4) is also etched by a thickness of (d) so that an exposure width of an upper surface of the source-drain region is increased. After the removal of the hard mask, it is easy to salicide the gate electrode (3) and to form a contact on the gate electrode (3).
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: December 13, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Tsuyoshi Sugihara
  • Patent number: 6943072
    Abstract: An method and apparatus for high voltage control of isolation region transistors (320) in an integrated circuit. Isolation region transistors (320) are formed between active devices by selective implantation of channel stop implants (140). Isolation region transistors (320) are those areas with a conductor (130) over an isolation region (120) with no channel stop implant (140). This provides an isolation region transistor (320) with a lower threshold voltage than the areas with channel stop implant (140). The voltage threshold of the isolation region transistors 320 are adjustable to a range of voltages by varying the length of channel stop implant (140). The apparatus may be fabricated using conventional fabrication processes.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: September 13, 2005
    Assignee: Altera Corporation
    Inventor: Dominik J. Schmidt
  • Patent number: 6841437
    Abstract: A method of forming medium breakdown voltage vertical transistors (11) and lateral transistors (12, 13) on the same substrate (14) provides for optimizing the epitaxial layer (16) for the lateral transistors (12, 13). The vertical transistor (11) is formed in a well (18) that has a lower resistivity than the epitaxial layer (16) to provide the required low on-resistance for the vertical power transistor (11).
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: January 11, 2005
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Stephen P. Robb
  • Publication number: 20040232512
    Abstract: In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.
    Type: Application
    Filed: June 24, 2004
    Publication date: November 25, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Eiji Hasunuma, Hideki Genjo, Shigeru Shiratake, Atsushi Hachisuka, Koji Taniguchi
  • Patent number: 6787880
    Abstract: A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions over the doped regions. The invention has two types of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) undoped or lightly doped regions (e.g., channel regions). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n−well (n minus well) can be formed under the collector. The high resistivity regions increase the collector resistivity thereby improving the performance of the parasitic bipolar ESD device.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: September 7, 2004
    Assignee: Nano Silicon Pte. Ltd.
    Inventors: David Hu, Jun Cai
  • Patent number: 6784043
    Abstract: An integrated circuit includes a first conductive layer, an insulator layer disposed on the first conductive layer, and a second conductive layer disposed on the insulator layer. A first fuse is disposed in the first conductive layer and provides a first signal, and a second fuse is disposed in the second conductive layer in alignment with the first fuse and provides a second signal.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Bryan C. Carson, Mark L. Hadzor, Lucien J. Bissey
  • Patent number: 6781206
    Abstract: Isolation regions, a peripheral anode, an N-type island region for output and a passive N-type island region are formed at the main surface of a P− substrate. A dummy N-type island region is formed at a region located between two isolation regions. A P-type region is formed at the surface of this N well. A pair of N++ type regions are formed at the surface of P-type region. A gate electrode is formed on a portion of P-type region interposed between N++ type regions. N++ type region is connected to ground while N++ type region is electrically connected to isolation region. Accordingly, current is restricted from flowing between the N-type island region for output and the passive N-type island region so as to obtain a semiconductor device in which occurrence of malfunctions is prevented.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: August 24, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Akio Uenishi
  • Publication number: 20040140520
    Abstract: A double gate MOS transistor includes a substrate active region defined in a semiconductor substrate and a transistor active region located over the substrate active region and overlapped with the substrate active region. At least one semiconductor pillar penetrates the transistor active region and is in contact with the substrate active region. The semiconductor pillar supports the transistor active region so that the transistor active region is spaced apart from the substrate active region. At least one bottom gate electrode fills a space between the transistor active region and the substrate active region. The bottom gate electrode is insulated from the substrate active region, the transistor active region and the semiconductor pillar. At least one top gate electrode crosses over the transistor active region and has at least one end that is in contact with a sidewall of the bottom gate electrode.
    Type: Application
    Filed: November 18, 2003
    Publication date: July 22, 2004
    Inventors: Sung-Min Kim, Dong-Gun Park, Chang-Sub Lee, Jeong-Dong Choe, Shin-Ae Lee, Seong-Ho Kim
  • Publication number: 20040113228
    Abstract: A convex polycrystalline silicon film is formed on a handle wafer. A semiconductor layer is formed on the polycrystalline silicon film. The semiconductor is thinner on its areas in which the convex polycrystalline silicon film is formed and is thicker on its areas in which the convex polycrystalline silicon film is not formed. An opening is formed in each of those areas of an insulating film which are located under respective thick-film semiconductor areas of the semiconductor layer. The polycrystalline silicon film is formed in the openings to connect electrically the thick-film semiconductor areas and the handle wafer together.
    Type: Application
    Filed: September 3, 2003
    Publication date: June 17, 2004
    Inventors: Takashi Yamada, Atsushi Azuma, Yoshihiro Minami, Hajime Nagano, Hiroaki Yamada, Tatsuya Ohguro, Kenji Kojima, Kazumi Inoh
  • Publication number: 20030218232
    Abstract: A method of forming isolation structures in semiconductor substrates comprising exposing a region of the semiconductor simultaneously to a transforming agent and to a viscosity reducing agent so that the transforming agent transforms a portion of the substrate into an isolation structure and the viscosity reducing agent reduces the viscosity of the isolation structure during formation. In one embodiment, a silicon substrate is exposed to oxygen in the presence of fluorine so that a silicon oxide isolation region is formed. The fluorine reduces the viscosity of the silicon oxide isolation region during formation which results in less lateral, bird's beak encroachment under adjacent masking stacks and also results in lower internal stress in the isolation region during formation. The lower internal stress and the lessened lateral encroachment result in thicker and improved isolation regions.
    Type: Application
    Filed: June 12, 2003
    Publication date: November 27, 2003
    Inventors: Viju K. Mathews, Nanseng Jeng, Pierre C. Fazan
  • Patent number: 6653182
    Abstract: Prior fabricating the transistors, a phase of forming a deep insulative trench in the substrate is followed by a phase of forming a shallow insulative trench in the substrate and extending the deep trench. The phase of forming the deep trench includes coating the inside walls of the deep trench with an initial oxide layer and filling the deep trench with silicon inside an envelope formed from an insulative material. The phase of forming the shallow trench includes coating the inside walls of the shallow trench with an initial oxide layer and filling the shallow trench with an insulative material.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: November 25, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Michel Marty, Hélène Baudry, François Leverd
  • Patent number: 6630377
    Abstract: An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reachthrough) and the P wells are used to form the base. N doped third wells are formed under the N wells, P wells, and shallow trench isolation regions to provide subcollectors. Since the P wells are not implanted through the STI, basewidths are reduced and current gain is increased. Gate electrode masking elements, formed over the base, separate the emitter and base contact regions, improving the emitter-to-base breakdown voltage. The CMOS source/drain N type implants then form emitters in the emitter regions and ohmic contacts in the collector contacts. The source/drain P type implants form the ohmic base contacts to complete the bipolar transistor.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: October 7, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Shesh Mani Panday, Alan Shafi, Yong Ju
  • Publication number: 20030183899
    Abstract: A semiconductor component includes a semiconductor substrate (310) having a first conductivity type, a first semiconductor device (320) at least in a first portion of the semiconductor substrate, and a second semiconductor device (330, 310) at least in a second portion of the semiconductor substrate. The first semiconductor device includes a first electrode region (321), a second electrode region (322), a body region (323), and an isolation region (324) in the first portion of the semiconductor substrate. The body region has the first conductivity type, and the first electrode region, the second electrode region, and the isolation region have a second conductivity type. The second electrode region has a different doping concentration than the first electrode region, and the body region is isolated from the second portion of the semiconductor substrate by the isolation region and the first electrode region.
    Type: Application
    Filed: April 1, 2002
    Publication date: October 2, 2003
    Applicant: Motorola, Inc.
    Inventors: Edouard de Fresart, Patrice Parris, Pak Tam
  • Patent number: 6624497
    Abstract: An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: September 23, 2003
    Assignee: Intersil Americas, Inc
    Inventor: James D. Beasom
  • Patent number: 6589833
    Abstract: A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions over the doped regions. The invention has two types of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) undoped or lightly doped regions (e.g., channel regions). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n−well (n minus well) can be formed under the collector. The high resistivity regions increase the collector resistivity thereby improving the performance of the parasitic bipolar ESD device.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: July 8, 2003
    Assignee: Nano Silicon Pte Ltd.
    Inventors: David Hu, Jun Cai
  • Patent number: 6582997
    Abstract: Disclosed are structures and a method to increase the power dissipation of an output pad of an integrated circuit during electrostatic discharge (ESD) by preventing ESD current from flowing through resistive means between that output pad and an internal circuit. By splitting the active region and thereby creating a bipolar transistor which connects directly to the output pad, the resistive means is shunted when the bipolar transistor together with an already existing parasitic bipolar transistor conduct during ESD. Current flow in the resistive means is therefore eliminated and with it damaging power dissipation.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: June 24, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jian-Hsing Lee, Shui-Hun Chen, Jiaw-Ren Shih
  • Publication number: 20030085442
    Abstract: An integrated circuit is described having a substrate, a power transistor in a first region of the substrate, and a plurality of barrier regions of the substrate around the first region. Each barrier region includes a barrier transistor and at least one substrate connection connecting the barrier transistor to at least one floating region of the substrate adjacent the barrier region. During operation of the integrated circuit, the floating regions and the barrier transistors operate to inhibit operation of parasitic devices associated with the power transistor.
    Type: Application
    Filed: July 2, 2002
    Publication date: May 8, 2003
    Applicant: Tripath Technology Inc.
    Inventors: Sorin Stefan Georgescu, Carl Sawtell
  • Publication number: 20030062587
    Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.
    Type: Application
    Filed: November 7, 2002
    Publication date: April 3, 2003
    Applicant: Sanyo Electric Co., Ltd., a Japan corporation
    Inventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen
  • Patent number: 6541325
    Abstract: The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: April 1, 2003
    Assignee: Windbond Electronics Corporation
    Inventors: Chih-Mu Huang, Chuan-Jane Chao, Chi-Hung Kao
  • Publication number: 20030040144
    Abstract: A merged device is that comprises a plurality of MOSFET cells and a plurality of Schottky rectifier cells, as well as a method of designing and making the same. According to an embodiment of the invention, the MOSFET cells comprise: (a) a source region of first conductivity type formed within an upper portion of a semiconductor region, (b) a body region of second conductivity type formed within a middle portion of the semiconductor region, (c) a drain region of first conductivity type formed within a lower portion of the semiconductor region, and (d) a gate region provided adjacent the source region, the body region, and the drain region. The Schottky diode cells in this embodiment are disposed within a trench network and comprise a conductor portion in Schottky rectifying contact with the lower portion of the semiconductor region. At least one MOSFET cell gate region is positioned along a sidewall of the trench network and adjacent at least one Schottky diode cell in this embodiment.
    Type: Application
    Filed: August 23, 2001
    Publication date: February 27, 2003
    Inventors: Richard A. Blanchard, Fwu-Iuan Hshieh, Koon Chong So
  • Patent number: RE41477
    Abstract: An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: August 10, 2010
    Inventor: James D. Beasom