Abstract: Integrated circuit memory devices include a memory cell field effect transistor in an integrated circuit substrate, a conductive plug that electrically contacts the memory cell field effect transistor and a titanium nitride bit line that electrically contacts the conductive plug opposite the memory cell filed effect transistor. Titanium nitride also may be used to electrically contact field effect transistors in the peripheral region of the integrated circuit memory device. Titanium nitride can be used as a bit line metal instead of conventional tungsten, and as a conductive plug to contact both p+-type and n+-type source/drain regions in the peripheral region of the memory device. The titanium nitride conductive plugs and bit lines may be formed simultaneously.

Abstract: On a main surface of a p-type silicon substrate having a bipolar transistor forming region and a MOS transistor forming region, an epitaxial layer is grown and n-type buried layers are formed. After forming a trench penetrating the buried layer, a buried polysilicon layer is formed in the trench. Then, a threshold control layer, a punch-through stopper layer, a channel stopper layer, an n-type well layer and a p-type well layer of each MOSFET are formed. At this point, since the well layer is formed through high energy ion implantation, the n-type buried layer is suppressed from being enlarged, and hence, time required for forming the trench can be shortened. Thus, a practical method of manufacturing a semiconductor device is provided.

Abstract: A method of manufacturing a semiconductor device is provided in which a semiconductor device including a plurality of FETs having different threshold voltages and gate insulating films with different film thicknesses can be manufactured in a simplified process. Specifically, a first gate insulating film is formed on the main surface of a semiconductor substrate. On the first gate insulating film, a first protection film is formed. In regions A and B in each of which an FET having a second gate insulating film with a film thickness different from that of the first gate insulating film is to be formed, the first gate insulating film and the first protection film are removed to expose the surface of the semiconductor substrate. At the same time, the first protection film is left in regions other than the regions A and B. Using the first protection film as a mask, an impurity is implanted into the semiconductor substrate in the regions A and B.

Abstract: A method for producing a bipolar transistor and an MOS transistor of the present invention includes the steps of: forming a first insulation film in an MOS transistor region where the MOS transistor is to be formed and in a bipolar transistor region where the bipolar transistor is to be formed; forming a first conductive film and a second insulation film on the first insulation film; and removing the second insulation film, the first conductive film and the first insulation film from the bipolar transistor region.

Abstract: A method for fabricating a CMOS image sensor resolves the abnormally elevated output at the first pixel without degrading the integration of the device. The method of the invention lengthens the field oxide layer within the scribe-line region to ensure the substrate and the conducting layer thereon are properly insulated. That prevents the leakage of the carriers generated by the Electro-optical effect to resolve the problem of an abnormally elevated output at the first pixel. In addition, a mask protects the dielectric layer on the scribe-line region from being etched, so the steep difference on the step height is improved to resolve the peeling of the photoresist. The field oxide layer under the dielectric layer covered by the dielectric layer then provides a better insulation.

Abstract: An improved method for simultaneously forming low voltage and high voltage devices is disclosed. The method includes using gradient doping to generate the gradient concentration in a semiconductor such that can tolerate higher threshold voltage. The device can get higher driving current by using gradient doping only in drain regions in metal-oxide-semiconductor field effect transistor (MOSFET). In addition, the invention can simultaneously generate higher current gain bipolar junction transistor (BJT) for applied integrated circuit. Further more, the invention can meet small layout rule of low voltage device and the only drain region to be operated in a high voltage device.

Abstract: The semiconductor device and method of manufacturing the same according to the present invention has an object of reducing hem-pulling at a side wall of an isolation trench caused at an open space of a device isolation region having a well boundary at its bottom portion thereby to prevent structurally occurrence of punch-through. In an insulator filled device isolation method, an isolation trench for device isolation is formed by dry etching. If a second isolation trench intersects an intermediate portion of a first isolation like a T-shape, one side of the first isolation trench has an open space. In this case, the inclination angle of the side wall of the first isolation trench, opposed to the open space, is loosened and the side wall forms a shape whose hem is pulled out on the bottom portion. In this case if a well boundary exists along the lengthwise direction at the bottom of the first isolation trench, the structure tends to cause punch-through easily.

Abstract: A method of forming a complementary metal-oxide-semiconductor (CMOS) integrated circuit, and the integrated circuit so formed, are disclosed. After the formation of a p-type well (4) and an n-type well (6) into which the transistors are to be formed; and gate structures (8n, 8p) overlying the surfaces of these wells (4, 6), a doped insulating layer (20) is formed overall, for example by way of chemical vapor deposition. The doped insulating layer (20) is, according to the preferred embodiment of the invention, silicon dioxide that is doped with boron. In the preferred embodiment of the invention, the portion of the doped insulating layer (20) overlying the p-type well (4) is removed, and ion implantation of n-type dopant is then performed. The remaining portion of the doped insulating layer (20) protects the n-type well (6) from the n-type ion implantation steps.

Abstract: In a Bi-CMOS integrated circuit device, to reduce a collector-substrate junction capacitance in an NPN transistor and to reduce the step of forming an anti-punch-through layer of the N-channel MOS transistor. Using as a mask a resist pattern having windows made on an element isolation LOCOS film 113a, 113c and P-type well layer 106, impurities are ion-implanted to form a channel stopper layer 115a, 115b for element isolation of a NPN transistor and an anti-punch-through layer 115c for a N-channel MOS transistor. Thus, a sufficient element isolation withstand voltage can be assured while avoiding an increase in the collector-substrate capacitance of the NPN transistor which is due to the transverse diffusion of the channel stopper layer when an epitaxial layer, well layer and LOCOS film are formed. In addition, without increasing the number of steps, the drain-source withstand voltage of the N-channel type MOS transistor and the short channel durability can be improved.

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a dielectric layer (24) to provide electrical isolation. The semiconductor device (10) includes a drain extension region (101) that extend from a drain region (44) to a gate structure (20). The semiconductor device (10) also has a conductive structure (105) that is adjacent to the gate structure (20).

Abstract: In a trench isolation structure having active regions at a main surface of a silicon substrate isolated by providing a gate electrode on an insulation film formed in a trench with a gate oxide film thereunder, the insulation film has a vertical cross section configuration wherein the carrier concentration of the active region at the proximity of the upper edge corner of the trench becomes lower than the carrier concentration at the center of the active region in a state where a predetermined bias voltage is applied to the gate electrode. According to this structure, electric field concentration at the edge of the trench isolation can be relaxed and generation of an inverse narrow channel effect suppressed. Therefore, the subthreshold characteristics can be improved.

Abstract: A method of forming, on an ultra-thin SOI substrate, an ESD protected device, includes: preparing a single crystal silicon substrate, including forming insulated areas thereon and forming selectively conductive areas thereon; doping the selectively conductive layers with dopants; growing, epitaxially, silicon layers over selected insulated areas and the doped, selectively conductive areas; heating the substrate and the structures formed thereon at between about 850.degree. C. to 1150.degree. C. for between about 30 minutes to three hours to redistribute the dopant into the epitaxially grown silicon layer; completing the fabrication of additional layers in the structure; and metallizing the structure.

Abstract: A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of adjacent bitlines may be isolated from each other without increasing the cell size and allowing a minimum area of approximately 4 F.sup.2 to be maintained. The array is suitable for Gbit DRAM applications because the stack capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof.

Abstract: A densely packed array of vertical semiconductor devices and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, acting as a channel, formed between source and drain regions. The source regions are self-aligned and located below the pillars. The source regions of adjacent bitlines are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F.sup.2 to be maintained. The isolated sources allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. The source may be initially implanted. Alternatively, the source may be diffused below the pillars after forming thereof.

Abstract: There are formed simultaneously a first conductive layer selectively on a region of a semiconductor substrate in which an N-channel MOS transistor is to be formed and on a region of the semiconductor in which a p-channel MOS transistor is to be formed, a second conductive layer on a region of the semiconductor substrate in which a capacitive element is to be formed, and a third conductive layer on a region of the semiconductor substrate in which the resistive element is to be formed. Next, there are formed simultaneously a first insulating film on the lateral side of the first conductive layer, a second insulating film selectively on the second conductive layer, and a third insulating film selectively on the third conductive layer. Then the fourth insulating film is formed on the whole surface.

Abstract: The present invention relates to a method of forming deep trenches in a BICMOS-type integrated circuit wherein the formation of a bipolar transistor includes the steps of depositing a base polysilicon layer, depositing a protection oxide layer, forming an emitter-base opening, and etching the silicon oxide protection layer and the base polysilicon layer outside the bipolar transistor areas. The formation of the trenches includes the steps of opening the protection oxide and base polysilicon layers above a thick oxide region while the emitter-base opening is being made, etching the thick oxide layer while the protection oxide layer is being etched, and etching the silicon under the thick oxide while the base polysilicon is being etched.

Abstract: An improved bipolar transistor of BiCMOS is provided to improve the breakdown voltage between a collector and a base. A low concentration diffusion layer is provided at a main surface of a semiconductor substrate at a boundary between an outer perimeter of an external base layer and an end portion of a field oxide film. The low concentration diffusion layer expands from the main surface of the semiconductor substrate toward the inside of the substrate and has a concentration lower than the impurity concentration of the external base layer.

Abstract: The present invention is to provide a semiconductor integrated circuit having bipolar transistor elements with a reduced isolating distance between adjacent transistors and a reduced collector/substrate capacitance. In the surface of a P-type semiconductor substrate, N.sup.+ type regions are formed serving as buried collector regions of bipolar transistors TR1 and TR2. Between the N.sup.+ type regions, a P-type region for element isolation is provided not in contact with the N.sup.+ type regions. A P-type impurity concentration in the peripheral portions of N.sup.+ type regions is equal to that of the semiconductor substrate. The insulating film serving as an element-isolating layer is provided on the P-type region in contact therewith and thus electrically isolates adjacent bipolar transistors.

Abstract: A complementary metal oxide (CMOS) integrated circuit configured for reducing the formation of silicon defects in its silicon substrate during manufacture. The silicon defects are formed from silicon interstitials present in the silicon substrate. The CMOS integrated circuit includes a deep implantation region formed within the silicon substrate. There is further included at least one vertical trench formed in the silicon substrate. The trench is formed such that at least a portion of the trench penetrates into the deep implantation region of the silicon substrate to present vertical surfaces within the deep implantation region, thereby allowing the silicon interstitials to recombine at the vertical surfaces.

Abstract: The present application provides a CMOS device and process in which the source/drain regions are polysilicon, and are dielectrically isolated from the well regions. This structure can be obtained, for example, by depositing the first layer of polysilicon under very high temperature conditions (essentially the same as those normally used for epitaxial deposition), so that the first polysilicon layer is formed epitaxially (as monocrystalline silicon) over exposed regions, and as polycrystalline material over oxide. An oxide is grown on the surface of the deposited layer, and a second polysilicon layer is then deposited, under normal conditions, to form the gate layer. After the second polysilicon layer has been patterned, source/drain implants are then made into the first (intrinsic) polysilicon layer to form source/drain implants. Thus, the first polysilicon layer will contain both N+ and P+ regions, and if desired, may also include intrinsic regions.

Abstract: A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

Abstract: A method of manufacturing a semiconductor device including selectively forming an element-isolating insulating layer on a surface of a semiconductor substrate to define active regions; forming a first insulating layer and removing respective portions thereof on surfaces of a second conductive type active region and a first active region of a first conductive type; oxidizing to form a gate oxide layer; forming and patterning a conductive layer to form a gate electrodes of MOS transistors and a base-extracting electrode of a bipolar transistor; forming an opening, in the base-extracting electrode, and a side wall insulating layer on an inner wall of the opening; removing first and second portions of the insulating layer to form an overhung portion; epitaxially growing a second conductive type semiconductor layer using the base-extracting electrode and active region of the first conductive type as a seed crystal; and selectively forming a first conductive type semiconductor layer that is to become an emitter tha

Abstract: An N-channel JFET (60) and a method of forming the N-channel JFET (60) in a BiCMOS process. The N-channel JFET (60) is monolithically fabricated with an N-channel IGFET (70), a P-channel IGFET (75), and an NPN BJT (80) in an epitaxial layer (21). The N-channel JFET (60) is formed in an isolated N-channel JFET region (24), the P-channel IGFET (75) is formed in an isolated P-channel IGFET region (27), and the NPN BJT (80) is formed in an isolated BJT region (29). The N-channel IGFET (70) is fabricated in a P-type well (26) that is not isolated from other N-channel IGFET's in the epitaxial layer (21). Accordingly, the N-channel JFET (60), the N-channel IGFET (70), the P-channel IGFET (75), and an NPN BJT (80) are monolithically formed in the BiCMOS process.

Abstract: It is the object of the invention to provide a method for fabricating a semiconductor device, such as a bipolar transistor, with improved characteristics when used in a semiconductor integrated circuit, without increasing the steps in fabricating process. In forming the graft base of the bipolar transistor, oxygen ions with higher energy than that of impurities are injected through the same mask. Thereafter, an insulating film is formed under the graft base region, by activating thermal treatment. Moreover, in a semiconductor integrated circuit of BiCMOS type, insulation films are formed under a source and a drain of a P-type transistor.