Semiconductor device with a reduced mask count buried layer
An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.
Related to a corresponding application entitled Reduced Mask Count Buried Layer Process
BACKGROUND OF THE INVENTION1. Field of the Invention
This invention relates to semiconductor devices and its manufacturing method, and, more specifically, to the formation of buried layers in such devices.
2. Description of Related Art
It is well known in semiconductor processing that the minimization of the number of masking operations in fabricating a semiconductor device is a constant goal. Thus processes which can eliminate a masking operation are highly desirable in the semiconductor processing art.
Fabrication of complementary vertical bipolar devices for analog signal processing on a single integrated circuit with N type and P type buried layers are known in the art. For example, Rupit Patel et al, “a 30 V Complementary Bipolar Technology on SOI for High Speed Precision Analog Circuits,” IEEE BCTM, pp. 48-50, 1997, and M. C. Wilson et cl, “Process HJ: A 30 GHz NPN and 20 GHz PNP Complementary Bipolar Process for High Linearity RF Circuits,” IEEE BCTM, pp. 164-167, 1998, describe examples of these types of circuits. In both publications the circuits taught use both N type and P type buried layers which are formed using separate mask and implant steps to form each buried layer. This requires two masks and two implants to form the two buried layers.
BRIEF SUMMARY OF THE INVENTIONIt is therefore an object of this invention to provide a semiconductor processing method which provides a non selective N buried layer without requiring a masking operation, together with a selective P type buried layer which is formed using a mask. It is also an object of this invention to provide a semiconductor device with a non selective N type buried layer and a selective P type buried layer.
According to the invention, there is provided a semiconductor process wherein a non selective N type buried layer and a selective P type buried layer are formed on a an semiconductor device, the dopant used as the N type buried layer dopant having a lower diffusion coefficient than the dopant used as the P type buried layer dopant.
According to the invention, there is further provided a semiconductor device having a non selective N type buried layer and a selective P type buried layer formed on a semiconductor device, the N type majority dopant present in the N type buried layer dopant having a lower diffusion coefficient than the P type majority dopant present in the P type buried layer dopant.
The aforementioned and other features, characteristics, advantages, and the invention in general will be better understood from the following more detailed description taken in conjunction with the accompanying drawings, in which:
It will be appreciated that for purposes of clarity and where deemed appropriate, reference numerals have been repeated in the figures to indicate corresponding features, and that the various elements in the drawings have not necessarily been drawn to scale in order to better show the features of the invention.
DETAILED DESCRIPTION OF THE INVENTIONTurning now to the drawings, all of which are diagrammatical fragmentary cross sections of a portion of a structure used in the fabrication of an integrated circuit,
As used herein the term “buried layer” refers to a conduction region in a silicon wafer as that term is known in the art for a completed device, and also, during processing of the device, to certain regions which may be located on the surface and elsewhere in a wafer which will become buried layers in a completed device.
There are alternative methods of controlling the doping level in the N+ buried layer 20. A first alternative is to form the non selective N+ SOI layer 16 directly by epitaxial growth without an N+ implant. In a second alternative, which is one preferred embodiment as depicted in
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Advantageously the dopant in P+ buried layer 36 is selected to have a higher diffusion coefficient than the N+ dopant in the N+ buried layer 20 so that the P+ buried layer 36 will out diffuse further into the overlaying N− epi layer 28 to connect with the P well 38 to form a P type buried layer at the bottom of the P well 38. If the dopant forming the N+ buried layer 20 had a higher diffusion coefficient than the dopant forming the P+ buried layer 36, the N+ buried layer 20 would extend above the P+ buried layer 36, and the P well 38 would have to have a high enough dose concentration to over compensate the N+ buried layer 20 in order to make a connection with the P+ buried layer 36. If the P well 38 is the collector of a PNP transistor used, for example, for analog signal processing, then the N+ buried layer 20 would not be over compensated since the dopant concentration in the collector of such a transistor is several orders of magnitude less than the heavy doping generally used to form an N+ buried layer. While there are relatively slow and fast diffusing N type dopants, there is no slow diffusing P type dopant presently being used in silicon semiconductor manufacturing. Thus, with the dopants commonly used in semiconductor manufacturing, a non selective P+ buried layer cannot practically be used with a selective N+ buried layer in silicon.
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In the above description the non selective N+ buried layer is formed before the selective P+ buried layer. The selective layer may be formed before the non selective layer as shown in
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Although the invention has been described in part by making detailed reference to a certain specific embodiment, such detail is intended to be, and will be understood to be, instructional rather than restrictive. It will be appreciated by those skilled in the art that many variations may be made on the structure and mode of operation without departing from the spirit and scope of the invention as disclosed in the teachings contained herein.
Claims
1. A semiconductor device comprising:
- a) an oxide layer;
- b) a non selective N type buried layer of an N type dopant with a first coefficient of diffusion covering the oxide layer;
- c) a selective P type buried layer of a P type dopant with a coefficient of diffusion greater than said first coefficient of diffusion located over selective regions of the oxide layer; and
- d) an N type layer extending over said non selective N type buried layer and said selective P type buried layer, the N type layer having a doping concentration less than the doping concentration of the non selective N type buried layer.
2. The semiconductor device set forth in claim 1 wherein said P type buried layer over compensates completely through said N type buried layer in places where said P type buried layer is formed.
3. The semiconductor device set forth in claim 1 wherein said P type buried layer does not over compensate completely through the thickness of said N type buried layer.
4. The semiconductor device set forth in claim 1 wherein a majority dopant in said N type buried layer is one of arsenic or antimony and a majority dopant in said P type buried layer is boron.
5. The semiconductor device set forth in claim 1 wherein a maximum concentration of an N type majority dopant of said N type buried layer is less than a maximum concentration of a P type majority dopant of said P type buried layer.
6. The semiconductor device set forth in claim 1 further including:
- a P well extending from said P type buried layer through said N type layer.
7. The semiconductor device set forth in claim 6 wherein an N type majority dopant in said N type buried layer has a maximum concentration greater than the maximum concentration of a P type majority dopant in said P well.
8. A semiconductor device comprising:
- a) an oxide layer;
- b) an N type buried layer located over the oxide layer;
- c) a P type buried layer;
- d) wherein said N type buried layer is non selective and is located over selective regions of the oxide layer;
- e) wherein said N type buried layer comprises a majority N type dopant having a first coefficient of diffusion;
- f) wherein said P type buried layer is selective;
- g) wherein said P type buried layer comprises a majority P type dopant having a coefficient of diffusion greater than said first coefficient of diffusion; and
- h) an N type layer extending over said non selective N type buried layer and said selective P type buried layer, the N type layer having a doping concentration less than the doping concentration of the non selective N type buried layer.
9. The semiconductor device set forth in claim 8 wherein said P type buried layer over compensates completely through said N type buried layer is places where said P type buried layer is formed.
10. The semiconductor device set forth in claim 8 wherein said P type buried layer does not over compensate completely through the thickness of said N type buried layer.
11. The semiconductor device set forth in claim 8 wherein a majority dopant in said N type buried layer is one of arsenic or antimony and a majority dopant in said P type buried layer is boron.
12. The semiconductor device set forth in claim 8 wherein a maximum concentration of an N type majority dopant of said N type buried layer is less than a maximum concentration of a P type majority dopant of said P type buried layer.
13. The semiconductor device set forth in claim 8 further including:
- a P well extending from said P type buried layer through said N type layer.
14. The semiconductor device set forth in claim 13 wherein an N type majority dopant in said N type buried layer has a maximum concentration greater than a maximum P type majority dopant concentration in a P well extending from said P type buried layer through an N type layer.
15. A semiconductor device comprising:
- a non selective N type buried layer extending over a first layer;
- at least one selective P type buried layer having its entire lateral extent formed in a selected portion of the N type buried layer;
- a semiconductor layer extending over the N and P type buried layers, the semiconductor layer having a doping concentration lower than the N type buried layer and is totally separated from the first layer by the non selective N type buried layer and the P type buried layer;
- the P type buried layer extending from the N type buried layer into the semiconductor layer; and
- a P well extending from the P type buried layer through the semiconductor layer.
16. The semiconductor device set forth in claim 15 in which the semiconductor layer is N type.
17. The semiconductor device set forth in claim 15, wherein the first layer is an insulator.
18. The semiconductor device set forth in claim 15, wherein the first layer is a semiconductor substrate.
19. The semiconductor device set forth in claim 15, wherein non selective N type buried layer covers the total surface of the first layer.
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- Rupit Patel, et al., A 30V Complementary Bipoar Technology on SOI for High Speed Precision Analog Circuits, 1997 IEEE BCTM, pp. 48-50.
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Type: Grant
Filed: Oct 5, 2004
Date of Patent: Aug 10, 2010
Inventor: James D. Beasom (Melbourne Village, FL)
Primary Examiner: Lynne Gurley
Assistant Examiner: Junghwa M Im
Application Number: 10/958,229
International Classification: H01L 29/00 (20060101);