Vertical Channel Patents (Class 438/212)
  • Patent number: 10242869
    Abstract: A method of manufacturing a switching element includes forming a recessed portion in a surface of a GaN semiconductor substrate in which a first n-type semiconductor layer is exposed on the surface, growing a p-type body layer within the recessed portion and on the surface of the GaN semiconductor substrate, removing a surface layer portion of the body layer to expose the first n-type semiconductor layer on the surface of the GaN semiconductor substrate, and leave the body layer within the recessed portion, forming a second n-type semiconductor layer which is separated from the first n-type semiconductor layer by the body layer and is exposed on the surface of the GaN semiconductor substrate, and forming a gate electrode which faces the body layer through an insulating film.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: March 26, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tetsuya Yamada, Hiroyuki Ueda, Tomohiko Mori
  • Patent number: 10096695
    Abstract: A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: October 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10008420
    Abstract: Techniques for measuring and testing a semiconductor wafer during semiconductor device fabrication include designating a test area on the top surface of the wafer and etching a first rectangular trench and a second rectangular trench on the top surface of the wafer in the test area. The trenches are oriented such that a length of the first trench is perpendicular to a length of the second trench, and positioned such that the length of the first trench, if extended, intersects the length of the second trench. A silicon-germanium compound is deposited into the first trench and the second trench, and a test pad is removed from the test area of the wafer. The test pad includes a side surface where both the first trench and the second trench are exposed. The side surface of the test pad is scanned with a transmission electron microscope to take measurements of the silicon-germanium.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: June 26, 2018
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Haifeng Zhou, Jun Tan
  • Patent number: 9929281
    Abstract: A transistor includes a gate, a source, and a drain, the gate is electrically connected to the source or the drain, a first signal is input to one of the source and the drain, and an oxide semiconductor layer whose carrier concentration is 5×1014/cm3 or less is used for a channel formation layer. A capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a second signal which is a clock signal is input to the second electrode. A voltage of the first signal is stepped up or down to obtain a third signal which is output as an output signal through the other of the source and the drain of the transistor.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroyuki Miyake, Masashi Tsubuku, Kosei Noda
  • Patent number: 9768193
    Abstract: A three-dimensional (3D) semiconductor device includes a stack of conductive layers spaced from each other in a vertical direction, the stack having a staircase-shaped section in a connection region, and ends of the conductive layers constituting treads of the staircase-shaped section, respectively. The 3D semiconductor device further includes buffer patterns disposed on and protruding above the respective ends of the conductive layers, an interconnection structure disposed above the stack and including conductive lines, and contact plugs extending vertically between the conductive lines and the buffer patterns and electrically connected to the conductive layers of the stack via the buffer patterns.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: September 19, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegoo Lee, Youngwoo Park
  • Patent number: 9658186
    Abstract: A transistor includes a substrate, a two-dimensional material including at least one layer that is substantially vertically aligned on the substrate such that an edge of the layer is on the substrate and the layer extends substantially vertical to the substrate, a source electrode and a drain electrode connected to opposite ends of the two-dimensional material, a gate insulation layer on the two-dimensional material between the source electrode and the drain electrode, and a gate electrode on the gate insulation layer. Each layer includes a semiconductor having a two-dimensional crystal structure.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: May 23, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kiyeon Yang, Changseung Lee, Namjeong Kim, Yeonhee Kim
  • Patent number: 9502518
    Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: November 22, 2016
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Liu, Ruilong Xie, Chun-chen Yeh, Xiuyu Cai
  • Patent number: 9356095
    Abstract: Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: May 31, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Filippini, Luca Ferrario, Marcello Mariani
  • Patent number: 9293499
    Abstract: A semiconductor light detecting element is provided with a silicon substrate having a semiconductor layer, and an epitaxial semiconductor layer grown on the semiconductor layer and having a lower impurity concentration than the semiconductor layer; and conductors provided on a surface of the epitaxial semiconductor layer. A photosensitive region is formed in the epitaxial semiconductor layer. Irregular asperity is formed at least in a surface opposed to the photosensitive region in the semiconductor layer. The irregular asperity is optically exposed.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: March 22, 2016
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Mitsuhito Mase, Akira Sakamoto, Takashi Suzuki, Tomohiro Yamazaki, Yoshimaro Fujii
  • Patent number: 9263577
    Abstract: A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. A gate construction of the transistor comprises inner dielectric extending along the channel top and laterally along the channel sidewalls. Inner conductive material is elevationally and laterally outward of the inner dielectric and extends along the channel top and laterally along the channel sidewalls. Outer ferroelectric material is elevationally outward of the inner conductive material and extends along the channel top. Outer conductive material is elevationally outward of the outer ferroelectric material and extends along the channel. Other constructions and methods are disclosed.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: February 16, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Kirk D. Prall
  • Patent number: 9123585
    Abstract: A method includes providing a structure having a substrate, a first electrically insulating layer overlying the substrate, a first semiconductor layer comprised of a first semiconductor material overlying the first electrically insulating layer, a second electrically insulating layer overlying the first semiconductor layer in a first portion of the structure and a second semiconductor layer comprised of a second, different semiconductor material overlying the second electrically insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure to form a regrown semiconductor layer; forming fins; forming gate structures orthogonal to the fins and removing at least a portion of the first semiconductor layer in the first portion of the structure to form a void and filling the void with insulating material. Structures formed by the method are also disclosed.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: September 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: Lukas Czornomaz, Jean Fompeyrine, Effendi Leobandung
  • Patent number: 9087895
    Abstract: Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: July 21, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Filippini, Luca Ferrario, Marcello Mariani
  • Patent number: 9059042
    Abstract: One method disclosed includes, among other things, removing a sacrificial gate structure to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to define a fin structure in a layer of semiconductor material using a patterned hard mask exposed within the replacement gate cavity as an etch mask and forming a replacement gate structure in the replacement gate cavity around at least a portion of the fin structure.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: June 16, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Ajey Poovannummoottil Jacob
  • Publication number: 20150137075
    Abstract: Inverters including two-dimensional (2D) material, methods of manufacturing the same, and logic devices including the inverters. An inverter may include a first transistor and a second transistor that are connected to each other, and the first and second transistor layers may include 2D materials. The first transistor may include a first graphene layer and a first 2D semiconductor layer contacting the first graphene layer, and the second transistor may include a second graphene layer and a second 2D semiconductor layer contacting the second graphene layer. The first 2D semiconductor layer may be a p-type semiconductor, and the second 2D semiconductor layer may be an n-type semiconductor. The first 2D semiconductor layer may be arranged at a lateral side of the second 2D semiconductor layer.
    Type: Application
    Filed: April 30, 2014
    Publication date: May 21, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-seong HEO, Seong-jun PARK, Hyeon-jin SHIN
  • Publication number: 20150132903
    Abstract: The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a first and a second pull-up devices; a first and a second pull-down devices configured with the first and second pull-up devices to form two cross-coupled inverters for data storage; and a first and second pass-gate devices configured with the two cross-coupled inverters to form a port for data access, wherein the first and second pull-down devices each includes a first channel doping feature of a first doping concentration, and the first and second pass-gate devices each includes a second channel doping feature of a second doping concentration greater than the first doping concentration.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Inventor: Jhon-Jhy Liaw
  • Patent number: 9024399
    Abstract: A perpendicular STT-MRAM comprises apparatus and a method of manufacturing a plurality of magnetoresistive memory element having local magnetic shielding. As an external perpendicular magnetic field exists, the permeable dielectric layers, the permeable bit line and the permeable bottom electrode are surrounding and have capability to absorb and channel most magnetic flux surrounding the MTJ element instead of penetrate through the MTJ element. Thus, magnetization of a recording layer can be less affected by the stray field during either writing or reading, standby operation.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 5, 2015
    Inventor: Yimin Guo
  • Patent number: 9006063
    Abstract: A method for forming a trench MOSFET includes doping a body region of the trench MOSFET in multiple ion implantation steps each having different ion implantation energy. The method further comprises etching the trench to a depth of about 1.7 ?m.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 14, 2015
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Yean Ching Yong, Stefania Fortuna
  • Patent number: 8994081
    Abstract: A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 8993395
    Abstract: A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Ramachandran Muralidhar, Philip J. Oldiges, Viorel Ontalus
  • Patent number: 8987083
    Abstract: In a non-planar based semiconductor process where the structure includes both N and P type raised structures (e.g., fins), and where a different type of epitaxy is to be grown on each of the N and P type raised structures, prior to the growing, a lithographic blocking material over one of the N and P type raised structure portions is selectively etched to expose and planarize a gate cap. After the first type of epitaxy is grown, the process is repeated for the other of the N and P type epitaxy.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: March 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Zhenyu Hu, Zhao Lun, Xing Zhang
  • Patent number: 8987082
    Abstract: A method of making a semiconductor device includes forming a sacrificial layer above a semiconductor layer. Portions of the sacrificial layer are selectively removed to define a first set of spaced apart sacrificial fins over a first region of the semiconductor layer, and a second set of spaced apart sacrificial fins over a second region of the semiconductor layer. An isolation trench is formed in the semiconductor layer between the first and second regions. The isolation trench and spaces are filled with a dielectric material. The first and second sets of sacrificial fins are removed to define respective first and second sets of fin openings. The first set of fin openings is filled to define a first set of semiconductor fins for a first conductivity-type transistor, and the second set of fin openings is filled to define a second set of semiconductor fins for a second conductivity-type transistor.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: March 24, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Prasanna Khare
  • Patent number: 8980707
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Patent number: 8981493
    Abstract: An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Thomas N. Adam, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8981469
    Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Tamaki, Yoshito Nakazawa
  • Patent number: 8975705
    Abstract: A semiconductor device includes a first planar silicon layer, first and second pillar-shaped silicon layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped silicon layer and a center of the second pillar-shaped silicon layer.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 10, 2015
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura
  • Patent number: 8969149
    Abstract: A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 8969154
    Abstract: A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: March 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 8969912
    Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 3, 2015
    Assignee: Avogy, Inc.
    Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
  • Patent number: 8962425
    Abstract: A semiconductor device has a substrate and trench formed partially through the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited within the trench. A channel region is formed along the sidewall of the trench above the insulating material. The channel region is separated from the insulating material. A gate structure is formed within the trench adjacent to the channel region. The gate structure includes an insulating layer formed along the sidewall of the trench adjacent to the channel region and polysilicon layer formed within the trench over the insulating layer. A source region is formed in a first surface of the substrate contacting the channel region.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: February 24, 2015
    Assignee: Great Wall Semiconductor Corporation
    Inventors: Zheng John Shen, Patrick M. Shea, David N. Okada
  • Patent number: 8941173
    Abstract: According to an example embodiment of inventive concepts, a capacitorless memory device includes a capacitorless memory cell that includes a bit line on a substrate; a read transistor, and a write transistor. The read transistor may include first to third impurity layers stacked in a vertical direction on the bit line. The first and third layers may be a first conductive type, and the second impurity layer may be a second conductive type that differs from the first conductive type. The write transistor may include a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate, and a gate line that is adjacent to a side surface of the body layer. The gate line may be spaced apart from the side surface of the body layer. The source layer may be adjacent to a side surface of the second impurity layer.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: January 27, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Uk Han, Jae-Hoon Lee, Jun-Su Kim, Satoru Yamada, Jin-Seong Lee, Nam-Ho Jeon
  • Publication number: 20150014765
    Abstract: A radiation resistant CMOS device and a method for fabricating the same. The CMOS device includes a substrate, a source region, a drain region and a vertical channel on the substrate. A first dielectric protection region is inserted into the vertical channel at the center of the vertical channel to divide the vertical channel into two parts and has a height equal to the length of the vertical channel. The edge of the first dielectric protection region is 20-100 nm from an outer side of the channel, with a central axis of an silicon platform for an active region as the center. A second dielectric protection region is disposed under the source or drain region, with a length equal to the length of the source or drain region and a height of 10-50 nm. The dielectric protection regions effectively block paths for the source and drain regions collecting charges.
    Type: Application
    Filed: June 5, 2013
    Publication date: January 15, 2015
    Applicant: PEKING UNIVERSITY
    Inventors: Ru Huang, Fei Tan, Xia An, Weikang Wu, Liangxi Huang
  • Patent number: 8921922
    Abstract: This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Young-Jin Lee, Sung-Jin Whang
  • Patent number: 8912063
    Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a gate pattern which intersects a fin-type active pattern protruding upward from a device isolation layer. A first blocking pattern is formed on a portion of the fin-type active pattern, which does not overlap the gate pattern. Side surfaces of the portion of the fin-type active pattern are exposed. A semiconductor pattern is formed on the exposed side surfaces of the portion of the fin-type active pattern after the forming of the first blocking pattern.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Bum Kim, Ha-Kyu Seong
  • Publication number: 20140353742
    Abstract: A power semiconductor device comprises a first substrate that is highly doped with a first dopant type, the first substrate having a front face and a back face, the back face forming a backside of the device, a vertical p-type FET and a vertical n-type FET provided laterally adjacent to each other on the front face of the first substrate, wherein one of the FETs has a first drift zone with a complementary doping to the first dopant of the first substrate, and wherein the p-type FET and the n-type FET share the first substrate as a common backside, and wherein a region between the first drift zone and the first substrate comprises a highly conductive structure providing a low ohmic connection between the first drift zone and the first substrate. Further, a method for producing such a device is provided.
    Type: Application
    Filed: June 4, 2013
    Publication date: December 4, 2014
    Inventors: Peter Irsigler, Franz Hirler, Hans-Joachim Schulze
  • Patent number: 8890252
    Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: November 18, 2014
    Assignee: DENSO CORPORATION
    Inventors: Hirotaka Saikaku, Tsuyoshi Yamamoto, Shoji Mizuno, Masakiyo Sumitomo, Tetsuo Fujii, Jun Sakakibara, Hitoshi Yamaguchi, Yoshiyuki Hattori, Rie Taguchi, Makoto Kuwahara
  • Patent number: 8883593
    Abstract: A semiconductor pillar which has a first conductivity type and protrudes from a semiconductor substrate, is formed. A bottom diffusion layer having a second conductivity type is formed in the semiconductor substrate around a bottom of the semiconductor pillar. A gate insulator film which covers a side surface of the semiconductor pillar, is formed. A gate electrode which covers the gate insulator film, is formed. A top diffusion layer having the second conductivity type is formed at a top portion of the semiconductor pillar. The top diffusion layer including a semiconductor body is formed by an epitaxial growth which contains an impurity.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: November 11, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kazuhiro Nojima
  • Patent number: 8883576
    Abstract: Provided are methods of fabricating a semiconductor device. The method may include forming a mold layer on a substrate, forming a mask layer on the mold layer, etching the mold layer using the mask layer as an etch mask to form a channel hole penetrating the mold layer, shrinking the mask layer to provide a reduced mask layer, forming a spacer layer to cover the reduced mask layer, and forming a vertical channel to fill the channel hole and be electrically connected to the substrate. As a result, the channel hole can have an enlarged entrance.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinkwan Lee, Yoochul Kong, Seongsoo Lee
  • Patent number: 8872243
    Abstract: A semiconductor device manufacturing method includes providing a mask on a semiconductor member. The method further includes providing a dummy element to cover a portion of the mask that overlaps a first portion of the semiconductor member and to cover a second portion of the semiconductor member. The method further includes removing a third portion of the semiconductor member, which has not been covered by the mask or the dummy element. The method further includes providing a silicon compound that contacts the first portion of the semiconductor member. The method further includes removing the dummy element to expose and to remove the second portion of the semiconductor member. The method further includes forming a gate structure that overlaps the first portion of the semiconductor member. The first portion of the semiconductor member is used as a channel region and is supported by the silicon compound.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 28, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fumitake Mieno
  • Patent number: 8859369
    Abstract: Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region (5) is formed therebetween. In this manner, when a high voltage is applied to a drain region and 0 V is applied to the gate electrode, the trench bottom surface lower region (5) is depleted, thereby increasing the breakdown voltage in the OFF state.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: October 14, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Yukimasa Minami
  • Publication number: 20140264559
    Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.
    Type: Application
    Filed: April 19, 2013
    Publication date: September 18, 2014
    Inventors: Tai-I Yang, Hong-Seng Shue, Kun-Ming Huang, Tzu-Cheng Chen, Ming-Che Yang, Po-Tao Chu
  • Patent number: 8835977
    Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: September 16, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Limin Weng
  • Patent number: 8829641
    Abstract: In one general aspect, a method of forming a field effect transistor can include forming a well region in a semiconductor region of a first conductivity type where the well region is of a second conductivity type and has an upper surface and a lower surface. The method can include forming a gate trench extending into the semiconductor region to a depth below a depth of the lower surface of the well region, and forming a stripe trench extending through the well region and into the semiconductor region to a depth below the depth of the gate trench. The method can also include forming a contiguous source region of the first conductivity type in the well region where the source region being in contact with the gate trench and in contact with the stripe trench.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: September 9, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Bruce D. Marchant
  • Patent number: 8828817
    Abstract: A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
  • Patent number: 8802524
    Abstract: The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 12, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yi-Wei Chen, Hsin-Fu Huang, Tzung-Ying Lee, Min-Chuan Tsai, Chan-Lon Yang, Chun-Yuan Wu, Teng-Chun Tsai, Guang-Yaw Hwang, Chia-Lin Hsu, Jie-Ning Yang, Cheng-Guo Chen, Jung-Tsung Tseng, Zhi-Cheng Lee, Hung-Ling Shih, Po-Cheng Huang, Yi-Wen Chen, Che-Hua Hsu
  • Patent number: 8803205
    Abstract: A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: August 12, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Hans Weber, Michael Treu
  • Patent number: 8796085
    Abstract: The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: August 5, 2014
    Inventors: Viktor Koldiaev, Rimma Pirogova
  • Patent number: 8796123
    Abstract: An impurity of a first conductivity type is implanted onto a silicon carbide substrate through an opening in a mask layer. First and second films made of first and second materials respectively are formed. It is sensed that etching of the first material is performed during anisotropic etching, and then anisotropic etching is stopped. An impurity of a second conductivity type is implanted onto the silicon carbide substrate through the opening narrowed by the first and second films. Thus, the impurity regions can be formed in an accurately self-aligned manner.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 5, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shunsuke Yamada, Takeyoshi Masuda
  • Publication number: 20140206161
    Abstract: A method of semiconductor device fabrication includes forming a first dummy gate structure in a first region of a semiconductor substrate and forming a second dummy gate structure in a second region of the semiconductor substrate. A protective layer (e.g., oxide and/or silicon nitride hard mask) is formed on the second dummy gate structure. The first dummy gate structure is removed after forming the protective layer, thereby providing a first trench. A capping layer (e.g., silicon) is formed in the first trench. A metal gate structure may be formed on the capping layer. The protective layer may protect the second dummy gate structure during the removal of the first dummy gate structure.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsu-Hsiu Perng, Zhao-Cheng Chen, Chun-Hsiang Fan, Ming-Huan Tsai
  • Patent number: 8772109
    Abstract: A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin structure and performing a solid phase epitaxial regrowth process on the amorphous silicon layer at a second temperature, wherein the second temperature is lower than the melting point of the germanium fin structure.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: July 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jean-Pierre Colinge
  • Patent number: 8772096
    Abstract: Provided are a method of forming a contact and a method of manufacturing a phase change memory device using the same. The method of forming a contact includes forming on a substrate an insulating layer pattern having first sidewalls extending in a first direction and second sidewalls extending in a second direction perpendicular to the first direction and which together delimit contact holes, forming semiconductor patterns in lower parts of the contact holes, forming isolation spacers on the semiconductor pattern and side surfaces of the first sidewalls to expose portions of the semiconductor patterns, and etching the exposed portions of the semiconductor patterns using the isolation spacers as a mask to divide the semiconductor patterns into a plurality of finer semiconductor patterns.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Pil Ko, Eun-Jung Kim, Yong-Jun Kim