With Epitaxial Semiconductor Layer Formation Patents (Class 438/226)
  • Patent number: 9034706
    Abstract: A method includes etching a semiconductor substrate to form a recess in the semiconductor substrate, and reacting a surface layer of the semiconductor substrate to generate a reacted layer. The surface layer of the semiconductor substrate is in the recess. The reacted layer is then removed. An epitaxy is performed to grow a semiconductor material in the recess.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Chih-Fang Liu, Tzu-Wei Kao, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Patent number: 9000516
    Abstract: A super-junction device including a unit region is disclosed. The unit region includes a heavily doped substrate; a first epitaxial layer over the heavily doped substrate; a second epitaxial layer over the first epitaxial layer; a plurality of first trenches in the second epitaxial layer; an oxide film in each of the plurality of first trenches; and a pair of first films on both sides of each of the plurality of first trenches, thereby forming a sandwich structure between every two adjacent ones of the plurality of first trenches, the sandwich structure including two first films and a second film sandwiched therebetween, the second film being formed of a portion of the second epitaxial layer between the two first films of a sandwich structure. A method of forming a super-junction device is also disclosed.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 7, 2015
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventor: Shengan Xiao
  • Patent number: 8912068
    Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 16, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Young-Ho Lee, Seung-Joon Jeon, Tae-Hang Ahn
  • Patent number: 8895357
    Abstract: Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: November 25, 2014
    Assignee: NXP B.V.
    Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Caroline Catharina Maria Beelen-Hendrikx
  • Patent number: 8895370
    Abstract: A vertical conduction power device includes respective gate, source and drain areas formed in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations are formed by a first metallization level. The gate, source and drain terminals are formed by a second metallization level. The device is configured as a set of modular areas extending parallel to each other. Each modular area has a rectangular elongate source area perimetrically surrounded by a gate area, and a drain area defined by first and second regions. The first regions of the drain extend parallel to one another and separate adjacent modular areas. The second regions of the drain area extend parallel to one another and contact ends of the first regions of the drain area.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 25, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magri′
  • Patent number: 8841177
    Abstract: First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 8841181
    Abstract: A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: September 23, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ying-Hung Chou, Shao-Hua Hsu, Chi-Horn Pai, Zen-Jay Tsai, Shih-Hao Su, Chun-Chia Chen, Shih-Chieh Hsu, Chih-Chung Chen
  • Patent number: 8809151
    Abstract: In sophisticated transistors, a specifically designed semiconductor material, such as a strain-inducing semiconductor material, may be sequentially provided in the drain region and the source region, thereby enabling a significant degree of lateral extension of the grown semiconductor materials without jeopardizing mechanical integrity of the transistor during the processing thereof. For example, semiconductor devices having different drain and source sides may be provided on the basis of sequentially provided embedded semiconductor materials.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: August 19, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Stephan-Detlef Kronholz, Jan Hoentschel, Thilo Scheiper
  • Patent number: 8796088
    Abstract: A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: August 5, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chul Jin Yoon
  • Patent number: 8748299
    Abstract: A semiconductor device includes an isolation layer pattern, an epitaxial layer pattern, a gate insulation layer pattern and a gate electrode. The isolation layer pattern is formed on a substrate, and defines an active region in the substrate. The isolation layer pattern extends in a second direction. The epitaxial layer pattern is formed on the active region and the isolation layer pattern, and has a width larger than that of the active region in a first direction perpendicular to the second direction. The gate insulation layer pattern is formed on the epitaxial layer pattern. The gate electrode is formed on the gate insulation layer pattern.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Suk Shin
  • Patent number: 8729672
    Abstract: To grow a gallium nitride crystal, a seed-crystal substrate is first immersed in a melt mixture containing gallium and sodium. Then, a gallium nitride crystal is grown on the seed-crystal substrate under heating the melt mixture in a pressurized atmosphere containing nitrogen gas and not containing oxygen. At this time, the gallium nitride crystal is grown on the seed-crystal substrate under a first stirring condition of stirring the melt mixture, the first stirring condition being set for providing a rough growth surface, and the gallium nitride crystal is subsequently grown on the seed-crystal substrate under a second stirring condition of stirring the melt mixture, the second stirring condition being set for providing a smooth growth surface.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: May 20, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Takanao Shimodaira, Takayuki Hirao, Katsuhiro Imai
  • Patent number: 8729591
    Abstract: Non-planar via designs for sub-mounts on which to mount a LED or other optoelectronic device include a continuous layer of metal to conduct the current from the front-side (e.g., LED side) to the backside (e.g., SMD side) through the via and to provide a sufficiently stable and reliable under bump metallization for SMD soldering. Each UBM can be structured so that it does not fully cover the sidewall surfaces of the via that forms the front-to-backside interconnect. In some implementations, each via structure for the feedthrough metallization extends to a respective side-edge of the sub-mount.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: May 20, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Jochen Kuhmann, Lior Shiv
  • Patent number: 8685773
    Abstract: A method for making a semiconductor epitaxial structure is provided. The method includes growing a substrate having an epitaxial growth surface, placing a carbon nanotube layer on the epitaxial growth surface, epitaxially growing a doped semiconductor epitaxial layer on the epitaxial growth surface. The carbon nanotube layer can be suspended above the epitaxial growth surface.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: April 1, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 8440017
    Abstract: To grow a gallium nitride crystal, a seed-crystal substrate is first immersed in a melt mixture containing gallium and sodium. Then, a gallium nitride crystal is grown on the seed-crystal substrate under heating the melt mixture in a pressurized atmosphere containing nitrogen gas and not containing oxygen. At this time, the gallium nitride crystal is grown on the seed-crystal substrate under a first stirring condition of stirring the melt mixture, the first stirring condition being set for providing a rough growth surface, and the gallium nitride crystal is subsequently grown on the seed-crystal substrate under a second stirring condition of stirring the melt mixture, the second stirring condition being set for providing a smooth growth surface.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: May 14, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Takanao Shimodaira, Takayuki Hirao, Katsuhiro Imai
  • Patent number: 8338246
    Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor substrate to have a SOI structure by an epitaxial process for forming a gate while forming an insulating film pattern in a bottom where a device isolation trench is formed. The method thereby increases the process margin for forming a device isolation film and prevents the punch-through phenomenon to improve electrical characteristics of semiconductor devices and increase product yield.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 25, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Song Hyeuk Im
  • Patent number: 8049231
    Abstract: Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can generate laser light of a different color. Within each multicolor pixel, the light generated from the stack of diodes is emitted perpendicular to the plane of the imager device via a plurality of vertical waveguides that are coupled to the optical confinement regions of each of the multiple laser diodes comprising the imager device. Each of the laser diodes comprising a single pixel is individually addressable, enabling each pixel to simultaneously emit any combination of the colors associated with the laser diodes at any required on/off duty cycle for each color. Each individual multicolor pixel can simultaneously emit the required colors and brightness values by controlling the on/off duty cycles of their respective laser diodes.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: November 1, 2011
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Robert G. W. Brown, Dale A. McNeill, Huibert DenBoer, Andrew J. Lanzone
  • Patent number: 8012833
    Abstract: A method for fabricating a semiconductor device includes forming an insulating pattern over a semiconductor substrate. An epitaxial growth layer is formed over the semiconductor substrate exposed by the insulating pattern to fill the insulating pattern with the epitaxial growth layer. A recess gate having a recess channel is formed. The recess channel is disposed between two neighboring insulating patterns.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: September 6, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Song Hyeuk Im
  • Patent number: 7972971
    Abstract: The disclosure relates to a method for producing a microelectronic device including a plurality of Si1-yGey based semi-conducting zones (where 0<y?1) which have different respective Germanium contents, comprising the steps of: a) formation on a substrate covered with a plurality of Si1-yGey based semi-conducting zones (where 0<x<1 and x<y) and identical compositions, of at least one mask comprising a set of masking blocks, wherein the masking blocks respectively cover at least one semi-conducting zone of the said plurality of semi-conducting zones, wherein several of said masking blocks have different thicknesses and/or are based on different materials, b) oxidation of the semi-conducting zones of the said plurality of semi-conducting zones through said mask.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: July 5, 2011
    Assignees: Commissariat A l'Energie Atomique, STMicroelectronics SA
    Inventors: Jean-Francois Damlencourt, Yves Morand, Laurent Clavelier
  • Patent number: 7972922
    Abstract: A method of forming a semiconductor layer, which in one embodiment is part of a photodetector, includes forming a silicon shape, applying ozonated water, removing the first oxide layer at a temperature below 600 degrees Celsius, and epitaxially growing germanium. The silicon shape has a top surface that is exposed. The ozonated water is applied to the top surface and causes formation of a first oxide layer on the top surface. The germanium is grown on the top surface.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: July 5, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hunter J. Martinez, John J. Hackenberg, Jill Hildreth, Ross E. Noble
  • Patent number: 7947569
    Abstract: A method for producing a semiconductor including a material layer. In one embodiment a trench is produced having two opposite sidewalls and a bottom, in a semiconductor body. A foreign material layer is produced on a first one of the two sidewalls of the trench. The trench is filled by epitaxially depositing a semiconductor material onto the second one of the two sidewalls and the bottom of the trench.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: May 24, 2011
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Frank Pfirsch, Rudolf Berger, Stefan Sedlmaier, Wolfgang Lehnert, Raimund Foerg
  • Patent number: 7939413
    Abstract: An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: May 10, 2011
    Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Yung Fu Chong, Zhijiong Luo, Joo Chan Kim, Brian Joseph Greene, Kern Rim
  • Patent number: 7902030
    Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp(21541/T).
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: March 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Ito, Yusuke Oshiki, Kouji Matsuo, Kenichi Yoshino, Takaharu Itani, Takuo Ohashi, Toshihiko Iinuma, Kiyotaka Miyano, Kunihiro Miyazaki
  • Patent number: 7795089
    Abstract: A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: September 14, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Laegu Kang, Vishal P. Trivedi, Da Zhang
  • Patent number: 7785975
    Abstract: An SOI device includes an SOI substrate composed of a stack structure of a silicon substrate, a buried oxide layer, and a silicon layer. Grooves are defined in the silicon layer each exposing the buried oxide layer. A barrier layer is formed on the lower portion of the sidewall of each of the grooves. An epi-silicon layer is formed to fill the grooves and cover the barrier layer. Gates are formed on the epi-silicon layer, and junction areas are formed in the silicon layer on both sides of the gates.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: August 31, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Bo Youn Kim
  • Patent number: 7776698
    Abstract: Methods for formation of epitaxial layers containing n-doped silicon are disclosed, including methods for the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. Formation of the n-doped epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source, a carbon source and an n-dopant source at a first temperature and pressure and then exposing the substrate to an etchant at a second higher temperature and a higher pressure than during deposition.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: August 17, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Zhiyuan Ye, Saurabh Chopra, Andrew Lam, Yihwan Kim
  • Patent number: 7763510
    Abstract: A semiconductor process and apparatus includes forming PMOS transistors (90) with enhanced hole mobility in the channel region by forming a hydrogen-rich silicon nitride layer (91, 136) on or adjacent to sidewalls of the PMOS gate structure as either a hydrogen-rich implant sidewall spacer (91) or as a post-silicide hydrogen-rich implant sidewall spacer (136), where the hydrogen-rich dielectric layer acts as a hydrogen source for passivating channel surface defectivity under the PMOS gate structure.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: July 27, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Voon-Yew Thean
  • Patent number: 7759229
    Abstract: A charge-free method of forming a nanostructure at low temperatures on a substrate. A substrate that is reactive with one of atomic oxygen and nitrogen is provided. A flux of neutral atoms of least one of oxygen and nitrogen is generated within a laser-sustained-discharge plasma source and a collimated beam of energetic neutral atoms and molecules is directed from the plasma source onto a surface of the substrate to form the nanostructure. The energetic neutral atoms and molecules in the beam have an average kinetic energy in a range from about 1 eV to about 5 eV.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: July 20, 2010
    Assignee: Los Alamos National Security, LLC
    Inventors: Mark Hoffbauer, Elshan Akhadov
  • Patent number: 7704809
    Abstract: A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation also overlies the insulator layer. In one embodiment, the silicon-on-insulator chip also includes a first transistor of a first conduction type formed on the first silicon island, and a second transistor of a second conduction type formed on the second silicon island. For example, the first crystal orientation can be (110) while the first transistor is a p-channel transistor, and the second crystal orientation can be (100) while the second transistor is an n-channel transistor.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: April 27, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Fu-Liang Yang
  • Patent number: 7687337
    Abstract: A transistor is formed by providing a semiconductor layer and forming a control electrode overlying the semiconductor layer. A portion of the semiconductor layer is removed lateral to the control electrode to form a first recess and a second recess on opposing sides of the control electrode. A first stressor is formed within the first recess and has a first doping profile. A second stressor is formed within the second recess and has the first doping profile. A third stressor is formed overlying the first stressor. The third stressor has a second doping profile that has a higher electrode current doping concentration than the first profile. A fourth stressor overlying the second stressor is formed and has the second doping profile. A first current electrode and a second current electrode of the transistor include at least a portion of the third stressor and the fourth stressor, respectively.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: March 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Mark C. Foisy
  • Patent number: 7682887
    Abstract: Methods and resulting structure of forming a transistor having a high mobility channel are disclosed. In one embodiment, the method includes providing a gate electrode including a gate material area and a gate dielectric, the gate electrode being positioned over a channel in a silicon substrate. A dielectric layer is formed about the gate electrode, and the gate material area and the gate dielectric are removed from the gate electrode to form an opening into a portion of the silicon substrate that exposes source/drain extensions. A high mobility semiconductor material, i.e., one having a carrier mobility greater than doped silicon, is then formed in the opening such that it laterally contacts the source/drain extensions. The gate dielectric and the gate material area may then be re-formed. This invention eliminates the high temperature steps after the formation of high mobility channel material used in related art methods.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Omer H. Dokumaci, Woo-Hyeong Lee
  • Patent number: 7655533
    Abstract: A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: February 2, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Sun Sheen, Sang Tae Ahn, Seok Pyo Song, Hyeon Ju An
  • Patent number: 7648893
    Abstract: A method for manufacturing a semiconductor including the steps of supplying a substrate having a support with one face supporting a strained silicon thin layer; forming a first mask on a portion of the strained silicon thin layer; epitaxy of Si1-xGex on the portion of the layer not masked by the first mask; condensating germanium to obtain a strained germanium layer, the strained germanium layer then covered by a silicon oxide layer; eliminating the first mask and of the silicon oxide layer thereby exposing a semi-conducting thin layer; forming a second mask on the semi-conducting thin layer exposed via the previous step, the second mask protecting a region of the exposing a remaining strained germanium portion; epitaxial growing germanium on the remaining strained germanium portion; and removing the second mask.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: January 19, 2010
    Assignee: Commissariat A l'Energie Atomique
    Inventors: Jean-Francois Damlencourt, Laurent Clavelier
  • Patent number: 7648853
    Abstract: Dual channel heterostructures comprising strained Si and strained Ge-containing layers are disclosed, along with methods for producing such structures. In preferred embodiments, a strain-relaxed buffer layer is deposited on a carrier substrate, a strained Si layer is deposited over the strain-relaxed buffer layer and a strained Ge-containing layer is deposited over the strained Si layer. The structure can be transferred to a host substrate to produce the strained Si layer over the strained Ge-containing layer. By depositing the Si layer first, the process avoids Ge agglomeration problems.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: January 19, 2010
    Assignee: ASM America, Inc.
    Inventor: Matthias Bauer
  • Patent number: 7629233
    Abstract: The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: December 8, 2009
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Jeffery Sleight, Min Yang
  • Patent number: 7615390
    Abstract: The present invention provides a method of depositing epitaxial layers based on Group IV elements on a silicon substrate by Chemical Vapor Deposition, wherein nitrogen or one of the noble gases is used as a carrier gas, and the invention further provides a Chemical Vapor Deposition apparatus (10) comprising a chamber (12) having a gas input port (14) and a gas output port (16), and means (18) for mounting a silicon substrate within the chamber (12), said apparatus further including a gas source connected to the input port and arranged to provide nitrogen or a noble gas as a carrier gas.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: November 10, 2009
    Assignee: NXP B.V.
    Inventors: Philippe Meunier-Beillard, Mathieu Rosa Jozef Caymax
  • Patent number: 7601582
    Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor substrate to have a SOI structure by an epitaxial process for forming a gate while forming an insulating film pattern in a bottom where a device isolation trench is formed. The method thereby increases the process margin for forming a device isolation film and prevents the punch-through phenomenon to improve electrical characteristics of semiconductor devices and increase product yield.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: October 13, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Song Hyeuk Im
  • Patent number: 7598142
    Abstract: A CMOS device having dual-epi channels comprises a first epitaxial region formed on a substrate, a PMOS device formed on the first epitaxial region, a second epitaxial region formed on the substrate, wherein the second epitaxial region is formed from a different material than the first epitaxial region, an NMOS device formed on the second epitaxial region, and electrical contacts coupled to the PMOS and NMOS devices, wherein the electrical contacts are self-aligned.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: October 6, 2009
    Inventors: Pushkar Ranade, Keith E. Zawadzki
  • Patent number: 7524707
    Abstract: A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). By forming the first gate electrode (151) over a first SOI substrate (90) formed by depositing (100) silicon and forming the second gate electrode (161) over an epitaxially grown (110) SiGe substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: April 28, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Olubunmi O. Adetutu, Mariam G. Sadaka, Ted R. White, Bich-Yen Nguyen
  • Patent number: 7510925
    Abstract: A method of manufacturing a semiconductor device includes: the first step of forming a gate electrode over a silicon substrate, with a gate insulating film; and the second step of digging down a surface layer of the silicon substrate by etching conducted with the gate electrode as a mask. The method of manufacturing the semiconductor device further includes the third step of epitaxially growing, on the surface of the dug-down portion of the silicon substrate, a mixed crystal layer including silicon and atoms different in lattice constant from silicon so that the mixed crystal layer contains an impurity with such a concentration gradient that the impurity concentration increases along the direction from the silicon substrate side toward the surface of the mixed crystal layer.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: March 31, 2009
    Assignee: Sony Corporation
    Inventor: Yuki Miyanami
  • Patent number: 7432167
    Abstract: The present invention provides a method of fabricating strained silicon channel MOS transistor, comprising providing a substrate, forming at least a gate structure on the substrate, forming a mask layer on the gate structure, performing an etching process to form two recesses corresponding to the gate structure within the substrate, performing a selective epitaxial growth (SEG) process to form an epitaxial layer in the recesses respectively, and performing an ion implantation process for the epitaxial layers to form a source/drain region.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: October 7, 2008
    Assignee: United Microelectronics Corp.
    Inventor: Chao-Ching Hsieh
  • Patent number: 7402477
    Abstract: A method of having transistors formed in enhanced performance crystal orientations begins with a wafer having a semiconductor substrate (12,52) of a first surface orientation, a thin etch stop layer (14,54) on the semiconductor substrate, a buried oxide layer (16,56) on the thin etch stop layer, and a semiconductor layer (18,58) of a second surface orientation on the buried oxide layer. An etch penetrates to the thin etch stop layer. Another etch, which is chosen to minimize the damage to the underlying semiconductor substrate, exposes a portion of the semiconductor substrate. An epitaxial semiconductor (28,66) is then grown from the exposed portion of the semiconductor substrate to form a semiconductor region having the first surface orientation and having few, if any, defects. The epitaxially grown semiconductor region is then used for enhancing one type of transistor while the semiconductor layer of the second surface orientation is used for enhancing a different type of transistor.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: July 22, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mariam G. Sadaka, Bich-Yen Nguyen, Ted R. White
  • Patent number: 7402485
    Abstract: A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: July 22, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William G. En, Thorsten Kammler, Eric N. Paton, Scott D. Luning
  • Patent number: 7393762
    Abstract: A method of forming a nanostructure at low temperatures. A substrate that is reactive with one of atomic oxygen and nitrogen is provided. A flux of neutral atoms of at least one of nitrogen and oxygen is generated within a laser-sustained-discharge plasma source and a collimated beam of energetic neutral atoms and molecules is directed from the plasma source onto a surface of the substrate to form the nanostructure. The energetic neutral atoms and molecules in the plasma have an average kinetic energy in a range from about 1 eV to about 5 eV.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: July 1, 2008
    Assignee: Los Alamos National Secruity, LLC
    Inventors: Mark Hoffbauer, Alex Mueller
  • Patent number: 7320923
    Abstract: A method for forming a resistor of high value in a semiconductor substrate including forming a stack of a first insulating layer, a first conductive layer, a second insulating layer, and a third insulating layer, the third insulating layer being selectively etchable with respect to the second insulating layer; etching the stack, to expose the substrate and keep the stack in the form of a line; forming insulating spacers on the lateral walls of the line; performing an epitaxial growth of a single-crystal semiconductor on the substrate, on either side of the line; selectively removing the third insulating layer to partially expose the second insulating layer at a predetermined location; and depositing and etching a conductive material to fill the cavity formed by the previous removal of the third insulating layer.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: January 22, 2008
    Assignee: STMicroelectronics Crolles 2 SAS
    Inventors: Bertrand Borot, Philippe Coronel
  • Patent number: 7145187
    Abstract: In a multiple input ESD protection structure, the inputs are isolated from the substrate by highly doped regions of opposite polarity to the input regions. Dual polarity is achieved by providing a symmetrical structure with n+ and p+ regions forming each dual polarity input. The inputs are formed in a p-well which, in turn, is formed in a n-well. Each dual polarity input is isolated by a PBL under the p-well, and a NISO underneath the n-well. An isolation ring separates and surrounds the inputs. The isolation ring comprises a p+ ring or a p+ region, n+ region, and p+ region formed into adjacent rings.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: December 5, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Philipp Lindorfer
  • Patent number: 7029979
    Abstract: Methods for manufacturing semiconductor devices are disclosed. In a disclosed method, a first nitride layer and a device isolation oxide layer are etched to thereby expose a portion of a silicon substrate where an active region is to be formed. An epitaxial growth is performed on the active region and a first oxide layer is deposited thereon. Portions of the first oxide layer where a source and a drain are to be formed are etched. The first oxide layer deposited on the portions where the source and the drain are to be formed is then etched. An epitaxial growth is performed on the portions where the source and the drain are to be formed to thereby form the source and the drain. A second nitride layer is deposited thereon. A portion of the first oxide layer located where a gate is to be formed is etched using a gate mask. A third nitride layer is deposited on the source, the drain, and the exposed active region and then etched back to thereby form a nitride layer to control a length of the gate.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: April 18, 2006
    Assignee: DongbuAnam Semiconductor Inc.
    Inventor: Cheolsoo Park
  • Patent number: 6881641
    Abstract: An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: April 19, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Manfred Horstmann, Rolf Stephan
  • Patent number: 6833589
    Abstract: A field oxide film for element isolation is formed on an SOI substrate having a silicon layer formed on an insulating layer, an active nitride film is wet-etched to reduce its film thickness to a value small enough to allow the edge of the silicon layer to become exposed and ions of a channel stopping impurity are implanted only into the edge of the silicon layer through self-alignment either vertically or at an angle by using the active nitride film as a mask. Through this manufacturing method, a field effect transistor which achieves a small gate length, is free from the adverse effect of a parasitic transistor and thus does not readily manifest a hump, and allows a reduction in the distance between an nMOS and a pMOS provided next to each other is realized.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: December 21, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hideaki Matsuhashi, Yoko Kajita, Yoshihiro Koga, Toshiyuki Nakamura, Jun Kanamori
  • Patent number: 6815278
    Abstract: The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by forming an opening into a structure that includes at least a first semiconductor layer and a second semiconductor layer that have different crystal orientations. The opening extends to the first semiconductor layer.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Meikei Ieong, Min Yang
  • Patent number: 6723618
    Abstract: Field isolation structures and methods of forming field isolation structures are described. In one implementation, the method includes etching a trench within a monocrystalline silicon substrate. The trench has sidewalls and a base, with the base comprising monocrystalline silicon. A dielectric material is formed on the sidewalls of the trench. Epitaxial monocrystalline silicon is grown from the base of the trench and over at least a portion of the dielectric material. An insulating layer is formed over the epitaxial monocrystalline silicon. According to one implementation, the invention includes a field isolation structure formed within a monocrystalline silicon comprising substrate. The field isolation structure includes a trench having sidewalls. A dielectric material is received on the sidewalls within the trench. Monocrystalline silicon is received within the trench between the dielectric material of the sidewalls. An insulating layer is received over the monocrystalline silicon within the trench.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: April 20, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Russell Meyer, Jeffrey W. Honeycutt, Stephen R. Porter