With Epitaxial Semiconductor Layer Formation Patents (Class 438/226)
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Patent number: 6815278Abstract: The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by forming an opening into a structure that includes at least a first semiconductor layer and a second semiconductor layer that have different crystal orientations. The opening extends to the first semiconductor layer.Type: GrantFiled: August 25, 2003Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: Meikei Ieong, Min Yang
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Patent number: 6723618Abstract: Field isolation structures and methods of forming field isolation structures are described. In one implementation, the method includes etching a trench within a monocrystalline silicon substrate. The trench has sidewalls and a base, with the base comprising monocrystalline silicon. A dielectric material is formed on the sidewalls of the trench. Epitaxial monocrystalline silicon is grown from the base of the trench and over at least a portion of the dielectric material. An insulating layer is formed over the epitaxial monocrystalline silicon. According to one implementation, the invention includes a field isolation structure formed within a monocrystalline silicon comprising substrate. The field isolation structure includes a trench having sidewalls. A dielectric material is received on the sidewalls within the trench. Monocrystalline silicon is received within the trench between the dielectric material of the sidewalls. An insulating layer is received over the monocrystalline silicon within the trench.Type: GrantFiled: July 26, 2002Date of Patent: April 20, 2004Assignee: Micron Technology, Inc.Inventors: Russell Meyer, Jeffrey W. Honeycutt, Stephen R. Porter
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Patent number: 6667200Abstract: A method for forming a transistor of a semiconductor device, including the step of forming channel layers of a first and a second conductive types, performing high temperature thermal process to form stabilized channel layers and forming an epitaxial channel structure having a super-steep-retrograde &dgr;-doped layer by growing undoped silicon epitaxial layers, treating the entire surface of the resulting structure with hydrogen, forming an epitaxial channel structure by growing undoped silicon epitaxial layers on the stabilized channel layers, forming gate insulating films and gate electrodes on the epitaxial channel structures, re-oxidizing the gate insulating films for repairing damaged portions of the gate insulating films; and forming a source/drain region and performing a low temperature thermal process.Type: GrantFiled: December 30, 2002Date of Patent: December 23, 2003Assignee: Hynix Semiconductor Inc.Inventors: Yong Sun Sohn, Chang Woo Ryoo, Jeong Youb Lee
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Patent number: 6657262Abstract: An electronic device, integrated monolithically in a semiconductor substrate and comprising a bipolar transistor connected in series to at least one MOS transistor, the bipolar transistor having a base region that includes a first buried region and a first diffused region extending continuously from the substrate surface down to the buried region, and the diffused region is bordered by an isolation trench region extending in the buried region.Type: GrantFiled: March 30, 2001Date of Patent: December 2, 2003Assignee: STMicroelectronics S.r.l.Inventor: Davide Patti
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Patent number: 6649481Abstract: The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction capacitances are obtained by implementing in a self-aligned manner the major portions of the heavily-doped source and drain regions of a device over the trench-isolation region using highly-conductive silicided polycrystalline- or amorphous-semiconductor and the junction leakage currents resulting from the generation/recombination current in the depletion regions of the heavily-doped source and drain junctions due to the implant-induced defects can be much reduced or eliminated. Moreover, the contacts are made on the silicided heavily-doped source and drain regions over the trench-isolation regions, the traditional contact-induced leakage current due to the shallow source/drain junction can be completely eliminated by the present invention.Type: GrantFiled: March 30, 2001Date of Patent: November 18, 2003Assignee: Silicon-Based Technology Corp.Inventor: Ching-Yuan Wu
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Patent number: 6627515Abstract: A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer.Type: GrantFiled: December 13, 2002Date of Patent: September 30, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Horng-Huei Tseng, Jyh-Chyurn Guo, Chenming Hu, Da-Chi Lin
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Patent number: 6620671Abstract: A method of manufacturing an integrated circuit on a substrate provides a gate structure including single crystalline material. The method can provide a first amorphous or polycrystalline semiconductor layer above a top surface of the substrate and patterning the first amorphous semiconductor layer to form a first gate conductor. The process can also include utilizing solid phase epitaxy to form a single crystal layer above the first gate conductor and patterning the single crystal layer to form a second gate conductor including the single crystal layer.Type: GrantFiled: May 1, 2001Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Haihong Wang, Joong Jeon
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Patent number: 6455377Abstract: A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench.Type: GrantFiled: January 19, 2001Date of Patent: September 24, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying Keung Leung, Yelehanka Ramachandramurthy Pradeep
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Patent number: 6423599Abstract: For fabricating a field effect transistor having dual gates, on a buried insulating layer in SOI (semiconductor on insulator) technology, a first layer of first semiconductor material is deposited on the buried insulating material. The first layer of first semiconductor material is patterned to form a first semiconductor island having a first top surface and a second semiconductor island having a second top surface. The first and second semiconductor islands are comprised of the first semiconductor material. An insulating material is deposited to surround the first and second semiconductor islands, and the insulating material is polished down until the first and second top surfaces of the first and second semiconductor islands are exposed such that sidewalls of the first and second semiconductor islands are surrounded by the insulating material. A gate dopant is implanted into the second semiconductor island.Type: GrantFiled: May 1, 2001Date of Patent: July 23, 2002Assignee: Advanced Micro Devices, Inc.Inventor: Bin Yu
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Patent number: 6413829Abstract: For forming a field effect transistor on a buried insulating material in SOI (semiconductor on insulator) technology, a gate dielectric and a gate electrode are formed on the semiconductor material, and spacers are formed on sidewalls of the gate electrode and the gate dielectric. The spacers cover portions of the semiconductor material. A dopant is implanted into exposed regions of the semiconductor material to form a drain doped region and a source doped region. A portion of the drain doped region and a portion of the source doped region extend under the spacers. A drain contact silicide is formed with an exposed portion of the drain doped region, and a source contact silicide is formed with an exposed portion of the source doped region. The spacers are removed to expose the portions of the semiconductor material including a portion of the drain doped region and a portion of the source doped region.Type: GrantFiled: June 1, 2001Date of Patent: July 2, 2002Assignee: Advanced Micro Devices, Inc.Inventor: Bin Yu
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Publication number: 20020061618Abstract: A method of producing a bipolar transistor includes the step of providing a sacrificial mesa over a layer of SiGe in order to prevent a polysilicon covering layer from forming over a predetermined region of the SiGe layer forming the transistor base. After an etching process removes the sacrificial mesa and the SiGe layer is exposed, an oppositely doped material is applied over top of the SiGe layer to form an emitter. This makes it possible to realize a thin layer of silicon germanium to serve as the transistor base. This method prevents the base layer SiGe from being affected, as it otherwise would be using a conventional double-poly process.Type: ApplicationFiled: February 1, 2002Publication date: May 23, 2002Inventors: Stephen J. Kovacic, Derek C. Houghton
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Publication number: 20020052074Abstract: A method of producing a bipolar transistor includes the step of providing a sacrificial mesa over a layer of SiGe in order to prevent a polysilicon covering layer from forming over a predetermined region of the SiGe layer forming the transistor base. After an etching process removes the sacrificial mesa and the SiGe layer is exposed, an oppositely doped material is applied over top of the SiGe layer to form an emitter. This makes it possible to realize a thin layer of silicon germanium to serve as the transistor base. This method prevents the base layer SiGe from being affected, as it otherwise would be using a conventional double-poly process.Type: ApplicationFiled: November 20, 2001Publication date: May 2, 2002Inventors: Derek C. Houghton, Hugues Lafontaine
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Patent number: 6376293Abstract: A method of fabricating a CMOS transistor to construct shallow drain extenders (30) using a replacement gate design. The method involves forming epitaxial layers (30) and (220) the will later function as shallow drain extensions. The etching of the replacement gate (220) and the formation of inner sidewalls (90) serve to define the transistor gate length.Type: GrantFiled: March 29, 2000Date of Patent: April 23, 2002Assignee: Texas Instruments IncorporatedInventor: Richard A. Chapman
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Publication number: 20020045307Abstract: An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming a conductive structure insulatively disposed over the semiconductor substrate (step 302 of FIG. 3); introducing a silicide enhancing substance into the conductive structure (step 304 of FIG. 3); amorphizing a portion of the conductive structure; forming a metal layer on the conductive structure (step 310 of FIG. 3); and wherein the metal layer interacts with the silicide enhancing substance in the amorphized portion of the conductive structure so as to form a lower resistivity silicide on the conductive structure. The conductive structure is, preferably, comprised of: doped polysilicon, undoped polysilicon, epitaxial silicon, or any combination thereof. Preferably, the silicide enhancing substance is comprised of: molybdenum, Co, W, Ta, Nb, Ru, Cr, any refractory metal, and any combination thereof.Type: ApplicationFiled: July 2, 1998Publication date: April 18, 2002Inventors: JORGE KITTL, QI-ZHONG HONG
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Patent number: 6368925Abstract: An epi-channel of a uniform shape is formed by adjusting the temperature and pressure of H2 bake process to prevent the etching of a separation oxide at an interface of an active region and a field region thereby ensuring that an epi-channel is formed having a uniform shape.Type: GrantFiled: June 15, 2001Date of Patent: April 9, 2002Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Dae Hee Weon, Seung Ho Hahn
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Publication number: 20020004249Abstract: A semiconductor memory device is manufactured by uniformly forming an epitaxial capacitor layer on the whole surface of a single-crystal semiconductor layer, finely dividing the capacitor layer into individual capacitors by etching, using the individual capacitors as a mask to etch the single-crystal semiconductor layer and forming semiconductor columnar portions, and preparing vertical field effect transistors each having a channel portion in the semiconductor columnar portion. Thereby, the vertical field effect transistor can be formed under the epitaxial capacitor in a self aligning manner.Type: ApplicationFiled: June 29, 2001Publication date: January 10, 2002Inventor: Takashi Kawakubo
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Publication number: 20010044177Abstract: The object of this invention is to provide a method by which to form molecule recognizing films on sensor electrodes efficiently, within a short period, uniformly and in a high quality state. Another object of this invention is to provide a method by which to accurately introduce a vast number of biological samples for evaluation to the plural minute sensor electrode dots within a short period and efficiently.Type: ApplicationFiled: June 1, 2001Publication date: November 22, 2001Inventors: Hitoshi Fukushima, Tatsuya Shimoda, Hywel Morgan
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Patent number: 6316303Abstract: A method of fabricating a MOS transistor having SEG Si. After the formation of a gate and a spacer and before a source/drain region is formed, a selective epitaxial growth (SEG) Si is deposited over the substrate. The spacer is then removed to form an ultra shallow junction in the exposed substrate covered by the spacer after the formation of the SEG Si.Type: GrantFiled: February 15, 2000Date of Patent: November 13, 2001Assignee: United Microelectronics Corp.Inventors: Tony Lin, Chien-Chao Huang, Ming-Yin Hao
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Patent number: 6303441Abstract: A semiconductor device and a method for fabricating the same is disclosed, which minimizes device degradation, minimizes noises, and simplifies the fabrication process. The device includes a substrate having a first semiconductor layer, a buried insulating film, and a second semiconductor layer stacked; a field oxide film for separating the second semiconductor layer into a first region and a second region; a recess region formed in a particular region of the second region; gate insulating films and gate electrodes formed in stacks on each of a particular region in the first region and the recess region in the second region; first impurity regions formed in surfaces of the second semiconductor layer on both sides of the gate electrode in the first region; and second impurity regions formed in surfaces of the second semiconductor layer on both sides of the gate electrode in the recess region in the second region so that the second semiconductor layer below the gate electrode is fully depleted.Type: GrantFiled: May 7, 1999Date of Patent: October 16, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Young June Park, Jong Ho Lee, Hyeok Jae Lee
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Patent number: 6287924Abstract: Sidewall spacers extending above a silicon gate with the distance between the spacers exceeding the length of the gate are used to confine selective silicon growth of the gate and subsequent self-aligned silicidation.Type: GrantFiled: September 28, 1999Date of Patent: September 11, 2001Assignee: Texas Instruments IncorporatedInventors: Chih-Ping Chao, Ih-Chin Chen, Rick L. Wise, Katherine E. Violette, Sreenath Unnikrishnan
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Patent number: 6287969Abstract: Disclosed herein is a method of forming a superconductor, comprising the steps of: providing a substrate and exposing the substrate to a first atmosphere, including precursors to form a first epitaxial layer segment. The first layer segment is then exposed to a second atmosphere, including precursors to form a second epitaxial layer segment, and the second layer segment is exposed to a third atmosphere including precursors to form a third epitaxial layer segment. Each of the first and third layer segments are each formed from a superconductor material and the second layer segment is formed from a material different from the first and third layer segments and the first, second and third layer segments have a collective thickness, the third layer segment having an outer surface with a roughness which is less than that of a single layer of the superconductor material with a thickness equal to the collective thickness.Type: GrantFiled: May 6, 1999Date of Patent: September 11, 2001Assignee: McMaster UniversityInventors: Robert A. Hughes, Patrick J. Turner, John S Preston
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Patent number: 6248620Abstract: A method for fabricating field effect-controlled semiconductor components, such as e.g. but not exclusively MIS power transistors. The field effect-controllable semiconductor component has a semiconductor substrate of a first conductivity type and a gate insulator layer on the surface of the semiconductor substrate. A well of a second conductivity type is produced in the semiconductor substrate by implanting first impurity atoms. A semiconductor layer having a first predetermined thickness is produced on the gate insulator layer prior to the production of the well. The semiconductor layer is reduced in a predtdermined region to obtain a residual layer having a second predetermined thickness, such that the semiconductor layer acts as an implantation barrier outside the predetermined region when the well is produced.Type: GrantFiled: January 24, 2000Date of Patent: June 19, 2001Assignee: Infineon Technologies AGInventors: Helmut Strack, Helmut Gassel, Joost Larik
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Patent number: 6225230Abstract: Disclosed is a method of forming an element isolation insulating film by STI (shallow trench isolation) method, which permits effectively preventing a concave portion from being formed in an edge of the element isolation insulating film, permits decreasing the number of treating steps, and also permits facilitating the formation of the element isolation insulating film with a high yield. In forming the element isolation insulating film, a groove is formed in a surface region of a semiconductor substrate, followed by forming an insulating film on the entire surface to fill at least the groove. Then, a flattening treatment is applied at least once to remove the insulating film from the substrate surface such that the insulating film is left unremoved only within the groove. In place of a wet etching treatment, a mirror-polishing method is employed for the last flattening treatment.Type: GrantFiled: May 22, 1997Date of Patent: May 1, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Nitta, Yusuke Kohyama
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Patent number: 6165826Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode.Type: GrantFiled: December 29, 1995Date of Patent: December 26, 2000Assignee: Intel CorporationInventors: Robert S. Chau, Chia-Hong Jan, Chan-Hong Chern, Leopoldo D. Yau
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Patent number: 6162689Abstract: High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. Emdodiments include forming field oxide regions, gates, spacers, and lightly doped implants, and then depositing a layer of oxide on a substrate. The oxide layer is masked to protect portions of the oxide layer located near the gate, where it is desired to have a shallow junction, then etched to expose portions of the intended source/drain regions where the silicided contacts are to be formed. A high-dosage source/drain implant is thereafter carried out to form deep source/drain junctions with the substrate where the oxide layer has been etched away, and to form shallower junctions near the gates, where the implant must travel through the oxide layer before reaching the substrate. A layer of cobalt is thereafter deposited and silicidation is performed to form metal silicide contacts over only the deep source/drain junctions, while the cobalt on the oxide layer (i.e.Type: GrantFiled: November 6, 1998Date of Patent: December 19, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Nick Kepler, Karsten Wieczorek, Larry Wang, Paul Raymond Besser
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Patent number: 6159822Abstract: A method for implementing self-planarized shallow trench isolation in an integrated circuit. A planarized insulator oxide layer is formed after shallow trench isolation is etched and insulator oxide layer is deposited and etched back. The corners of silicon nitride layer over active area are exposed after the etch back step. Then, a silicon nitride cap layer is deposited. A non-critical photoresist patterning is used to expose the bigger active regions. Afterward, the cap layer on the bigger active regions is removed. Then, the insulator oxide layer under the cap layer is removed by wet etch after stripping of photoresist. Subsequently, wet etch is used to remove the cap layer and the silicon nitride layer. Finally, the self-planarized shallow trench isolation processes are completed after the pad oxide is removed.Type: GrantFiled: June 2, 1999Date of Patent: December 12, 2000Assignee: Vanguard International Semiconductor CorporationInventors: Fu-Liang Yang, Chung-Ju Lee, Meow-Ru Sheu
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Patent number: 6136637Abstract: A method for forming CMOS DRAM circuitry is disclosed and which includes forming a substrate comprising an array NMOS region, a peripheral NMOS region, and a peripheral PMOS region; forming a pair of insulated and spaced gate lines in the array NMOS region; forming at least one electrically conductive plug in the array NMOS region and which spans between the pair of gate lines; forming a barrier layer over the pair of gate lines in the array NMOS region, the peripheral NMOS and the peripheral PMOS region; and patterning and etching in the peripheral PMOS region to form peripheral PMOS region gate lines including removing a portion of the barrier layer in the PMOS peripheral region and leaving barrier layer material in the NMOS region masking over the electrically conductive plugType: GrantFiled: July 28, 1998Date of Patent: October 24, 2000Assignee: Micron Technology, Inc.Inventors: Aftab Ahmad, David J. Keller, Tyler A. Lowrey
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Patent number: 6130132Abstract: The following steps are used to form a split gate electrode MOS FET device. Form a tunnel oxide layer over a semiconductor substrate. Over the tunnel oxide layer, form a doped first polysilicon layer with a top surface upon which a native oxide forms. Then as an option, remove the native oxide layer. On the top surface of the first polysilicon layer, form a silicon nitride layer and etch the silicon nitride layer to form it into a cell-defining layer. Form a polysilicon oxide dielectric cap over the top surface of the first polysilicon layer. Aside from the polysilicon oxide cap, etch the first polysilicon layer and the tunnel oxide layer to form a floating gate electrode stack in the pattern of the masking cap forming a sharp peak on the periphery of the floating gate electrode. Form spacers on the sidewalls of the gate electrode stack. Then form blanket inter-polysilicon dielectric and blanket control gate layers covering exposed portions of the substrate and covering the stack.Type: GrantFiled: April 6, 1998Date of Patent: October 10, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Ta Hsieh, Hung-Cheng Sung, Yai-Fen Lin, Di-Son Kuo
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Patent number: 6110803Abstract: A method for fabricating a high-bias device is provided. The method contains forming an N-type epitaxial silicon layer over a P-type substrate. At least a first stacked double well is formed in the epitaxial silicon layer at a region, where a field oxide (FOX) structure is to be formed. A second stacked double well is formed in the epitaxial silicon layer at a region, where a source region is to be formed inside. A FOX structure is formed on the first stacked double well. A gate oxide layer is formed on the epitaxial silicon layer. A conductive gate layer is formed over the substrate to cover a region extending from a portion of the FOX structure to a portion of the second stacked double well. A source region is formed in the second stacked double well with the second-type dopant. A drain region is formed in the epitaxial silicon layer at the opposite side of the FOX layer.Type: GrantFiled: December 10, 1998Date of Patent: August 29, 2000Assignee: United Microelectronics Corp.Inventor: Ming-Tsung Tung
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Patent number: 6103575Abstract: A flash memory cell formed in a semiconductor substrate. The memory cell comprises: (a) a gate oxide formed atop said semiconductor substrate, said gate oxide including a thin region and a thick region; (b) a floating gate formed atop said thin region; (c) a control gate formed atop said thick region; (d) a drain region formed under said thin region and within said floating gate; (e) a source region formed under said thick region and outside said control gate; and (f) an insulating dielectric layer between said control gate and said floating gate.Type: GrantFiled: August 20, 1999Date of Patent: August 15, 2000Assignee: Worldwide Semiconductor Manufacturing CorporationInventor: Ko-Hsing Chang
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Patent number: 6100125Abstract: An ESD protection device including a transistor structure with resistive regions located within active areas thereof. The transistor structure is formed of one or more MOS transistors, preferably N-type MOS transistors. The drain regions of the transistors are modified to reduce the conductivity of those resistive regions by preventing high carrier concentration implants in one or more sections of the drain regions. This is achieved by modifying an N LDD mask and the steps related thereto, as well as a silicide exclusion mask and the steps related thereto. The modifications result in the omission of N LDD dopant from the area immediately adjacent to the underlying channel. In addition, portions of a spacer oxide remain over the drain region to be formed. Subsequent implant and siliciding steps are effectively blocked by the spacer oxide that remains, leaving a low-density drain (LDD) charge carrier concentration in those regions, except where omitted.Type: GrantFiled: September 25, 1998Date of Patent: August 8, 2000Assignee: Fairchild Semiconductor Corp.Inventors: Ronald Brett Hulfachor, Steven Leibiger, Michael Harley-Stead, Daniel James Hahn
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Patent number: 6043114Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.Type: GrantFiled: September 22, 1997Date of Patent: March 28, 2000Assignee: Hitachi, Ltd.Inventors: Hiroto Kawagoe, Tatsumi Shirasu, Shogo Kiyota, Norio Suzuki, Eiichi Yamada, Yuji Sugino, Manabu Kitano, Yoshihiko Sakurai, Takashi Naganuma, Hisashi Arakawa
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Patent number: 6017785Abstract: A method of improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, an implant mask which has a variable permeability to implanted impurities is formed on the surface of a substrate having a first dopant region. A first portion of the implant mask overlies a first portion of the first dopant region. The structure is subjected to high energy implantation which forms a heavily doped region. A first portion of the heavily doped region is located along the lower boundary of the first dopant region. A second portion of the heavily doped region which extends along a side boundary of the first dopant region is formed by impurity ions which pass through the first portion of the implant mask. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.Type: GrantFiled: August 15, 1996Date of Patent: January 25, 2000Assignee: Integrated Device Technology, Inc.Inventors: Chung-Chyung Han, Jeong Yeol Choi, Cheun-Der Lien
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Patent number: 6010929Abstract: A process for forming high voltage and low voltage transistors on the same substrates includes first forming a poly gate (16) over layer gate oxide (10) on a substrate (12). An LDD implant is then performed, followed by the formation of a nitride cap (30) over the gate (16). The cap (30) is not disposed over gate electrodes associated with low voltage transistors. Thereafter, the source/drain implant is performed which forms source/drain regions (40) and (42). The cap (30) prevents the introduction of dopants into the gate electrode (16) during the source/drain implant step. This effectively increases the gate oxide width due to a larger depletion region at the oxide/polysilicon gate boundary as compared to the low voltage transistors with the higher dopant levels and the gate electrode.Type: GrantFiled: December 11, 1997Date of Patent: January 4, 2000Assignee: Texas Instruments IncorporatedInventor: Richard A. Chapman
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Patent number: 5976925Abstract: A semiconductor device having asymmetrically-doped gate electrode and active region and a process of fabricating such a device is provided. According to one embodiment of the invention, a polysilicon layer is formed over the substrate. The polysilicon layer is then implanted with a first dopant to form a doped polysilicon layer. Portions of the doped polysilicon layer are then removed to form at least one gate electrode. Active regions of the substrate adjacent the gate electrode are implanted with a second dopant to form source/drain regions in the substrate. In this manner, the implant used to form the source/drain regions may be decoupled from the implant used to form the gate electrode. This, for example, allows for shallower source/drain regions to be formed without the formation of the depletion layer in the gate electrode.Type: GrantFiled: December 1, 1997Date of Patent: November 2, 1999Assignee: Advanced Micro DevicesInventors: Jon Cheek, Derick J. Wristers, James F. Buller
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Patent number: 5953604Abstract: A structure for a complementary field effect transistor includes a semiconductor body having a first body region of a first conductivity type and an adjoining second body region of an opposite second conductivity type. A buried dielectric region is located in the semiconductor body beneath the upper semiconductor surface and extends into the first and second body regions. A first drain region of the second conductivity type is located in the semiconductor body and adjoins the first body region, the dielectric region and the upper semiconductor surface. A second drain region of the first conductivity type is located in the semiconductor body and adjoins the second body region, the dielectric region and the upper semiconductor surface. The two drain regions are adjacent to one another.Type: GrantFiled: September 13, 1996Date of Patent: September 14, 1999Assignee: Integrated Device Technology, Inc.Inventor: Chuen-Der Lien
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Patent number: 5885876Abstract: A Fermi-FET includes a drain field termination region between the source and drain regions, to reduce and preferably prevent injection of carriers from the source region into the channel as a result of drain bias. The drain field terminating region prevents excessive drain induced barrier lowering while still allowing low vertical field in the channel. The drain field terminating region is preferably embodied by a buried counterdoped layer between the source and drain regions, extending beneath the substrate surface from the source region to the drain region. The buried counterdoped layer may be formed using a three tub structure which produces three layers between the spaced apart source and drain regions. The drain field terminating region may also be used in a conventional MOSFET. The channel region is preferably formed by epitaxial deposition, so that the channel region need not be counterdoped relative to the drain field terminating region.Type: GrantFiled: July 29, 1997Date of Patent: March 23, 1999Assignee: Thunderbird Technologies, Inc.Inventor: Michael W. Dennen
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Patent number: 5854509Abstract: Ordinary anisotropic etching is performed up to a depth (d1) while anisotropic etching is performed to form an inward taper from the depth (d1) by changing etching conditions such as components in a vapor phase and the temperature of a silicon substrate (1), thereby forming a groove (20). Thereafter silicon is epitaxially grown in the groove (20), thereby forming an epitaxial silicon layer (4). An NMOS transistor is formed on an upper layer part of the epitaxial silicon layer (4). At this time, the taper of the groove (20) is located under a part of an n.sup.+ layer (8) forming the NMOS transistor. Thus, a method of fabricating a semiconductor device capable of performing element isolation with neither halation nor formation of bird's beak in fabrication while minimizing a leakage current flowing across elements is obtained.Type: GrantFiled: May 2, 1996Date of Patent: December 29, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tatsuya Kunikiyo
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Patent number: 5783469Abstract: A method of fabricating an integrated circuit in which nitrogen is incorporated into the gate dielectric and transistor gate. The method comprises the providing of a semiconductor substrate that has a p-well and a laterally displaced n-well, each including a channel region laterally displaced between a pair of source/drain regions. Preferably, the semiconductor substrate has a resistivity of approximately 10 to 15 .OMEGA.-cm. A dielectric layer is formed on an upper surface of the semiconductor substrate. The formation of the dielectric layer preferably comprises a thermal oxidation performed at a temperature of approximately 600.degree. to 900.degree. C. and the resulting thermal oxide has a thickness less than approximately 50 angstroms. A conductive gate layer is then formed on the dielectric layer. In a preferred embodiment, the conductive gate layer is formed by chemically vapor depositing polysilicon at a pressure of less than approximately 2 torrs at a temperature in the range of approximately 500.Type: GrantFiled: December 10, 1996Date of Patent: July 21, 1998Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, Mark C. Gilmer
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Patent number: 5624858Abstract: A low concentration impurity region 6 of a second conductivity type is formed to cover lower portion of a high concentration impurity region 8 of the second conductivity type. Consequently, impurity concentration gradient between the high concentration impurity region 8 of the second conductivity type and the low concentration impurity layer 2 of a first conductivity type can be made moderate to relax the electric field, which leads to provision of higher breakdown voltage of the semiconductor device. Further, the depth of impurity diffusion of the low concentration impurity region 6 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type is made at least three times the depth of impurity diffusion of the high concentration impurity region 8 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type.Type: GrantFiled: December 21, 1995Date of Patent: April 29, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tomohide Terashima
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Patent number: 5622885Abstract: An integrated circuit includes an N isolation buried layer underlying high density and low voltage type P channel and N channel transistors to define islands of arbitrary voltage on the substrate. Thus such transistors, which otherwise are capable only of low voltage operation, become capable of operating at high voltage relative to the substrate. This allows integration, on a single chip, of high voltage circuit elements with low voltage and high density transistors all formed by the same fabrication process sequence. In one example this allows creation of an 18 volt range charge pump using a CMOS process which normally provides only 3 volt operating range transistors. This then allows integration on a single integrated circuit chip of a complex digital logic function such as a UART (universal asynchronous receiver and transmitter) with a high voltage function such as an RS-232 interface, including integrated capacitors for the RS-232 interface charge pump.Type: GrantFiled: June 7, 1995Date of Patent: April 22, 1997Assignee: National Semiconductor CorporationInventors: Richard B. Merrill, Whu-ming Young