Utilizing Gate Sidewall Structure Patents (Class 438/230)
  • Patent number: 10515809
    Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yasutoshi Okuno, Teng-Chun Tsai, Ziwei Fang, Fu-Ting Yen
  • Patent number: 10388562
    Abstract: A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haigou Huang, Daniel Jaeger, Xusheng Wu, Jinsheng Gao
  • Patent number: 9991364
    Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee
  • Patent number: 9947790
    Abstract: A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region with a gate insulating film therebetween; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: April 17, 2018
    Assignee: SONY CORPORATION
    Inventors: Satoru Mayuzumi, Hitoshi Wakabayashi
  • Patent number: 9812369
    Abstract: A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: November 7, 2017
    Assignee: Infineon Technologies AG
    Inventors: Frank Hoffmann, Dirk Manger, Andreas Pribil, Marc Probst, Stefan Tegen
  • Patent number: 9673294
    Abstract: According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: June 6, 2017
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Dmitri Alex Tschumakow, Claus Dahl, Armin Tilke
  • Patent number: 9412842
    Abstract: A gate pattern is formed on a first region of a substrate. An epitaxial layer is formed on a second region of the substrate. A recess is formed in the second region of the substrate by etching the epitaxial layer and the substrate underneath. The first region is adjacent to the second region.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: August 9, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Bum Kim, Kyung-Bum Koo, Taek-Soo Jeon, Tae-Ho Cha, Judson R Holt, Henry K Utomo
  • Patent number: 9397219
    Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in the device, and a method of manufacturing the device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region. The gate structure includes a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: July 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-hoon Kim, Jin-bum Kim, Kwan-heum Lee, Byeong-chan Lee, Cho-eun Lee, Su-jin Jung
  • Patent number: 9368513
    Abstract: A semiconductor device includes a semiconductor material positioned above a substrate and a gate structure positioned above a surface of the semiconductor material, the gate structure covering a non-planar surface portion of the surface. A sidewall spacer is positioned adjacent to the gate structure and includes first dopants having one of an N-type and a P-type conductivity, wherein the sidewall spacer covers an entire sidewall surface of the gate structure and partially covers the surface of the semiconductor material. Source/drain extension regions that include the first dopants are positioned within the non-planar surface portion and in alignment with the sidewall spacer, wherein a concentration of the first dopants within a portion of the sidewall spacer proximate the non-planar surface portion substantially corresponds to a concentration of the first dopants within the source/drain extension regions proximate the non-planar surface portion.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: June 14, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Gerd Zsch├Ątzsch, Stefan Flachowsky, Dominic Thurmer
  • Patent number: 9331072
    Abstract: Integrated circuit devices having a cavity and methods of manufacturing the integrated circuit devices are provided. The integrated circuit devices may include a pair of spacers, which define a recess. The integrated circuit device may also include a lower conductive pattern in the recess and an upper conductive pattern on the lower conductive pattern. The upper conductive pattern may have an etch selectivity with respect to the lower conductive pattern and may expose an upper surface of the lower conductive pattern adjacent a sidewall of the upper conductive pattern. An inner sidewall of one of the pair of spacers, the upper surface of the lower conductive pattern and the sidewall of the upper conductive pattern may define a space and a capping pattern may be formed on the upper conductive pattern to seal a top portion of the space, such that a cavity is disposed under the capping pattern.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: May 3, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-Ill Seo, Jin-Wook Lee
  • Patent number: 9324883
    Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.
    Type: Grant
    Filed: September 7, 2014
    Date of Patent: April 26, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kota Funayama, Hiraku Chakihara, Yasushi Ishii
  • Patent number: 9312369
    Abstract: According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: April 12, 2016
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Dmitri Alex Tschumakow, Claus Dahl, Armin Tilke
  • Patent number: 9306033
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a substrate. A spacer is formed adjoining a sidewall of the gate stack. A recess is formed between the spacer and the substrate. Then, a strained feature is formed in the recess. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Fu Cheng
  • Patent number: 9293557
    Abstract: Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Alfred Grill, Deborah A. Neumayer, Dae-Gyu Park, Norma E. Sosa, Min Yang
  • Patent number: 9142651
    Abstract: One method disclosed includes, among other things, covering a top surface and a portion of the sidewalls of a fin with etch stop material, forming a sacrificial gate structure above and around the fin, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one process operation to remove the sacrificial gate structure and thereby define a replacement gate cavity, forming a counter-doped region in the fin below an upper surface of the fin and below the channel region of the device, wherein the counter-doped region is doped with a second type of dopant material that is of an opposite type relative to the first type of dopant material, and forming a replacement gate structure in the replacement gate cavity.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: September 22, 2015
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 9136329
    Abstract: Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Tsung Huang, Kuo-Cheng Wu, Carlos H. Diaz
  • Patent number: 9099335
    Abstract: Embodiments include a semiconductor device comprising: a substrate; a first transistor formed on the substrate; and a second transistor formed on the substrate, wherein a common region of the semiconductor device forms (i) a drain region of the first transistor, and (ii) a source region of the second transistor, and wherein a gate region of the first transistor is electrically coupled to a gate region of the second transistor.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: August 4, 2015
    Assignee: Marvell World Trade Ltd.
    Inventor: Albert Wu
  • Patent number: 9064728
    Abstract: The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS gates, NMOS gates, memory cells, P+ active areas, and N+ active areas. These structures are fabricated through the use of multiple masking processes, which may cause shorts when a buried digit layer is deposited if the masking processes are misaligned. Accordingly, a dielectric etch stop layer, such as aluminum oxide Al2O3 or silicon carbide SiC, may be utilized in the array to prevent shorts between the wordlines, active areas, and the buried digit layer when the contacts are misaligned.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: June 23, 2015
    Assignee: Micron Technology, Inc.
    Inventor: H. Montgomery Manning
  • Publication number: 20150140751
    Abstract: Circuit fabrication methods are provided which include, for example: providing the circuit structure with at least one gate structure extending over a first region and a second region of a substrate structure, the at least one gate structure including a capping layer; and modifying an etch property of at least a portion of the capping layer of the at least one gate structure, where the modified etch property inhibits etching of the at least one gate structure during a first etch process facilitating fabrication of at least one first transistor in the first region and inhibits etching of the at least one gate structure during a second etch process facilitating fabrication of at least one second transistor in the second region.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hong YU, Huang LIU, Lun ZHAO, Richard J. CARTER
  • Patent number: 9035381
    Abstract: An aspect of the present embodiment, there is provided a semiconductor device includes a high-voltage element, the high-voltage element including a substrate, a first semiconductor region with a first conductive type on the substrate, an insulating isolation film on the substrate, a second semiconductor region with a second conductive type, the second semiconductor region being provided between the first semiconductor region and the insulating isolation film, a drain region with the second conductive type provided on a surface of the second semiconductor region, an impurity concentration of the drain region being higher than an impurity concentration of the second semiconductor region, a source region with the second conductive type provided on a surface of the first semiconductor, the source region being separated from the drain region, a floating drain region with the second conductive type provided on the surface of the first semiconductor region between the second semiconductor region and the source regio
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 19, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Osamu Takata
  • Patent number: 9029214
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the non-conformal spacer material. The method etches the non-conformal spacer material and protection mask to form a salicidation spacer. Further, a self-aligned silicide contact is formed adjacent the salicidation spacer.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: May 12, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Jan Hoentschel, Stefan Flachowsky, Nicolas Sassiat, Ran Yan
  • Patent number: 9029930
    Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
  • Patent number: 9023698
    Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Huajie Chen, Dureseti Chidambarrao, Omer H. Dokumaci
  • Patent number: 9024388
    Abstract: One illustrative method disclosed herein includes forming replacement gate structures for an NMOS transistor and a PMOS transistor by forming gate insulation layers and a first metal layer for the devices from the same materials and selectively forming a metal-silicide material layer only on the first metal layer for the NMOS device but not on the PMOS device. One example of a novel integrated circuit product disclosed herein includes an NMOS device and a PMOS device wherein the gate insulation layers and the first metal layer of the gate structures of the devices are made of the same material, the gate structure of the NMOS device includes a metal silicide material positioned on the first metal layer of the NMOS device, and a second metal layer that is positioned on the metal silicide material for the NMOS device and on the first metal layer for the PMOS device.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: May 5, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kisik Choi, Ruilong Xie
  • Patent number: 9023726
    Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: May 5, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Wei Cheng, Ming Sheng Xu, Duan Quan Liao, Yikun Chen, Ching Hwa Tey
  • Patent number: 9006058
    Abstract: A method for fabricating a semiconductor device is described. A semiconductor substrate is provided, wherein the substrate has a first area and a second area. A first gate structure and a second gate structure are formed over the substrate in the first area and the substrate in the second area, respectively. A first spacer is framed on the sidewall of each gate structure. At least one etching process including at least one wet etching process is performed. The first spacer is removed. A second spacer is formed on the sidewall of each gate structure. A mask layer is formed in the second area. Ion implantation is formed using the mask layer, the first gate structure and the second spacer as a mask to form S/D extensions in the substrate beside the first gate structure in the first area. The mask layer is then removed.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: April 14, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tung-Ming Chen, Yu-Chun Huang, Shin-Chuan Huang, Chia-Jong Liu, I-Fang Huang
  • Patent number: 8962414
    Abstract: In aspects of the present disclosure, a reliable encapsulation of a gate dielectric is provided at very early stages during fabrication. In other aspects, a semiconductor device is provided wherein a reliable encapsulation of a gate dielectric material is maintained, the reliable encapsulation being present at early stages during fabrication. In embodiments, a semiconductor device having a plurality of gate structures is provided over a surface of a semiconductor substrate. Sidewall spacers are formed over the surface and adjacent to each of the plurality of gate structures, wherein the sidewall spacers cover sidewall surfaces of each of the plurality of gate structures.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: February 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Juergen Faul, Frank Jakubowski
  • Publication number: 20150050785
    Abstract: A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular example, a method of forming a CMOS device includes forming a first layer on an extension layer of a wafer, forming a first gate on a portion of the first layer, and forming an expansion region proximate to the extension layer. The method also includes removing a portion of the first gate to create a cavity and removing a portion of the first layer to extend the cavity to the extension layer.
    Type: Application
    Filed: September 25, 2014
    Publication date: February 19, 2015
    Inventors: Bin Yang, Xia Li, Jun Yuan
  • Publication number: 20150044831
    Abstract: A semiconductor process includes the following steps. A first gate and a second gate are formed on a substrate. A first stress layer is formed to cover the first gate and the second gate. The first stress layer covering the first gate is etched to form a first spacer beside the first gate, but reserves the first stress layer covering the second gate. A first epitaxial layer is formed beside the first spacer. The first stress layer and the first spacer are entirely removed. A second stress layer is formed to cover the first gate and the second gate. The second stress layer covering the second gate is etched to form a second spacer beside the second gate, but reserves the second stress layer covering the first gate. A second epitaxial layer is formed beside the second spacer. The second stress layer and the second spacer are entirely removed.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 12, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Cheng Tung, Chin-I Liao
  • Patent number: 8951868
    Abstract: A plurality of sacrificial gate structures is formed on substrate. A first set of sacrificial gate structures of the plurality of sacrificial gate structures contains a sacrificial spacer on sidewall surfaces thereof, and a second set of sacrificial gate structures of the plurality of sacrificial gate structures has bare sidewall surfaces. A dielectric spacer is provided to the first and second sets of sacrificial gate structures. Each sacrificial gate structure of the first and second sets is removed together with the sacrificial spacers providing first gate cavities in the area previously occupied by a sacrificial gate structure of the first set of sacrificial gate structures and the sacrificial spacer and second gate cavities in the area previously occupied by a sacrificial gate structure of the second set of sacrificial gate structures. A functional gate is formed in each of the first and second gate cavities.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventor: Sameer H. Jain
  • Publication number: 20150017768
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.
    Type: Application
    Filed: May 5, 2014
    Publication date: January 15, 2015
    Inventors: Clement Hsingjen Wann, Chih-Hao Chang, Shou Zen Chang, Chih-Hsin Ko, Yasutoshi Okuno, Andrew Joseph Kelly
  • Patent number: 8927350
    Abstract: An integration flow for LDD and spacer fabrication on a sacrificial amorphous carbon gate structure, form first spacer by way of depositing on the si substrate which have gate structure first. Gate is provided above the N-well and P-well on substrate. Spin coating a layer of photoresist in the first spacer, patterning the photoresist, and the gate structure above the N-well or P-well is exposed, ion lightly dope treatment is then used to the whole device. Remove the redundant photoresist and the first spacer layer, form the second spacer layer by depositing on the surface of the si substrate and gate, and spin coating another photoresist layer on the second spacer layer. Pattern the another photoresist layer, and another side of the gate structure is exposed, ion lightly dope treatment is then used to the whole device. Remove the redundant photoresist and the second spacer layer, form the third spacer layer and SiN layer by depositing on the gate and the Si substrate in turn.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: January 6, 2015
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: Chunsheng Zheng
  • Patent number: 8928040
    Abstract: A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics).
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: January 6, 2015
    Assignee: SK Hynix Inc.
    Inventor: Kyung Do Kim
  • Patent number: 8921179
    Abstract: Methodology enabling a reduction of edge and strap cell size, and the resulting device are disclosed. Embodiments include: providing first and second NW regions on a substrate; providing first and second RX regions on the first and second NW regions, respectively; providing a contact on the substrate connecting the first and second RX regions; and providing a dummy PC on the substrate connecting the first and second RX regions. Other embodiments include: determining an RX region of an IC design; determining a PPLUS mask region extending along a horizontal direction and being on an entire upper surface of the RX region; determining a NW region extending along a vertical direction and separated from the RX region; and comparing an area of an overlap of the NW region and PPLUS mask region to a threshold value.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: December 30, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Bipul C. Paul, Anurag Mittal, Pierre Malinge
  • Patent number: 8921178
    Abstract: Improved formation of replacement metal gate transistors is obtained by utilizing a silicon to metal substitution reaction. After removing the dummy gate, a gate dielectric and work function metal are deposited. The work function metal is deposited to a different thickness for the P-channel transistors than for the N-channel transistors. A sacrificial polysilicon gate is then formed, which is caused to undergo substitution with a metal such as aluminum.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: December 30, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Kenzo Manabe
  • Patent number: 8916428
    Abstract: A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming spacers adjoining sidewalls of the gate stacks, wherein at least one of the spacers extends beyond an edge the isolation feature. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsan-Chun Wang, Chun Hsiung Tsai
  • Patent number: 8906759
    Abstract: A method of forming a FinFET structure which includes forming fins on a semiconductor substrate; forming a gate wrapping around at least one of the fins, the gate having a first surface and an opposing second surface facing the fins; depositing a hard mask on a top of the gate; angle implanting nitrogen into the first and second surfaces of the gate so as to form a nitrogen-containing layer in the gate that is below and in direct contact with the hard mask on top of the gate; forming spacers on the gate and in contact with the nitrogen-containing layer; and epitaxially depositing silicon on the at least one fin so as to form a raised source/drain. Also disclosed is a FinFET structure.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Sanjay Mehta, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8900956
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
  • Patent number: 8900957
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
  • Patent number: 8900944
    Abstract: A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-Yeon Jeong, Myeong-Cheol Kim, Do-Hyoung Kim, Do-Haing Lee, Nam-Myun Cho, In-Ho Kim
  • Patent number: 8895384
    Abstract: A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Unoh Kwon, Ramachandran Muralidhar, Viorel Ontalus
  • Patent number: 8890258
    Abstract: A method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method further includes depositing a stress film over the NMOS gate structure, performing an annealing process, and removing the stress film.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsan-Chun Wang, Ziwei Fang
  • Patent number: 8884344
    Abstract: Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface of the gate, depositing an insulating layer above the semiconductor device, and planarizing the insulating layer using the blocking region as a planarization stop. Embodiments further include semiconductor devices having a semiconductor substrate, a gate above the semiconductor substrate, a source/drain region adjacent to the gate, a gate cap above the gate that cover the full width of the gate, and a contact adjacent to the source/drain region having a portion of its sidewall defined by the gate cap.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: November 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan, Thomas N. Adam
  • Patent number: 8883582
    Abstract: During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: November 11, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Uwe Griebenow, Katrin Reiche, Heike Berthold
  • Patent number: 8877581
    Abstract: An integrated circuit (IC) includes a plurality of strained metal oxide semiconductor (MOS) devices that include a semiconductor surface having a first doping type, a gate electrode stack over a portion of the semiconductor surface, and source/drain recesses that extend into the semiconductor surface and are framed by semiconductor surface interface regions on opposing sides of the gate stack. A first epitaxial strained alloy layer (rim) is on the semiconductor surface interface regions, and is doped with the first doping type. A second epitaxial strained alloy layer is on the rim and is doped with a second doping type that is opposite to the first doping type that is used to form source/drain regions.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Amitabh Jain, Deborah J. Riley
  • Patent number: 8872244
    Abstract: After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Chiahsun Tseng, Chun-chen Yeh, Yunpeng Yin
  • Patent number: 8871625
    Abstract: A method of fabricating a spacer structure which includes forming a dummy gate structure comprising a top surface and sidewall surfaces over a substrate and forming a spacer structure over the sidewall surfaces. Forming the spacer structure includes depositing a first oxygen-sealing layer on the dummy gate structure and removing a portion of the first oxygen-sealing layer on the top surface of the dummy gate structure, whereby the first oxygen-sealing layer remains on the sidewall surfaces. Forming the spacer structure further includes depositing an oxygen-containing layer on the first oxygen-sealing layer and the top surface of the dummy gate structure. Forming the spacer structure further includes depositing a second oxygen-sealing layer on the oxygen-containing layer and removing a portion of the second oxygen-sealing layer over the top surface of the dummy gate structure. Forming the spacer structure further includes thinning the second oxygen-sealing layer.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Ryan Chia-Jen Chen
  • Patent number: 8871622
    Abstract: A semiconductor device includes a substrate that has a surface. The semiconductor further includes a fin disposed on the surface and including a semiconductor member. The semiconductor further includes a spacer disposed on the surface, having a type of stress, and overlapping the semiconductor member in a direction parallel to the surface. A thickness of the spacer in a direction perpendicular to the surface is less than a height of the semiconductor member in the direction perpendicular to the surface.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: October 28, 2014
    Assignees: Semicondoctor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Wayne Bao
  • Patent number: 8853036
    Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.
    Type: Grant
    Filed: December 21, 2013
    Date of Patent: October 7, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kota Funayama, Hiraku Chakihara, Yasushi Ishii
  • Patent number: 8841181
    Abstract: A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: September 23, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ying-Hung Chou, Shao-Hua Hsu, Chi-Horn Pai, Zen-Jay Tsai, Shih-Hao Su, Chun-Chia Chen, Shih-Chieh Hsu, Chih-Chung Chen