Plural Doping Steps Patents (Class 438/231)
  • Patent number: 10522358
    Abstract: A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang, Shahaji B. More
  • Patent number: 10388698
    Abstract: A resistive memory includes a semiconductor substrate, a dielectric layer, an insulating layer and a metal electrode layer. The semiconductor substrate has a top surface and a recess extending downwards into the semiconductor substrate from the top surface. The dielectric layer is disposed on the semiconductor substrate and has a first through-hole aligning the recess. The insulating layer is disposed in the first through-hole and the recess. The metal electrode layer is disposed on the insulating layer by which the metal electrode layer is isolated from the semiconductor substrate.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: August 20, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Hao Tseng, Dai-Ying Lee, Erh-Kun Lai
  • Patent number: 10361319
    Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mirco Cantoro, Yeon-cheol Heo, Maria Toledano Luque
  • Patent number: 10326003
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a first gate spacer is formed over a dummy gate of a fin field effect transistor (finFET). The method also includes performing a carbon plasma doping of the first gate spacer. The method also includes forming a plurality of source/drain regions, where a source/drain region is disposed on opposite sides of the dummy gate. The method also includes removing dummy gate.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chen, Huicheng Chang, Liang-Yin Chen, Chun-Feng Nieh, Li-Ting Wang, Wan-Yi Kao, Chia-Ling Chan
  • Patent number: 10026837
    Abstract: An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS transistor without extension and without pocket implants and with SiGe source and drains. The distance from the SiGe source and drains to the gate of the first PMOS transistor is greater than the distance from the SiGe source and drains to the gate of the second PMOS transistor and the turn on voltage of the first PMOS transistor is at least 50 mV higher than the turn on voltage of the second PMOS transistor.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: July 17, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Younsung Choi, Deborah J. Riley
  • Patent number: 9922976
    Abstract: A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack is present on the first semiconductor channel. The second gate stack is present on the second semiconductor channel. The first gate stack and the second gate stack are different at least in tantalum nitride amount.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu Chen, Ming-Huei Lin, Chih-Pin Tsao, Shih-Hsun Chang
  • Patent number: 9847416
    Abstract: Disclosed are performance-enhanced vertical devices (e.g., vertical field effect transistors (FETs) or complementary metal oxide semiconductor (CMOS) devices, which incorporate vertical FETs) and methods of forming such devices. A strained dielectric layer is positioned laterally adjacent to the gate of a vertical FET, increasing the charge carrier mobility within the channel region and improving performance. In a vertical n-type FET (NFET), the strain is compressive to improve electron mobility given the direction of current within the vertical NFET; whereas, in a vertical p-type FET (PFET), the strain is tensile to improve hole mobility given the direction of current within the vertical PFET. Optionally, the orientation of a vertical FET relative to the surface plane of the semiconductor wafer on which it is formed is also preplanned as function of the type of FET (i.e., NFET or PFET) for optimal charge carrier mobility and, thereby enhanced performance.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: December 19, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Edward J. Nowak, Robert R. Robison, Brent A. Anderson
  • Patent number: 9831321
    Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate including at least one fin, at least one gate stack formed on a top surface of the at least one fin, a first inter-layer dielectric (ILD) layer formed on the top surface of the at least one fin, and a strained layer formed at least on a top surface of the at least one gate stack, wherein the strained layer is configured to provide a strain force to the at least one gate stack.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lun-Wei Chang, Yun-Ju Sun, Tomonari Yamamoto
  • Patent number: 9799566
    Abstract: A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack is present on the first semiconductor channel. The first gate stack includes a first work function layer and a first interposing layer present between the first semiconductor channel and the first work function layer. The second gate stack is present on the second semiconductor channel. The second gate stack includes a second work function layer and a second interposing layer present between the second semiconductor channel and the second work function layer. The first interposing layer and the second interposing layer are different at least in tantalum nitride amount.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: October 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shun-Jang Liao, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 9780002
    Abstract: Methodologies for patterning and implantation are provided Embodiments include forming fins; forming an SiN over the fins; forming an a-Si layer over the SiN; forming and patterning a first patterning layer over the a-Si layer; etching through the a-Si layer using the first patterning layer as a mask; removing the first patterning layer; implanting ions in exposed groups of fins; forming and patterning a second patterning layer to expose a first group of fins and a portion of the a-Si layer on opposite sides of the first group of fins; implanting ions in a first region of the first group of fins; forming a third patterning layer over the first region of the first group of fins and exposing a second region of the first group of fins; and implanting ions in the second region of the first group of fins.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: October 3, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xintuo Dai, Brian Greene, Mahender Kumar, Daniel J. Dechene, Daniel Jaeger
  • Patent number: 9761718
    Abstract: A semiconductor device includes: a sidewall insulating film; a gate electrode; source and drain regions; a first stress film; and a second stress film.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: September 12, 2017
    Assignee: SONY CORPORATION
    Inventor: Yuki Miyanami
  • Patent number: 9620507
    Abstract: An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: April 11, 2017
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Nicolas Loubet, Qing Liu, Prasanna Khare, Stephane Allegret-Maret, Bruce Doris, Kangguo Cheng
  • Patent number: 9620506
    Abstract: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: April 11, 2017
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Nicolas Loubet, Qing Liu, Prasanna Khare, Stephane Allegret-Maret, Bruce Doris, Kangguo Cheng
  • Patent number: 9620620
    Abstract: A method of preventing contact metal from protruding into neighboring gate devices to affect work functions of the neighboring gate devices is provided includes forming a gate structure. Forming the gate structure includes forming a work function layer, and forming a gate metal layer having a void, wherein the work function layer surrounds the gate metal layer. The method further includes forming a contact plug having a contact metal directly on the gate metal layer of the first gate stack, wherein the contact metal protrudes into the void, and the work function layer prevents the contact metal from protruding into a second gate stack.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: April 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Wee Teo, Ming Zhu, Chi-Ju Lee, Sheng-Chen Chung, Kai-Shyang You, Harry-Hak-Lay Chuang
  • Patent number: 9577098
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: February 21, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Patent number: 9570318
    Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric layer over at least a portion of the at least one fin. The method further includes forming a work function layer over at least a portion of the dielectric layer. The method further includes forming a source region or a drain region adjacent the at least one fin, and performing an anneal operation, wherein the anneal operation anneals the dielectric layer and either the source region or the drain region, and wherein the work function layer provides a protection function to the at least a portion of the dielectric layer during the anneal operation.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: February 14, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Jin Cho, MiaoMiao Wang, Hui Zang
  • Patent number: 9508598
    Abstract: To enhance reliability and performance of a semiconductor device that has a fully-depleted SOI transistor, while a width of an offset spacer formed on side walls of a gate electrode is configured to be larger than or equal to a thickness of a semiconductor layer and smaller than or equal to a thickness of a sum total of a thickness of the semiconductor layer and a thickness of an insulation film, an impurity is ion-implanted into the semiconductor layer that is not covered by the gate electrode and the offset spacer. Thus, an extension layer formed by ion implantation of an impurity is kept from entering into a channel from a position lower than the end part of the gate electrode.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: November 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Hidekazu Oda
  • Patent number: 9449883
    Abstract: First protective films are formed to cover side surfaces of gate electrode portions. In an nMOS region, an extention implantation region is formed by causing a portion of the first protective film located on the side surface of the gate electrode portion to function as an offset spacer and using the offset spacer as a mask, and then, cleaning is done. Since silicon nitride films are formed on surfaces of the first protective films, the resistance to chemical solutions is improved. Furthermore, second protective films are formed on the first protective films, respectively. In a pMOS region, an extention implantation region is formed by causing a portion of the first protective film and a portion of the second protective film located on the side surface of the gate electrode portion to function as an offset spacer and using the offset spacer as the mask, and then, cleaning is done.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: September 20, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hisayuki Kato, Yoshihiko Kusakabe
  • Patent number: 9431509
    Abstract: An integrated circuit containing metal replacement gates may be formed by forming a nitrogen-rich titanium-based barrier between a high-k gate dielectric layer and a metal work function layer of a PMOS transistor. The nitrogen-rich titanium-based barrier is less than 1 nanometer thick and has an atomic ratio of titanium to nitrogen of less than 43:57. The nitrogen-rich titanium-based barrier may be formed by forming a titanium based layer over the gate dielectric layer and subsequently adding nitrogen to the titanium based layer. The metal work function layer is formed over the nitrogen-rich titanium-based barrier.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 30, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroaki Niimi, James Joseph Chambers
  • Patent number: 9368353
    Abstract: A method comprises growing a channel layer comprising a first channel region and a second channel region, depositing a first hard mask layer over the channel layer, patterning the first hard mask layer, applying a first delta doping process to the first channel region to form a first delta doping layer over the first channel region, depositing a first cap layer over the first delta doping layer, depositing a second hard mask layer over the channel layer, wherein the first cap layer is embedded in the second hard mask layer, patterning the second hard mask layer and the first hard mask layer to expose the second channel region, applying a second delta doping process to the second channel region to form a second delta doping layer over the second channel region and applying a first diffusion process to the first delta doping layer and the second delta doping layer.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Martin Christopher Holland
  • Patent number: 9362402
    Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate; and forming a first gate structure on the semiconductor substrate. The method also includes forming offset spacers doped with a certain type of ions to increase an anti-corrosion ability of the offset spacers on both sides of the first gate structure by a stability doping process; and forming trenches in the semiconductor substrate at both sides of the first gate structures. Further, the method includes forming stress layers in the trenches.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: June 7, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Yonggen He
  • Patent number: 9318333
    Abstract: In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: April 19, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Vidyut Gopal, Shankar Sinha, Jean Yee-Mei Yang, Phillip L. Jones
  • Patent number: 9312188
    Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: April 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Youn Kim, Sang-Duk Park, Jae-Kyung Seo, Kwang-Sub Yoon, In-Gu Yoon
  • Patent number: 9269637
    Abstract: A TFT substrate includes: a substrate; and a plurality of TFTs, wherein each of the TFTs comprises: a gate electrode, disposed on the substrate; a gate insulating layer, disposed on the substrate and covering the gate electrode; a metallic oxide active layer, disposed on the gate insulating layer; a metallic oxide protection layer, disposed on the metallic oxide active layer; an etching stop layer, disposed on the metallic oxide protection layer, wherein a first through hole and a second through hole penetrate through the etching stop layer and the metallic oxide protection layer; and a source electrode and a drain electrode, disposed in the first through hole and the second through hole respectively, and electrically connected to the metallic oxide active layer.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: February 23, 2016
    Assignee: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Chin-Tzu Kao, Wen-Cheng Lu
  • Patent number: 9202915
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: December 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jeff J. Xu
  • Patent number: 9196708
    Abstract: Embodiments of a method for forming a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a sealing structure over a sidewall of the gate stack. The method also includes forming a dummy shielding layer over the semiconductor substrate, the sealing structure, and the gate stack. The method further includes performing an ion implantation process on the dummy shielding layer to form source and drain regions in the semiconductor substrate. In addition, the method includes removing the dummy shielding layer after the source and drain regions are formed.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: November 24, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Che-Cheng Chang, Yi-Jen Chen, Yung-Jung Chang
  • Patent number: 9184052
    Abstract: A method of manufacturing a semiconductor device using a metal oxide includes forming a metal oxide layer on a substrate, forming an amorphous semiconductor layer on the metal oxide layer, and forming a polycrystalline semiconductor layer by crystallizing the amorphous semiconductor layer using the metal oxide layer.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: November 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xianyu Wenxu, Woo-young Yang, Chang-youl Moon, Yong-young Park, Jeong-yub Lee
  • Patent number: 9147683
    Abstract: A dielectric material layer is deposited on gate structures of first and second semiconductor material portions. The dielectric material layer is anisotropically etched to form a first gate spacer on a first semiconductor material portion, while being protected above the second semiconductor material portion. After formation of first raised active regions on the first semiconductor material portion, a dielectric stack of a dielectric oxide liner and a dielectric nitride liner is formed. The dielectric stack is removed over the second semiconductor material portion and a second gate spacer is formed on the second semiconductor material portion, while the dielectric stack protects the first raised active regions. A second gate spacer is formed by anisotropically etching the dielectric material layer over the second semiconductor material portion. The first and second gate spacers have the same composition and thickness. Second raised active regions can be formed on the second semiconductor material portion.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: September 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 9142673
    Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One intermediate semiconductor device includes, for instance: a substrate with at least one fin with at least one channel; at least one gate over the channel; at least one hard-mask over the gate; and at least one spacer disposed over the gate and hard-mask. One method includes, for instance: obtaining an intermediate semiconductor device; forming at least one recess into the substrate, the recess including a bottom and at least one sidewall exposing a portion of the at least one fin; depositing a dielectric layer into the at least one recess; removing at least a portion of the dielectric layer to form a barrier dielectric layer; and performing selective epitaxial growth in the at least one recess over the barrier dielectric layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 22, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jin Ping Liu, Min-hwa Chi
  • Patent number: 9117926
    Abstract: A semiconductor device and a method of manufacturing the same is disclosed. In one aspect, the method comprises forming a first MOSFET having a first gate length in a semiconductor substrate, and forming a second MOSFET having a second gate length in the semiconductor substrate. Furthermore, the second gate length is less than the first gate length, and wherein the second MOSFET has a gate stack in the form of a spacer having a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor substrate.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: August 25, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Qingqing Liang
  • Patent number: 9105498
    Abstract: A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: August 11, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mohit Bajaj, Kota V. R. M. Murali, Rahul Nayak, Edward J. Nowak, Rajan K. Pandey
  • Patent number: 8999795
    Abstract: An asymmetrical field effect transistor (FET) device includes a semiconductor substrate, a buried oxide layer disposed on the semiconductor substrate, an extended source region disposed on the buried oxide layer and a drain region disposed on the buried oxide layer. The asymmetrical FET device also includes a silicon on insulator region disposed between the extended source region and the drain region and a gate region disposed above the extended source region and the silicon on insulator region.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8994117
    Abstract: A semiconductor chip having a P? substrate and an N+ epitaxial layer grown on the P? substrate is shown. A P? circuit layer is grown on top of the N+ epitaxial layer. A first moat having an electrically quiet ground connected to a first N+ epitaxial region is created by isolating the first N+ epitaxial region with a first deep trench. The first moat is surrounded, except for a DC path, by a second moat with a second N+ epitaxial region, created by isolating the second N+ epitaxial region with a second deep trench. The second moat may be arranged as a rectangular spiral around the first moat.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Joel T. Ficke, David M. Friend, James D. Strom, Erik S. Unterborn
  • Patent number: 8987081
    Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kazunobu Ota, Hirokazu Sayama, Hidekazu Oda
  • Patent number: 8988626
    Abstract: A liquid crystal display device and method for manufacturing the same are provided. A liquid crystal display (LCD) with a touch function includes: a pixel thin film transistor (TFT) in a display area, and a buffer TFT of a gate driver in a non-display area, wherein a lightly-doped drain (LDD) length of the buffer TFT is shorter than a lightly doped drain (LDD) length of the pixel TFT.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: March 24, 2015
    Assignee: LG Display Co., Ltd.
    Inventor: Sangwon Lee
  • Publication number: 20150072487
    Abstract: A method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method further includes depositing a stress film over the NMOS gate structure, performing an annealing process, and removing the stress film.
    Type: Application
    Filed: November 18, 2014
    Publication date: March 12, 2015
    Inventors: Tsan-Chun Wang, Ziwei Fang
  • Patent number: 8975704
    Abstract: A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jan Hoentschel, Shiang Yang Ong, Stefan Flachowsky, Thilo Scheiper
  • Publication number: 20150037946
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a fin protruding upwardly from or through a surface of a substrate, forming a to-be-sacrificed dummy gate enwrapping a first portion of the fin, forming a first insulating material layer so as to at least cover an exposed second portion of the fin, and selectively removing the dummy gate to thereby expose the first portion of the first semiconductor layer portion that was enwrapped by the dummy gate. The method further includes introducing, into the exposed portion of the first semiconductor layer portion, one or more dopants including a conductivity type reversing dopant, so as to form a channel region having a first conductivity type and at least two opposed channel control regions having a second conductivity type, wherein the channel control regions further comprise a portion formed above and adjoining a top of the channel region.
    Type: Application
    Filed: October 2, 2014
    Publication date: February 5, 2015
    Inventor: Mieno FUMITAKE
  • Patent number: 8946007
    Abstract: After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. The removal of the bottom semiconductor layer exposes a horizontal surface of the buried insulator layer present between source and drain regions on which a conductive material layer is formed as a back gate electrode.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Douglas C. La Tulipe, Jr.
  • Publication number: 20150011061
    Abstract: A process of forming a CMOS integrated circuit by forming a first stressor layer over two MOS transistors of opposite polarity, removing a portion of the first stressor layer from the first transistor, and forming a second stressor layer over the two transistors. A source/drain anneal is performed, crystallizing amorphous regions of silicon in the gates of the two transistors, and subsequently removing the stressor layers. A process of forming a CMOS integrated circuit by forming two transistors of opposite polarity, forming a two stressor layers over the transistors, annealing the integrated circuit, removing the stressor layers, and siliciding the transistors. A process of forming a CMOS integrated circuit with an NMOS transistor and a PMOS transistor using a stress memorization technique, by removing the stressor layers with wet etch processes.
    Type: Application
    Filed: September 26, 2014
    Publication date: January 8, 2015
    Inventors: Russell Carlton McMULLAN, Dong Joo BAE
  • Publication number: 20140377919
    Abstract: A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.
    Type: Application
    Filed: August 27, 2014
    Publication date: December 25, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Suraj Mathew
  • Patent number: 8916430
    Abstract: A method for fabricating an integrated circuit includes forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region, forming a sacrificial spacer on sidewalls of the first and second gate electrode structures, and forming deep drain and source regions selectively in the first and second active regions by using the sacrificial spacer as an implantation mask. The method further includes forming drain and source extension and halo regions in the first and second active regions after removal of the sacrificial spacer and forming a nitrogen implant region in the halo region of the first active region after formation of the drain and source extension and halo regions.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ran Yan, Jan Hoentschel, Shiang Yang Ong
  • Patent number: 8889554
    Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: November 18, 2014
    Assignee: The Institue of Microelectronics Chinese Academy of Science
    Inventors: Haizhou Yin, Wei Jiang, Zhijiong Luo, Huilong Zhu
  • Patent number: 8877582
    Abstract: One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An N-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e18-5e21 ions/cm3.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: November 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Peter Javorka, Stefan Flachowsky, Nicolas Sassiat
  • Patent number: 8877581
    Abstract: An integrated circuit (IC) includes a plurality of strained metal oxide semiconductor (MOS) devices that include a semiconductor surface having a first doping type, a gate electrode stack over a portion of the semiconductor surface, and source/drain recesses that extend into the semiconductor surface and are framed by semiconductor surface interface regions on opposing sides of the gate stack. A first epitaxial strained alloy layer (rim) is on the semiconductor surface interface regions, and is doped with the first doping type. A second epitaxial strained alloy layer is on the rim and is doped with a second doping type that is opposite to the first doping type that is used to form source/drain regions.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Amitabh Jain, Deborah J. Riley
  • Patent number: 8859360
    Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: October 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazunobu Ota, Hirokazu Sayama, Hidekazu Oda
  • Patent number: 8846461
    Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Hsin Lin, Weng Chang, Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Ming-Hua Yu
  • Patent number: 8835291
    Abstract: Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chao Huang, Fu-Liang Yang
  • Publication number: 20140248749
    Abstract: A method comprises providing a semiconductor structure comprising a gate structure provided over a semiconductor region. An ion implantation process is performed. In the ion implantation process, a first portion of the semiconductor region adjacent the gate structure and a second portion of the semiconductor region adjacent the gate structure are amorphized so that a first amorphized region and a second amorphized region are formed adjacent the gate structure. An atomic layer deposition process is performed. The atomic layer deposition process deposits a layer of a material having an intrinsic stress over the semiconductor structure. A temperature at which at least a part of the atomic layer deposition process is performed and a duration of the at least a part of the atomic layer deposition process are selected such that the first amorphized region and the second amorphized region are re-crystallized during the atomic layer deposition process.
    Type: Application
    Filed: March 4, 2013
    Publication date: September 4, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Stefan Flachowsky, Nicolas Sassiat, Ralf Richter
  • Patent number: 8822298
    Abstract: Sophisticated transistors for semiconductor devices may be formed on the basis of a superior process sequence in which an increased space between closely spaced gate electrode structures may be obtained in combination with a reduced material loss in the active regions. To this end, an offset spacer conventionally used for laterally profiling the drain and source extension regions is omitted and the spacer for the deep drain and source areas may be completely removed.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: September 2, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel