And Additional Field Effect Transistor (e.g., Sense Or Access Transistor, Etc.) Patents (Class 438/241)
  • Patent number: 10566233
    Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: February 18, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Dohyun Lee, Youngwoo Park, Junghoon Park, Jaeduk Lee
  • Patent number: 10217932
    Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include a free layer including a plurality of magnetic layers each having a variable magnetization direction; a tunnel barrier layer formed over the free layer; and a pinned layer formed over the tunnel barrier layer and having a pinned magnetization direction; wherein the plurality of magnetic layers in the free layer includes a first magnetic layer in contact with the tunnel barrier layer and a second magnetic layer not in contact with the tunnel barrier layer and a sum of an exchange field between the first magnetic layer and the second magnetic layer and a stray field generated by the first magnetic layer is larger than or the same as a difference between a uniaxial anisotropy field of the second magnetic layer and a demagnetizing field due to a shape of the second magnetic layer.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: February 26, 2019
    Assignee: SK hynix Inc.
    Inventors: Jung-Hwan Moon, Sung-Joon Yoon
  • Patent number: 10199328
    Abstract: A semiconductor device includes a first contact plug on a substrate, a first lower electrode disposed on the first contact plug and extended in a thickness direction of the substrate, a first supporter pattern on the first lower electrode and including an upper surface and a lower surface, the upper surface of the first supporter pattern being higher than a top surface of the first lower electrode, a dielectric film on the first lower electrode, the upper surface of the first supporter pattern and the lower surface of the first supporter pattern and an upper electrode disposed on the dielectric film.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan Sic Yoon, Ki Seok Lee
  • Patent number: 10032673
    Abstract: A method for manufacturing a semiconductor device includes forming a first gate structure on a semiconductor substrate. The first gate structure includes a first gate dielectric layer and a first gate electrode layer formed thereon. The method also includes forming an insulating material layer on the semiconductor substrate, wherein the semiconductor substrate and the first gate structure are covered by the insulating material layer. The method further includes removing a portion of the insulating material layer in a high-voltage element region to form a second gate dielectric layer in the high-voltage element region on the semiconductor substrate, and forming a second gate electrode layer on the second gate dielectric layer.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: July 24, 2018
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Li-Che Chen, Chien-Wei Chiu, Chien-Hsien Song
  • Patent number: 10026744
    Abstract: An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate located in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate located in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate located in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: July 17, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideaki Yamakoshi, Takashi Hashimoto, Shinichiro Abe, Yuto Omizu
  • Patent number: 9355851
    Abstract: A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: May 31, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Won Hong, Hei-Seung Kim, Kyoung-hee Nam, In-sun Park, Jong-Myeong Lee
  • Patent number: 9343471
    Abstract: An embedded flash memory cell and a corresponding method for fabricating the embedded flash memory cell are disclosed. In some embodiments, the flash memory cell comprises a floating gate that has been formed using a metal gate and local interconnect metal. For some embodiments, the embedded flash memory can be fabricated with little-to-no additional processes than what one would normally employ in fabricating a metal-oxide semiconductor field-effect transistor (MOSFET).
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: May 17, 2016
    Assignee: BROADCOM CORPORATION
    Inventor: Wei Xia
  • Patent number: 9337106
    Abstract: A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist layer is developed (but not baked) to form a first resist geometry and a plurality of sublithographic resist geometries. The resist layer is baked causing the sublithographic resist geometries to reflow into a continuous second resist geometry having a thickness less that the first resist geometry. A high energy implant implants dopants through the second resist geometry but not through the first resist geometry. A low energy implant is blocked by both the first and second resist geometries.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: May 10, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer P. Pendharkar, Binghua Hu
  • Patent number: 9318488
    Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a first active region adjacent a first side of a shallow trench isolation (STI) region. The first active region including a first proximal fin having a first proximal fin height adjacent the STI region, and a first distal fin having a first distal fin height adjacent the first proximal fin, the first proximal fin height less than the first distal fin height. The STI region includes oxide, the oxide having an oxide volume, where the oxide volume is inversely proportional to the first proximal fin height. A method of formation includes forming a first proximal fin with a first proximal fin height less than a first distal fin height of a first distal fin, such that the first proximal fin is situated between the first distal fin and an STI region.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: April 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Wen Wu, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Hsiao-Chiu Hsu, Hsin-Ying Lin
  • Patent number: 9312185
    Abstract: Embodiments of present invention provide a method of forming metal resistor. The method includes forming a first and a second structure on top of a semiconductor substrate in a replacement-metal-gate process to have, respectively, a sacrificial gate and spacers adjacent to sidewalls of the sacrificial gate; covering the second structure with an etch-stop mask; replacing the sacrificial gate of the first structure with a replacement metal gate; removing the etch-stop mask to expose the sacrificial gate of the second structure; forming a silicide in the second structure as a metal resistor; and forming contacts to the silicide. In one embodiment, forming the silicide includes siliciding a top portion of the sacrificial gate of the second structure to form the metal resistor. In another embodiment, forming the silicide includes removing the sacrificial gate of the second structure to expose and silicide a channel region underneath thereof.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Cung Tran, Emre Alptekin, Viraj Sardesai, Reinaldo Vega
  • Patent number: 9257324
    Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: February 9, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Alan B. Botula, Renata Camillo-Castillo, James S. Dunn, Jeffrey P. Gambino, Douglas B. Hershberger, Alvin J. Joseph, Robert M. Rassel, Mark E. Stidham
  • Patent number: 9214356
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun Liu, Chung-Te Lin, Ming-Feng Shieh, Shih-Ming Chang, Tsai-Sheng Gau
  • Patent number: 9129853
    Abstract: A method for manufacturing a semiconductor device including a semiconductor substrate having transistors formed thereon, a first interlayer insulating film formed above the semiconductor substrate and the transistors, a ferroelectric capacitor formed above the first interlayer insulating film, a second interlayer insulating film formed above the first interlayer insulating film and the ferroelectric capacitor, a first metal wiring formed on the second interlayer insulating film, and a protection film formed on an upper surface of the wiring but not on a side surface of the wiring.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: September 8, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Kouichi Nagai
  • Patent number: 9130061
    Abstract: A semiconductor device includes: a micro CMOS region including a micro CMOS and a micro interconnect that is connected to the micro CMOS; and a high breakdown voltage device region including a high breakdown voltage device that has a breakdown voltage higher than that of the micro CMOS, and drain and source interconnects that are connected to the high breakdown voltage device and have a width greater than that of the micro interconnect in a plan view. In the high breakdown voltage device region, an electrically-isolated dummy interconnect is not provided adjacent to at least the drain interconnect and the source interconnect.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: September 8, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hisamitsu Suzuki
  • Patent number: 9123662
    Abstract: A method includes forming a mask layer forming a first photo resist over the mask layer, performing a first patterning step on the first photo resist, and performing a first etching step on the mask layer using the first photo resist as an etching mask. The first photo resist is then removed. The method further includes forming a particle-fixing layer on a top surface and sidewalls of the mask layer, forming a second photo resist over the particle-fixing layer and the mask layer, performing a second patterning step on the second photo resist, and performing a second etching step on the particle-fixing layer and the mask layer using the second photo resist as an etching mask. The particle-fixing layer is etched through. A target layer underlying the mask layer is etched using the mask layer as an etching mask.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ching-Yu Chang
  • Patent number: 9093504
    Abstract: A semiconductor device is manufactured by forming, on an insulating base material, a first support element having a side face that extends from a surface of the insulating base material, forming a coating of amorphous silicon on the side face of the first support element, filling an aperture disposed between the first support element and a second support element that extends from a surface of the insulating base material with an insulating film, planarizing the insulating film to expose an exposed portion of the coating and a surface of the first support element, and siliciding the amorphous silicon of the coating to form an interconnect.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: July 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masakatsu Tsuchiaki
  • Patent number: 9093318
    Abstract: A memory device is described. Generally, the device includes a memory transistor and a metal oxide semiconductor (MOS) logic transistor. The memory transistor includes: a channel region electrically connecting a source region and a drain region, the channel region comprising polysilicon; an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, the ONNO stack comprising a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer; and a gate electrode comprising doped polysilicon formed over a surface of the ONNO stack. The MOS logic transistor includes a gate oxide and a gate electrode comprising doped polysilicon. Other embodiments are also described.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: July 28, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Igor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
  • Patent number: 9024425
    Abstract: The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least an integrated intermediate-circuit die comprising both a read/write-voltage generator (VR/VW-generator) and an address/data translator (A/D-translator). The intermediate-circuit die performs voltage, address and/or data conversion between the 3D-M core region and the host. Discrete 3D-M support multiple 3D-array dies.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 5, 2015
    Assignees: HangZhou HaiCun Information Technology Co., Ltd., Guobiao Zhang
    Inventor: Guobiao Zhang
  • Patent number: 8987800
    Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert, Xinhui Wang
  • Publication number: 20150060971
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device including a memory cell transistor having a stacked gate structure including a tunnel insulating film, a charge accumulation layer, a memory cell insulating film, and a control gate electrode film are orderly stacked above a semiconductor substrate, and a capacitor in which a first insulating film, a first electrode film, a second insulating film, a second electrode film, a third insulating film, and a third electrode film are orderly stacked above the semiconductor substrate is provided. A material of the second electrode film is same as the charge accumulation layer of the memory cell transistor. The third electrode film includes a material same as the control gate electrode film of the memory cell transistor.
    Type: Application
    Filed: December 2, 2013
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa FUJII
  • Publication number: 20150050789
    Abstract: A method comprises implanting ions in a substrate to form a first active region and a second active region, depositing a first dielectric layer over the substrate, forming a first via and a second via in the first dielectric layer, wherein the first via is over the first active region and the second via is over the second active region, depositing a second dielectric layer over the first dielectric layer, forming a third via and a fourth via in the second dielectric layer, wherein the third via is over the first via and the fourth via is over the second via and forming a connector in a metallization layer over the second dielectric layer, wherein the connector is electrically connected to the third via and the fourth via.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 19, 2015
    Inventors: Hsiao-Tsung Yen, Yu-Ling Lin
  • Patent number: 8946019
    Abstract: In a semiconductor device, capacitors may be formed so as to be in direct contact with a transistor by using a shared transistor region, such as a drain region or a source region of closely spaced transistors, as one capacitor electrode, while the other capacitor electrode is provided in the form of a buried electrode in the dielectric material of the contact level. To this end, dielectric material may be deposited so as to reliably form a void, wherein, at any appropriate manufacturing stage, a capacitor dielectric material may be provided so as to separate the capacitor electrodes.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: February 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dmytro Chumakov, Tino Hertzsch
  • Patent number: 8936992
    Abstract: Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 8921991
    Abstract: The present invention discloses a discrete three-dimensional memory (3D-M). It is partitioned into at least two discrete dice: a memory-array die and a peripheral-circuit die. The memory-array die comprises at least a 3D-M array, which is built in a 3-D space. The peripheral-circuit die comprises at least a peripheral-circuit component, which is built on a 2-D plane. At least one peripheral-circuit component of the 3D-M is formed in the peripheral-circuit die instead of in the memory-array die. The array efficiency of the memory-array die can be larger than 70%.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: December 30, 2014
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 8916470
    Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: December 23, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Durga Panda, Jaydip Guha, Robert Kerr
  • Patent number: 8907459
    Abstract: A three-dimensional semiconductor integrated circuit device is provided. A first semiconductor chip includes a solid-state circuit and is smaller than a base, and is stacked on the base. The first chip is buried by a first filling material having approximately the same contour as the base. Buried electrodes that penetrate through the first chip along its thickness direction are formed in the first chip. A second semiconductor chip includes a solid-state circuit and is smaller than the base, and is stacked on the first chip. The second chip is buried by a second filling material having approximately the same contour as the base. Buried electrodes that penetrate through the second chip along its thickness direction are formed in the second chip. The first and second filling materials have processibilities required for forming the buried electrodes and thermal expansion coefficients equivalent to those of the first and second chips, respectively.
    Type: Grant
    Filed: January 15, 2007
    Date of Patent: December 9, 2014
    Assignee: Zycube Co., Ltd.
    Inventor: Manabu Bonkohara
  • Patent number: 8907392
    Abstract: A semiconductor memory device which includes a memory cell including two or more sub memory cells is provided. The sub memory cells each including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In the semiconductor device, the sub memory cells are stacked in the memory cell; a first gate and a second gate are formed with a semiconductor film provided therebetween in the transistor; the first gate and the second gate are connected to the word line; one of a source and a drain of the transistor is connected to the bit line; the other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor; and the first gate and the second gate of the transistor in each sub memory cell overlap with each other and are connected to each other.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8907423
    Abstract: A high withstand voltage transistor is formed in a high withstand voltage region, and a low withstand voltage transistor is formed in a low withstand voltage region in a method of manufacturing a semiconductor device. The method includes forming a thermal oxide film and a silicon nitride film over the surface of a silicon substrate; forming an opening to the thermal oxide film and the silicon nitride film in each of the high withstand voltage region and the low withstand voltage region; etching the silicon substrate to form trenches; burying a buried oxide film in each of the trenches; removing the thermal oxide film and the silicon nitride film; and forming a thick gate oxide film and a thin oxide film. The depth of a tapered portion of the trench in the low withstand voltage region is shallower than that in the high withstand voltage region.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Tadahiro Miwatashi
  • Patent number: 8895386
    Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. An oxide material layer and a first conductive material layer are sequentially formed on the substrate in the cell and periphery areas. A patterning step is performed to form first and second stacked structures on the substrate respectively in the cell and periphery areas. First and second spacers are formed respectively on sidewalls of the first and second stacked structures. At least two first doped regions are formed in the substrate beside the first stacked structure, and two second doped regions are formed in the substrate beside the second stacked structure. A dielectric layer and a second conductive layer are formed at least on the first stacked structure. The first stacked structure, the dielectric layer, and the second conductive layer in the cell area constitute a charge storage structure.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: November 25, 2014
    Assignee: Maxchip Electronics Corp.
    Inventors: Chen-Chiu Hsu, Tung-Ming Lai, Kai-An Hsueh, Ming-De Huang
  • Patent number: 8890300
    Abstract: The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its read/write-voltage generator (VR/VW-generator) is located on a separate peripheral-circuit die. The VR/VW-generator generates at least a read and/or write voltage to the 3D-array die. A single VR/VW-generator die can support multiple 3D-array dies.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: November 18, 2014
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 8890214
    Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 18, 2014
    Assignee: Nan Ya Technology Corporation
    Inventors: Panda Durga, Jaydip Guha, Robert Kerr
  • Publication number: 20140319591
    Abstract: In an interlayer insulating film in which contact plugs are embedded, a capacitor element is formed which has electrodes each formed of a metal. Over a substrate, the interlayer insulating film is formed. The interlayer insulating film includes a first insulating film and a second insulating film. In the second insulating film, the first and second contact plugs are formed. The first and second contact plugs extend through the second insulating film to reach first and second gate electrodes. In a surface of the substrate, an isolation film is formed. Within a region overlapping the isolation film in planar view, the capacitor element is formed. The capacitor element includes the lower and upper electrodes. Each of the lower and upper electrodes contains a metal. The lower and upper electrodes of the capacitor element are formed over the first insulating film to be embedded in the second insulating film.
    Type: Application
    Filed: April 14, 2014
    Publication date: October 30, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Takeshi TODA
  • Patent number: 8865543
    Abstract: The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO2) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron Schottky barrier height of metal/Ge contact, but also improves the current switching ratio of the Ge-based Schottky and therefore, it will improve the performance of the Ge-based Schottky NMOS transistor. In addition, the fabrication process is very easy and completely compatible with the silicon CMOS process. As compared with conventional fabrication method, the Ge-based NMOS device structure and the fabrication method in the present invention can easily and effectively improve the performance of the Ge-based Schottky NMOS transistor.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: October 21, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Zhiqiang Li, Xia An, Yue Guo, Xing Zhang
  • Patent number: 8866233
    Abstract: An object is to provide a semiconductor device having a novel structure which includes a combination of semiconductor elements with different characteristics and is capable of realizing higher integration. A semiconductor device includes a first transistor, which includes a first channel formation region including a first semiconductor material, and a first gate electrode, and a second transistor, which includes one of a second source electrode and a second drain electrode combined with the first gate electrode, and a second channel formation region including a second semiconductor material and electrically connected to the second source electrode and the second drain electrode.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8859362
    Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, John Lee, Zengtao Liu, Eric Freeman, Russell Nielsen
  • Patent number: 8835247
    Abstract: A sensor array for detecting particles, the sensor array comprising a substrate having a plurality of holes, a plurality of electronic sensor chips each having a sensor active region being sensitive to the presence of particles to be detected, and an electric contacting structure adapted for electrically contacting the plurality of electronic sensor chips, wherein the plurality of electronic sensor chips and/or the electric contacting structure are connected to the substrate in such a manner that the plurality of holes in combination with the plurality of electronic sensor chips and/or the electric contacting structure form a plurality of wells with integrated particle sensors.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: September 16, 2014
    Assignee: NXP, B.V.
    Inventors: Michel De Langen, Ger Reuvers, Frans Meeuwsen
  • Patent number: 8809927
    Abstract: A highly integrated DRAM is provided. A circuit for driving a memory cell array is formed over a substrate, a bit line is formed thereover, and a semiconductor region, word lines, and a capacitor are formed over the bit line. Since the bit line is located below the semiconductor region, and the word lines and the capacitor are located above the semiconductor region, the degree of freedom of the arrangement of the bit line is high. When an open-bit-line DRAM is formed, an area per memory cell less than or equal to 6F2, or when a special structure is employed for a cell transistor, an area per memory cell less than or equal to 4F2 can be achieved.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 8797791
    Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
  • Patent number: 8785273
    Abstract: A method of manufacturing a FinFET non-volatile memory device and a FinFET non-volatile memory device structure. A substrate is provided and a layer of semiconductor material is deposited over the substrate. A hard mask is deposited over the semiconductor material and the structure is patterned to form fins. A charge storage layer is deposited over the structure, including the fins and the portions of it are damaged using an angled ion implantation process. The damaged portions are removed and gate structures are formed on either side of the fin, with only one side having a charge storage layer.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni
  • Patent number: 8772104
    Abstract: The semiconductor device comprises a device isolation region formed in a semiconductor substrate, a lower electrode formed in a device region defined by the device isolation region and formed of an impurity diffused layer, a dielectric film of a thermal oxide film formed on the lower electrode, an upper electrode formed on the dielectric film, an insulation layer formed on the semiconductor substrate, covering the upper electrode, a first conductor plug buried in a first contact hole formed down to the lower electrode, and a second conductor plug buried in a second contact hole formed down to the upper electrode, the upper electrode being not formed in the device isolation region. The upper electrode is not formed in the device isolation region, whereby the short-circuit between the upper electrode and the lower electrode in the cavity can be prevented.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: July 8, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Makoto Yasuda, Akiyoshi Watanabe, Yoshihiro Matsuoka
  • Publication number: 20140167172
    Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is semiconductor device including a first FinFET over a substrate, wherein the first FinFET includes a first set of semiconductor fins. The semiconductor device further includes a first body contact for the first FinFET over the substrate, wherein the first body contact includes a second set of semiconductor fins, and wherein the first body contact is laterally adjacent the first FinFET.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Patent number: 8728886
    Abstract: A first dielectric layer is formed in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer and is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed in the NVM and logic regions which surrounds the charge storage structure and dummy gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. The dummy gate is removed, resulting in an opening. A third dielectric layer is formed over the charge storage structure and within the opening, and a gate layer is formed over the third dielectric layer and within the opening, wherein the gate layer forms a control gate layer in the NVM region and the gate layer within the opening forms a logic gate.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: May 20, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Patent number: 8709891
    Abstract: Memory devices and methods for providing the memory devices are provided. The memory devices utilize multiple metal oxide layers. The methods for providing the memory devices can include providing a transistor; producing a capacitor that includes metal layers and metal oxide layers; connecting the capacitor to a side of the transistor; and providing a wordline, bitline, and driveline through connection with the transistor or the capacitor.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: April 29, 2014
    Assignee: 4D-S Ltd.
    Inventors: Zhida Lan, Dongmin Chen
  • Patent number: 8687416
    Abstract: It is an object to provide a signal processing circuit for which a complex manufacturing process is not necessary and whose power consumption can be suppressed. In particular, it is an object to provide a signal processing circuit whose power consumption can be suppressed by stopping the power supply for a short time. The signal processing circuit includes a control circuit, an arithmetic unit, and a buffer memory device. The buffer memory device stores data sent from the main memory device or the arithmetic unit in accordance with an instruction from the control unit; the buffer memory device comprises a plurality of memory cells; and the memory cells each include a transistor including an oxide semiconductor in a channel formation region and a memory element to which charge whose amount depends on a value of the data is supplied via the transistor.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 8654592
    Abstract: Memory devices and methods of programming and forming the same are disclosed. In one embodiment, a memory device has memory cells contained within dielectric isolation structures to isolate them from at least those memory cells in communication with other bit lines, such as to facilitate forward-bias write operations. The dielectric isolation structures contain an upper well having a first conductivity type and a buried well having a second conductivity type. By forward biasing the junction from the buried well to the upper well, electrons can be injected into charge-storage nodes of memory cells that are contained within the dielectric isolation structures.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: February 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Badih El-Kareh, Leonard Forbes
  • Patent number: 8647944
    Abstract: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: February 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Shinkawata
  • Patent number: 8637364
    Abstract: An amorphous carbon film and an interlayer insulation film are formed in a memory cell region and a peripheral circuit region, respectively. An insulating film is formed on the amorphous carbon film and the interlayer insulation film. A portion of the insulating film that corresponds to capacitors on the amorphous carbon film is removed so that lower electrodes of the capacitors are supported from opposite sides of the lower electrodes. An insulating film pattern continuously extends from the memory cell region to the peripheral circuit region wholly covered with the insulating film pattern. Subsequently, the amorphous carbon film is removed to leave the capacitors supported by the insulating film pattern on both sides of the lower electrodes.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: January 28, 2014
    Inventor: Yasuhiko Ueda
  • Publication number: 20140024183
    Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. An oxide material layer and a first conductive material layer are sequentially formed on the substrate in the cell and periphery areas. A patterning step is performed to form first and second stacked structures on the substrate respectively in the cell and periphery areas. First and second spacers are formed respectively on sidewalls of the first and second stacked structures. At least two first doped regions are formed in the substrate beside the first stacked structure, and two second doped regions are formed in the substrate beside the second stacked structure. A dielectric layer and a second conductive layer are formed at least on the first stacked structure. The first stacked structure, the dielectric layer, and the second conductive layer in the cell area constitute a charge storage structure.
    Type: Application
    Filed: October 1, 2012
    Publication date: January 23, 2014
    Inventors: Chen-Chiu Hsu, Tung-Ming Lai, Kai-An Hsueh, Ming-De Huang
  • Patent number: 8633118
    Abstract: Methods for forming thin metal and semi-metal layers by thermal remote oxygen scavenging are described. In one embodiment, the method includes forming an oxide layer containing a metal or a semi-metal on a substrate, where the semi-metal excludes silicon, forming a diffusion layer on the oxide layer, forming an oxygen scavenging layer on the diffusion layer, and performing an anneal that reduces the oxide layer to a corresponding metal or semi-metal layer by oxygen diffusion from the oxide layer to the oxygen scavenging layer.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: January 21, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Robert D Clark
  • Patent number: 8629032
    Abstract: A non-volatile memory cell structure and a method of fabricating the same. The method comprising the steps of: fabricating a portion of a floating gate from one or more first metal local interconnection layer (LIL) slit contacts deposited on a patterned dielectric layer; and fabricating a portion of a control gate from one or more second metal LIL slit contacts deposited on the patterned dielectric layer; wherein the first and second metal LIL slit contacts form a capacitive structure between the floating gate and the control gate.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: January 14, 2014
    Assignee: Systems On Silicon Manufacturing Co. Pte. Ltd.
    Inventor: Sheng He Huang