Including Transistor Formed On Trench Sidewalls Patents (Class 438/242)
  • Patent number: 11917810
    Abstract: A memory cell includes a bit line and a plate line that are spaced apart from each other and vertically oriented in a first direction; a transistor provided with an active region that is laterally oriented in a second direction crossing the bit line and includes a first active cylinder, a second active cylinder, and at least one channel portion oriented laterally between the first active cylinder and the second active cylinder; a word line extending in a third direction while surrounding the at least one channel portion of the active region; and a capacitor oriented laterally in the second direction between the active region and the plate line.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 27, 2024
    Assignee: SK hynix Inc.
    Inventor: Ki Hong Lee
  • Patent number: 11876018
    Abstract: Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: January 16, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mitsuru Soma, Masahiro Shimbo, Masaki Kuramae, Kouhei Uchida
  • Patent number: 11843002
    Abstract: A transistor structure may include a first electrode, a second electrode, a third electrode, a substrate, and a semiconductor member. The semiconductor member overlaps the third electrode and includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion directly contacts the first electrode, is directly connected to the third semiconductor portion, and is connected through the third semiconductor portion to the second semiconductor portion. The second semiconductor portion directly contacts the second electrode and is directly connected to the third semiconductor portion. A minimum distance between the first semiconductor portion and the substrate is unequal to a minimum distance between the second semiconductor portion and the substrate.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: December 12, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun Sup Lee, Jung Hun Noh, Keun Kyu Song, Sang Hee Jang, Byung Seok Choi
  • Patent number: 11830830
    Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: November 28, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Alexei Sadovnikov, Sheldon Douglas Haynie, Ujwal Radhakrishna
  • Patent number: 11812600
    Abstract: An integrated circuit includes one or more layers of insulating material defining a vertical bore with a first portion and a second portion. A capacitor structure is in the first portion of the vertical bore and includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode. A transistor structure is in the second portion of the vertical bore and includes a third electrode extending into the second portion of the vertical bore, a layer of semiconductor material in contact with the first electrode and in contact with the second electrode, and a dielectric between the semiconductor material and the insulating material. A fourth electrode wraps around the transistor structure such that the dielectric is between the semiconductor material and the fourth electrode. The capacitor structure can be above or below the transistor structure in a self-aligned vertical arrangement.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: November 7, 2023
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Charles C. Kuo, Abhishek A. Sharma, Van H. Le, Jack Kavalieros
  • Patent number: 11538920
    Abstract: A method for increasing an oxide thickness at trench corner of an UMOSFET is provided, comprising providing an N-type substrate, and forming an N-type drift region, N-type and P-type heavily doped regions and P-type body therein. A trench is defined through lithography, and a pad oxide is formed along the trench through oxidation or deposition process. An oxidation barrier is formed upon the pad oxide. A thermal oxidation process is employed, so a corner oxide is effectively formed at the trench corner. After removing the pad oxide and oxidation barrier, various back-end processes are carried out to complete the transistor structure. The invention is aimed to increase oxide thickness near the trench bottom, and can be applied to high voltage devices, such as SiC. The conventional electric field crowding effect occurring at the trench corner is greatly solved, thus increasing breakdown voltages thereof.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: December 27, 2022
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Bing-Yue Tsui, Fang-Hsin Lu, Yi-Ting Shih
  • Patent number: 11502250
    Abstract: A memory device may be provided, including a base insulating layer, a bottom electrode arranged within the base insulating layer, a substantially planar switching layer arranged over the base insulating layer and a substantially planar top electrode arranged over the switching layer in a laterally offset position relative to the bottom electrode.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: November 15, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Shyue Seng Tan
  • Patent number: 11489055
    Abstract: Semiconductor devices and methods of forming the same are disclosed. The semiconductor devices may include a substrate including a first region and a second region, which are spaced apart from each other with a device isolation layer interposed therebetween, a first gate electrode and a second gate electrode on the first and second regions, respectively, an insulating separation pattern separating the first gate electrode and the second gate electrode from each other and extending in a second direction that traverses the first direction, a connection structure electrically connecting the first gate electrode to the second gate electrode, and a first signal line electrically connected to the connection structure. The first and second gate electrodes are extended in a first direction and are aligned to each other in the first direction. The first signal line may extend in the second direction and may vertically overlap the insulating separation pattern.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: November 1, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keun Hwi Cho, Soonmoon Jung, Dongwon Kim, Myung Gil Kang
  • Patent number: 11450364
    Abstract: Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih, Jonathan Tsung-Yung Chang
  • Patent number: 11233062
    Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: January 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jihye Kim, Jaehoon Lee, Jiyoung Kim, Bongtae Park, Jaejoo Shim
  • Patent number: 11227788
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Bing-Hung Chen, Chien-Hsun Wang, Cheng-Tung Lin, Chih-Tang Peng, De-Fang Chen, Huan-Just Lin, Li-Ting Wang, Yung-Cheng Lu
  • Patent number: 11063047
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The disclosed semiconductor device includes a plurality of gain-cell memory cells each stacked over a substrate. Axes of channel length directions of write transistors of memory cells correspond to each other, and are substantially perpendicular to the top surface of the substrate. The semiconductor device can retain multi-level data. The channel of read transistors is columnar silicon (embedded in a hole penetrating gates of the read transistors). The channel of write transistors is columnar metal oxide (embedded in a hole penetrating the gates of the read transistors and gates, or write word lines, of the write transistors). The columnar silicon faces the gate of the read transistor with an insulating film therebetween. The columnar metal oxide faces the write word line with an insulating film, which is obtained by oxidizing the write word line, therebetween, and is electrically connected to the gate of the read transistor.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: July 13, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Yoshiyuki Kurokawa
  • Patent number: 11031281
    Abstract: According to various embodiments, a semiconductor device may include: a semiconductor substrate; a deep trench extending from a first portion of the semiconductor substrate to a second portion of the semiconductor substrate, wherein the second portion underlies the first portion; and an insulator region at least substantially lining sides of the deep trench. The insulator region includes at least one shallow trench in the first portion of the semiconductor substrate. At least a portion of the shallow trench(es) is arranged over at least a portion of the deep trench.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: June 8, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Ke Dong
  • Patent number: 10777689
    Abstract: A shielded Schottky heterojunction power transistor is made from a Silicon-Carbide (SiC) wafer with SiC epitaxial layers including a N+ source and a Silicon N-epitaxial layer under the gate with higher channel mobility than SiC. The bulk of the wafer is a N+ SiC drain contacted by backside metal. A trench is formed between heterojunction transistors. Metal contacting the N+ source is extended into the trench to form a Schottky diode with the N-SiC substrate. P+ taps on the sides of the trench connect the metal to a P-SiC body diode under the heterojunction gate, and also prevent the Schottky metal from directly contacting the P body diode. Buried P pillars with P+ pillar caps are formed under the trench Schottky diode and under the heterojunction transistors. The P pillars provide shielding by balancing charge with the N substrate, acting as dielectrics to reduce the E-field above the pillars.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: September 15, 2020
    Assignee: Hong Kong Applied Science and Technology Research Institute Company, Limited
    Inventors: Shu Kin Yau, Siu Wai Wong
  • Patent number: 10020310
    Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a capping layer. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The capping layer is over the gate structure to define a void therebetween.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: July 10, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Tieh-Chiang Wu
  • Patent number: 9735161
    Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a capping layer. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The capping layer is over the gate structure to define a void therebetween.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: August 15, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Tieh-Chiang Wu
  • Patent number: 9349724
    Abstract: A semiconductor device including at least one first capacitor and at least one second capacitor. The at least one first capacitor includes a first storage node having a cylindrical shape. The at least one second capacitor includes a lower second storage node having a hollow pillar shape including a hollow portion, and an upper second storage node having a cylindrical shape and extending upward from the lower second storage node.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: May 24, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Cheon-bae Kim, Yong-chul Oh, Kuk-han Yoon, Kyu-pil Lee, Jong-ryul Jun, Chang-hyun Cho, Gyo-young Jin
  • Patent number: 9341759
    Abstract: A method for manufacturing a polarizer may include forming a first barrier and a second barrier on a surface of a metal layer. The method may further include providing a copolymer layer between the first barrier and the second barrier. The method may further include processing the copolymer layer to form a processed polymer layer that includes first-polymer portions and second-polymer portions that are alternately disposed. The method may further include removing the second-polymer portions from the processed polymer layer to form polymer members that are spaced from each other. The method may further include etching the metal layer, using at least the polymer members, the first barrier, and the second barrier as a mask, to form a plurality of first-type wires and a plurality of second-type wires.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: May 17, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: TaeWoo Kim, Lei Xie, Minhyuck Kang, Myung Im Kim, Seung-won Park, Moongyu Lee, Sumi Lee
  • Patent number: 9318366
    Abstract: A method includes forming an isolation structure partially buried in a substrate. A portion of the isolation structure protrudes from an upper surface of the substrate. The isolation structure is partially removed, thereby forming a modified isolation structure. An upper surface of the modified isolation structure is lower than the upper surface of the substrate. A gate dielectric structure is formed to be partially on the substrate and partially on the upper surface of the modified isolation structure.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: April 19, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih Chou, Kong-Beng Thei
  • Patent number: 9236326
    Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: January 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Shih-Fen Huang, Hsin-Li Cheng, Felix Ying-Kit Tsui
  • Patent number: 9006060
    Abstract: An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region there-between. At least one of the source/drain regions is conductively doped n-type with at least one of As and P. A conductivity-neutral dopant is in the silicon-comprising semiconductor material in at least one of the channel region and the at least one source/drain region. A gate construction is operatively proximate the channel region. Methods are disclosed.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Allen McTeer
  • Patent number: 8962455
    Abstract: A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hyun Choi, Jin-Ho Noh, Yoon-Ho Son, Dae-Hyuk Chung, In-Seak Hwang, Tae-Joon Park, Tae-Ho Hwang
  • Patent number: 8946045
    Abstract: A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Herbert L. Ho, Babar A. Khan, Kirk D. Peterson
  • Patent number: 8907392
    Abstract: A semiconductor memory device which includes a memory cell including two or more sub memory cells is provided. The sub memory cells each including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In the semiconductor device, the sub memory cells are stacked in the memory cell; a first gate and a second gate are formed with a semiconductor film provided therebetween in the transistor; the first gate and the second gate are connected to the word line; one of a source and a drain of the transistor is connected to the bit line; the other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor; and the first gate and the second gate of the transistor in each sub memory cell overlap with each other and are connected to each other.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8859369
    Abstract: Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region (5) is formed therebetween. In this manner, when a high voltage is applied to a drain region and 0 V is applied to the gate electrode, the trench bottom surface lower region (5) is depleted, thereby increasing the breakdown voltage in the OFF state.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: October 14, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Yukimasa Minami
  • Patent number: 8847361
    Abstract: A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhon-Jhy Liaw, Chang-Yun Chang
  • Patent number: 8846469
    Abstract: A fabrication method of a trenched power semiconductor device with source trench is provided. Firstly, at least two gate trenches are formed in a base. Then, a dielectric layer and a polysilicon structure are sequentially formed in the gate trench. Afterward, at least a source trench is formed between the neighboring gate trenches. Next, the dielectric layer and a second polysilicon structure are sequentially formed in the source trench. The second polysilicon structure is located in a lower portion of the source trench. Then, the exposed portion of the dielectric layer in the source trench is removed to expose a source region and a body region. Finally, a conductive structure is filled into the source trench to electrically connect the second polysilicon structure, the body region, and the source region.
    Type: Grant
    Filed: May 12, 2012
    Date of Patent: September 30, 2014
    Assignee: Great Power Semiconductor Corp.
    Inventors: Chun Ying Yeh, Hsiu Wen Hsu
  • Patent number: 8835248
    Abstract: Techniques for fabricating metal lines in semiconductor systems are disclosed. The metal may be tungsten. A hybrid Chemical Vapor Deposition (CVD)/Physical Vapor Deposition (PVD) process may be used. A layer of tungsten may be formed using CVD. This CVD layer may be formed over a barrier layer, such as, but not limited to, TiN or WN. This CVD layer may completely fill some feature such as a trench or via. Then, a layer of tungsten may be formed over the CVD layer using PVD. The layers of tungsten may then be etched to form a wire or line. Techniques for forming metal wires using a hybrid CVD/PVD process may provide for low resistivity with a barrier metal, low surface roughness, and good gap filling.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: September 16, 2014
    Assignee: SanDisk Technologies Inc.
    Inventor: Naoki Takeguchi
  • Patent number: 8828884
    Abstract: A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: September 9, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Yao-Sheng Lee, Zhen Chen, Syo Fukata
  • Patent number: 8816430
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a gate electrode, source/drain regions, and a gate insulating film. The substrate is made of monocrystalline silicon, an upper surface of the substrate is a (100) plane, and a trench is made in the upper surface. The gate electrode is provided in at least an interior of the trench. The source/drain regions are formed in regions of the substrate having the trench interposed. The gate insulating film is provided between the substrate and the gate electrode. The trench includes a bottom surface made of a (100) plane, a pair of oblique surfaces made of (111) planes contacting the bottom surface, and a pair of side surfaces made of (110) planes contacting the oblique surfaces. The source/drain regions are in contact with the side and oblique surfaces and are apart from a central portion of the bottom surface.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Yanagisawa
  • Patent number: 8809145
    Abstract: Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: August 19, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, John K. Zahurak
  • Patent number: 8796089
    Abstract: An embodiment relates to a method of forming a semiconductor structure, comprising: forming a first semiconductor layer; forming a second semiconductor layer over the first semiconductor layer; forming a third semiconductor layer over the second semiconductor layer; forming an opening in the first, second and third semiconductor layers; forming a conductive region within the first, the and third semiconductor layer, the conductive region surrounding the opening, the conductive region being electrically coupled to the first semiconductor layer; forming a dielectric layer in the opening and over the conductive region; and forming a conductive layer over the dielectric layer in the opening.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: August 5, 2014
    Assignee: Infineon Technologies AG
    Inventors: Detlef Wilhelm, Guenter Pfeifer, Bernd Eisener, Dieter Claeys
  • Patent number: 8772862
    Abstract: A vertical channel transistor includes a pillar formed over a substrate, and a gate electrode formed on sidewalls of the pillar, wherein the pillar includes a source area, a vertical channel area over the source area, a drain area over the vertical channel area, and a leakage prevention area interposed between the vertical channel area and the drain area.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: July 8, 2014
    Assignee: SK Hynix Inc.
    Inventor: Heung-Jae Cho
  • Patent number: 8735228
    Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 27, 2014
    Assignee: PFC Device Corp.
    Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao
  • Patent number: 8658498
    Abstract: A method for fabricating vertical surround gate structures in semiconductor device arrays. The method includes forming pillars separated by vertical and horizontal trenches on a substrate. Forming a gate layer over the pillars and trenches such that the gate layer forms gate trenches in the horizontal trenches. The method includes forming fillers within the gate trenches, and planarizing the gate layer and fillers. The method also includes successively etching a first portion of the gate layer, removing the fillers, and etching a second portion of the gate layer.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chung H. Lam, Jing Li
  • Patent number: 8652901
    Abstract: A method for fabricating vertical surround gate structures in semiconductor device arrays. The method includes forming pillars separated by vertical and horizontal trenches on a substrate. Forming a gate layer over the pillars and trenches such that the gate layer forms gate trenches in the horizontal trenches. The method includes forming fillers within the gate trenches, and planarizing the gate layer and fillers. The method also includes successively etching a first portion of the gate layer, removing the fillers, and etching a second portion of the gate layer.
    Type: Grant
    Filed: March 3, 2013
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chung H. Lam, Jing Li
  • Patent number: 8653596
    Abstract: An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kulkarni
  • Patent number: 8637355
    Abstract: Actuating a semiconductor device includes providing a transistor that includes a substrate and a first electrically conductive material layer, including a reentrant profile, positioned on the substrate. An electrically insulating material layer is conformally positioned over the first electrically conductive material layer and at least a portion of the substrate. A semiconductor material layer conforms to and is in contact with the electrically insulating material layer. A second electrically conductive material layer and third electrically conductive material layer are nonconformally positioned over and in contact with a first portion of the semiconductor material layer and a second portion of the semiconductor material layer, respectively.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: January 28, 2014
    Assignee: Eastman Kodak Company
    Inventors: Shelby F. Nelson, Lee W. Tutt
  • Patent number: 8623725
    Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Mark Kiehlbauch, Kevin R. Shea
  • Patent number: 8609492
    Abstract: Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: December 17, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kurt D. Beigel, Sanh D. Tang
  • Patent number: 8592883
    Abstract: An embodiment may be a semiconductor structure, comprising; a workpiece having a front side and a back side; and a capacitor disposed in the workpiece, the capacitor including a bottom electrode electrically coupled to a back side of said workpiece. In an embodiment, the bottom electrode may form a conductive pathway to the front side of the workpiece. In an embodiment, the capacitor may be a trench capacitor.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: November 26, 2013
    Assignee: Infineon Technologies AG
    Inventors: Dieter Claeys, Bernd Eisener, Guenter Pfeifer, Detlef Wilhelm
  • Patent number: 8580637
    Abstract: A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: November 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhun Hua Chen, Yu-Lung Tung, Chi-Tien Chen, Hua-Tai Lin, Hsiang-Lin Chen, Hung Chang Hsieh, Yi-Fan Chen
  • Patent number: 8569164
    Abstract: A through substrate structure, an electronic device package using the same, and methods for manufacturing the same are disclosed. First, a via hole pattern is formed by etching an upper surface of a first substrate. A pattern layer of a second substrate is formed on the first substrate by filling the via hole pattern with a material for the second substrate by reflow. A via hole pattern is formed in the pattern layer of the second substrate by patterning the upper surface of the first substrate. Moreover, a via plug filling the via hole pattern is formed by a plating process, for example, thereby forming a through substrate structure, which can be used in an electronic device package.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: October 29, 2013
    Assignee: Industry-Academic Cooperation Foundation, Dankook University
    Inventors: Jae Hyoung Park, Seung Ki Lee, Ju Yong Lee
  • Patent number: 8557656
    Abstract: A non-planar transistor having floating body structures and methods for fabricating the same are disclosed. In certain embodiments, the transistor includes a fin having upper and lower doped regions. The upper doped regions may form a source and drain separated by a shallow trench formed in the fin. During formation of the fin, a hollow region may be formed underneath the shallow trench, isolating the source and drain. An oxide may be formed in the hollow region to form a floating body structure, wherein the source and drain are isolated from each other and the substrate formed below the fin. In some embodiments, independently bias gates may be formed adjacent to walls of the fin. In other embodiments, electrically coupled gates may be formed adjacent to the walls of the fin.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: October 15, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8546215
    Abstract: A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: October 1, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Gordon Haller, Sanh Dang Tang, Steve Cummings
  • Patent number: 8518792
    Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: August 27, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Thomas E. Davenport, John Cronin
  • Patent number: 8518791
    Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating the same in the form of a damascene self-aligned F-RAM device comprising a PZT capacitor built on the sidewalls of an oxide trench, while allowing for the simultaneous formation of two ferroelectric sidewall capacitors.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: August 27, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Thomas E. Davenport, John Cronin
  • Patent number: 8501561
    Abstract: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: August 6, 2013
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler, Norbert Krischke
  • Patent number: 8501559
    Abstract: Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: August 6, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, John K. Zahurak
  • Patent number: 8493709
    Abstract: In a capacitor structure and method of forming the same, a first electrode, a second electrode, and a first insulation layer are sequentially formed on a substrate. The first and second electrodes and the first insulation layer are covered with a second insulation layer on the substrate. A first plug is in contact with the second electrode through the second insulation layer. A second plug is in contact with the first electrode through the first and second insulation layer. A third insulation layer is formed on the second insulation layer. Third and fourth comb-shaped electrodes are formed in the third insulation layer. The third electrode is contact with the first plug and the fourth electrode is contact with the second plug while facing the third electrode. Thus, the teeth of the comb-shaped electrodes are alternately arranged and spaced apart in the third insulation layer.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: July 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chul-Ho Chung