Multiple Doping Steps Patents (Class 438/247)
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Patent number: 11114551Abstract: Fin field-effect transistors are provided. A fin field-effect transistor includes a semiconductor substrate; a plurality of fins on the semiconductor substrate; a gate structure across the fins by covering portions of top and side surfaces of the fins, providing portions of the fins under the gate structure as channel regions; lightly doped regions in the fins at both sides of the gate structure; doped source/drain regions in the fins at both sides of the gate structure; and counter doped regions in fins and between the lightly doped regions and the doped source/drain regions.Type: GrantFiled: June 12, 2019Date of Patent: September 7, 2021Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Fei Zhou
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Patent number: 10892320Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a first conductivity type. An epitaxial layer having the first conductivity type is disposed on the substrate, and a trench is formed in the epitaxial layer. A first well region having a second conductivity type that is different from the first conductivity type is disposed in the epitaxial layer and under the trench. A first gate electrode having the second conductivity type is disposed in the trench, and a second gate electrode is disposed in the trench on the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by a first insulating layer. A method for forming the semiconductor device is also provided.Type: GrantFiled: April 30, 2019Date of Patent: January 12, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Wen-Shan Lee, Chung-Yeh Lee, Fu-Hsin Chen
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Patent number: 10355125Abstract: In one embodiment, a method for forming a semiconductor device having a shield electrode includes forming first and second shield electrode contact portions within a contact trench. The first shield electrode contact portion can be formed recessed within the contact trench and includes a flat portion. The second shield electrode contact portion can be formed within the contact trench and makes contact to the first shield electrode contact portion along the flat portion.Type: GrantFiled: November 13, 2014Date of Patent: July 16, 2019Assignee: Semiconductor Components Industries, LLCInventor: Gordon M Grivna
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Patent number: 8987800Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.Type: GrantFiled: March 14, 2013Date of Patent: March 24, 2015Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert, Xinhui Wang
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Patent number: 8895370Abstract: A vertical conduction power device includes respective gate, source and drain areas formed in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations are formed by a first metallization level. The gate, source and drain terminals are formed by a second metallization level. The device is configured as a set of modular areas extending parallel to each other. Each modular area has a rectangular elongate source area perimetrically surrounded by a gate area, and a drain area defined by first and second regions. The first regions of the drain extend parallel to one another and separate adjacent modular areas. The second regions of the drain area extend parallel to one another and contact ends of the first regions of the drain area.Type: GrantFiled: September 30, 2013Date of Patent: November 25, 2014Assignee: STMicroelectronics S.R.L.Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magri′
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Patent number: 8557657Abstract: A semiconductor device includes a substrate having a first doped portion to a first depth and a second doped portion below the first depth. A deep trench capacitor is formed in the substrate and extends below the first depth. The deep trench capacitor has a buried plate that includes a dopant type forming an electrically conductive connection with second doped portion of the substrate and being electrically insulated from the first doped portion.Type: GrantFiled: May 18, 2012Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Veeraraghavan S. Basker, Wilfried E. Haensch, Effendi Leobandung, Tenko Yamashita, Chun-Chen Yeh
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Patent number: 8492221Abstract: A method for fabricating a power semiconductor device is provided. A substrate with a first conductivity type is prepared. A semiconductor layer with a second conductivity type is formed on the substrate. A hard mask pattern having at least an opening is formed on the semiconductor layer. A first trench etching is performed to form a first recess in the semiconductor layer via the opening. A first ion implantation is performed to vertically implant dopants into the bottom of the first recess via the opening, thereby forming a first doping region. A second trench etching is performed to etch through the first doping region, thereby forming a second recess.Type: GrantFiled: March 28, 2012Date of Patent: July 23, 2013Assignee: Anpec Electronics CorporationInventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
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Patent number: 8372710Abstract: A semiconductor structure having U-shaped transistors includes source/drain regions at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. Methods of forming semiconductor structures are also disclosed.Type: GrantFiled: December 19, 2011Date of Patent: February 12, 2013Assignee: Micron Technology, Inc.Inventor: Werner Juengling
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Patent number: 8324014Abstract: The present invention relates to a process for depositing films on a substrate by chemical vapour deposition (CVD) or physical vapour deposition (PVD), said process employing at least one boron compound. This process is particularly useful for fabricating photovoltaic solar cells. The invention also relates to the use of boron compounds for conferring optical and/or electrical properties on materials in a CVD or PVD deposition process. This process is also particularly useful for fabricating a photovoltaic solar cell.Type: GrantFiled: November 3, 2008Date of Patent: December 4, 2012Assignee: L'Air Liquide Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges ClaudeInventors: Audrey Pinchart, Denis Jahan
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Patent number: 8133781Abstract: A mask layer formed over a semiconductor substrate is lithographically patterned to form an opening therein. Ions are implanted at an angle that is normal to the surface of the semiconductor substrate through the opening and into an upper portion of the semiconductor substrate. Straggle of the implanted ions form a doped region that laterally extends beyond a horizontal cross-sectional area of the opening. A deep trench is formed by performing an anisotropic etch of a semiconductor material underneath the opening to a depth above a deep end of an implanted region. Ion implantation steps and anisotropic etch steps are alternately employed to extend the depth of the doped region and the depth of the deep trench, thereby forming a doped region around a deep trench that has narrow lateral dimensions. The doped region can be employed as a buried plate for a deep trench capacitor.Type: GrantFiled: February 15, 2010Date of Patent: March 13, 2012Assignee: International Business Machines CorporationInventors: Joseph Ervin, Geng Wang
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Patent number: 7951682Abstract: A method for fabricating a capacitor in a semiconductor device includes forming an insulation layer over a substrate, forming a storage node contact plug passing through the insulation layer and coupled to the substrate, recessing the storage node contact plug to a certain depth to obtain a sloped profile, forming a barrier metal over the surface profile of the recessed storage node contact plug, forming a sacrificial layer over the substrate structure, etching the sacrificial layer to form an opening exposing the barrier metal, forming a bottom electrode over the surface profile of the opening, and removing the etched sacrificial layer.Type: GrantFiled: May 4, 2009Date of Patent: May 31, 2011Assignee: Hynix Semiconductor Inc.Inventor: Soung-Min Ku
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Patent number: 7902020Abstract: A semiconductor device includes a first conductivity-type deep well formed in a substrate, a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep well is formed, a second conductivity-type well formed on a portion of the first conductivity-type deep well between two of the device isolation layers, a first gate pattern formed over a portion of the second conductivity-type well, a second gate pattern formed over one of the device isolation layers, a source region formed in an upper surface of the second conductivity-type well to adjoin a first side of the first gate pattern, a first drain region formed to include the interface between an upper surface of the second conductivity-type well adjoining a second side of the first gate pattern and an upper surface of the first conductivity-type deep well adjoining the second side of the first gate pattern, and a second drain region formed in an upper surface of the first conductivity-type deep well to be spaced from thType: GrantFiled: October 1, 2009Date of Patent: March 8, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Il-Yong Park
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Patent number: 7883984Abstract: A method of manufacturing a flash memory device may include forming a trench, defining at least a common source region, on a semiconductor substrate, forming a gate poly over the semiconductor substrate, performing an ion implantation process employing a first photoresist pattern and the gate poly as a mask, wherein the ion implantation process forms a source/drain junction on the semiconductor substrate, forming a recess common source region in the trench by using a second photoresist pattern, and performing an ion implantation process on the recess common source region.Type: GrantFiled: November 18, 2009Date of Patent: February 8, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Ji-Hwan Park
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Patent number: 7871881Abstract: A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench, which reaches down to the insulator and surrounds a region of the monocrystalline silicon of a SOI structure, doping the monocrystalline silicon region, forming an insulating, which can be nitride, layer region on a portion of the monocrystalline silicon region, forming a doped silicon layer region on the insulating layer region, and forming an insulating outside sidewall spacer on the monocrystalline silicon region, where the outside sidewall spacer surrounds the doped silicon layer region to provide an isolation between the doped silicon layer region and exposed portions of the monocrystalline silicon region. The monocrystalline silicon region, the insulating layer region, and the doped silicon layer region constitute a lower electrode, a dielectric, and an upper electrode of the capacitor.Type: GrantFiled: March 30, 2009Date of Patent: January 18, 2011Assignee: Infineon Technologies AGInventor: Ted Johansson
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Patent number: 7863130Abstract: System and method for creating stressed polycrystalline silicon in an integrated circuit. A preferred embodiment includes manufacturing an integrated circuit, including forming a trench in an integrated circuit substrate, forming a cavity within the integrated circuit substrate, wherein the cavity is linked to the trench, depositing a dielectric layer within the cavity, and depositing polycrystalline silicon over the dielectric layer, wherein an inherent stress is induced in the polycrystalline silicon that grows on the dielectric layer. The dielectric layer may be, for example, silicon aluminum oxynitride (SiAlON), mullite (3Al2O3.2SiO2), and alumina (Al2O3).Type: GrantFiled: May 16, 2007Date of Patent: January 4, 2011Assignee: Infineon Technologies AGInventors: Matthias Hierlemann, Chandrasekhar Sarma
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Patent number: 7803701Abstract: A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.Type: GrantFiled: December 26, 2007Date of Patent: September 28, 2010Assignee: Nanya Technology CorporationInventors: Shian-Jyh Lin, Shun-Fu Chen, Tse-Chuan Kuo, An-Hsiung Liu
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Patent number: 7785996Abstract: A nonvolatile memory device and a method of manufacturing the same are provided. The nonvolatile memory device includes a semiconductor substrate on which a source region, a drain region, and a channel region are formed, a silicon oxide layer formed on the channel region, a transition metal oxide layer having trap particles that trap electrons, formed on the silicon oxide layer, and a gate electrode formed on the transition metal oxide layer.Type: GrantFiled: October 19, 2005Date of Patent: August 31, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-hyun Lee, Kyu-sik Kim
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Patent number: 7713814Abstract: Method of limiting the lateral extent of a trench capacitor by a dielectric spacer in a hybrid orientations substrate is provided. The dielectric spacer separates a top semiconductor portion from an epitaxially regrown portion, which have different crystallographic orientations. The deep trench is formed as a substantially straight trench within the epitaxially regrown portion such that part of the epitaxially regrown portion remains overlying the dielectric spacer. The substantially straight trench is then laterally expanded to form a bottle shaped trench and to provide increased capacitance. The lateral expansion of the deep trench is self-limited by the dielectric spacer above the interface between the handle substrate and the buried insulator layer.Type: GrantFiled: January 4, 2008Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ramachandra Divakaruni
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Patent number: 7709365Abstract: A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.Type: GrantFiled: October 23, 2006Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Wilfried Haensch, Terence B. Hook, Louis C. Hsu, Rajiv V. Joshi, Werner Rausch
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Patent number: 7682897Abstract: A process for fabricating a dynamic random access memory is provided. In this fabrication process, the steps of forming the silicon layer, and performing the ion implantation process and the removing process are repeated at least twice and the oxidation process is performed once to form an oxidation spacer that is larger than the landing area for a bit line contact in the prior art. Therefore, when defining a bit line contact opening, a larger process window is fabricated to prevent the occurrence of a short between the bit line contact and the gate of a transistor due to misalignment.Type: GrantFiled: June 5, 2007Date of Patent: March 23, 2010Assignee: Nanya Technology CorporationInventors: Chih-Huang Wu, Chien-Jung Yang
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Patent number: 7470948Abstract: A NAND-type non-volatile semiconductor memory device includes a gate insulating layer on an active region of a semiconductor substrate, first and second select gate structures on the active region, and a memory gate structure therebetween. The first and second select gate structures respectively include a plurality of select gate patterns, and the memory gate structure includes a plurality of storage gate patterns. The gate insulating layer includes a plurality of openings therein exposing portions of the active region between ones of the plurality of select gate patterns of the first and second select gate structures. The device may further include impurity regions in portions of the active region between the gate patterns, and halo regions adjacent ones of the impurity regions in the portions of the active region exposed by the openings in the gate insulating layer. Related fabrication methods are also discussed.Type: GrantFiled: December 28, 2006Date of Patent: December 30, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Tae Park, Jung-Dal Choi
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Publication number: 20080248619Abstract: A process for fabricating a dynamic random access memory is provided. In this fabrication process, the steps of forming the silicon layer, and performing the ion implantation process and the removing process are repeated at least twice and the oxidation process is performed once to form an oxidation spacer that is larger than the landing area for a bit line contact in the prior art. Therefore, when defining a bit line contact opening, a larger process window is fabricated to prevent the occurrence of a short between the bit line contact and the gate of a transistor due to misalignment.Type: ApplicationFiled: June 5, 2007Publication date: October 9, 2008Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Chih-Huang Wu, Chien-Jung Yang
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Patent number: 7348235Abstract: An isolation insulation film is formed in an isolation trench in an upper portion of a silicon substrate. The isolation insulation film has an opening by which inner walls and bottom of the isolation trench are exposed. A lower diffusion layer serving as a lower electrode of capacitors of DRAM cells extends into the inner walls of the isolation trench exposed by the opening, and a dielectric layer is formed in almost constant thickness on the inner walls and bottom of the isolation trench exposed by the opening. An upper electrode is partially buried in the opening. A channel cut layer is formed in the vicinity of the bottom of the opening.Type: GrantFiled: April 27, 2006Date of Patent: March 25, 2008Assignee: Renesas Technology Corp.Inventor: Yoshitaka Fujiishi
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Patent number: 7282406Abstract: In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate.Type: GrantFiled: March 6, 2006Date of Patent: October 16, 2007Assignee: Semiconductor Companents Industries, L.L.C.Inventors: Gordon M. Grivna, Francine Y. Robb
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Patent number: 7166890Abstract: An improved superjunction semiconductor device includes a charged balanced pylon in a body region, where a top of the pylon is large to create slight charge imbalance. A MOSgated structure is formed over the top of the pylon and designed to conduct current through the pylon. By increasing a dimension of the top of the pylon, the resulting device is less susceptible to variations in manufacturing tolerances to obtain a good breakdown voltage and improved device ruggedness.Type: GrantFiled: October 19, 2004Date of Patent: January 23, 2007Inventor: Srikant Sridevan
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Patent number: 7157328Abstract: The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.Type: GrantFiled: January 31, 2005Date of Patent: January 2, 2007Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Helmut Horst Tews, Stephan Kudelka, Kenneth T. Settlemyer
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Patent number: 7148103Abstract: Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by: manufacturing the first electronic circuit (1) with a first conductive layer (6; 6) that is patterned by subjecting an exposed layer portion thereof to Reactive Ion Etching (RIE); manufacturing the second electronic circuit (2) with a second conductive layer (6; 8) that is patterned by subjecting an exposed layer portion thereof to RIE; providing a tile structure (25; 26); providing the tile structure (25; 26) with at least one dummy conductive layer (6; 8) produced in the same processing step as the second conductive layer (6; 8); and exposing the dummy conductive layer (6; 8), at least partially, to obtain an exposed dummy layer portion, and RIE-etching of that exposed portion too when the second (6; 8) conductive layer is subjected to RIE.Type: GrantFiled: October 16, 2002Date of Patent: December 12, 2006Assignee: Koninklijke Philips Electronics N.V.Inventors: Antonius Maria Petrus Johannes Hendriks, Guido Jozef Maria Dormans, Robertus Dominicus Joseph Verhaar
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Patent number: 7098100Abstract: The present invention discloses a trench capacitor formed in a trench in a semiconductor substrate. The trench capacitor comprises a bottom electrode positioned on a lower outer surface of the trench, a dielectric layer positioned on an inner surface of the bottom electrode, a top electrode positioned on the dielectric layer, a collar oxide layer positioned on an upper inner surface of the trench, a buried conductive strap positioned on the top electrode, and an interface layer made of silicon nitride positioned at the side of the buried conductive strap. The bottom electrode, the dielectric layer and the top electrode form a capacitive structure. The collar oxide layer includes a first block and a second block, and the height of the first block is larger than the height of the second block. The interface layer is positioned on a portion of the inner surface of the trench above the second block.Type: GrantFiled: April 26, 2005Date of Patent: August 29, 2006Assignee: Promos Technologies Inc.Inventors: Hui Min Li, Jung Wu Chien, Chao Hsi Chung, Ming Hung Lin
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Patent number: 7045417Abstract: A method of manufacturing a semiconductor device, which comprises forming a first semiconductor film on a surface of a semiconductor substrate, adsorbing a first impurity on a surface of the first semiconductor film, adsorbing a second impurity on the surface of the first semiconductor film, forming a second semiconductor film on the surface of the first semiconductor film, and solid-phase-diffusing the first impurity and the second impurity into a region of the semiconductor substrate which is located adjacent to the first and second semiconductor films to thereby form a first diffusion region containing the first impurity and a second diffusion region containing the second impurity, a concentration of the first impurity in the first diffusion region being higher than that of the second impurity in the second diffusion region, and the first diffusion region having the bottom thereof covered by the second diffusion region.Type: GrantFiled: February 22, 2005Date of Patent: May 16, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Kasai, Miki Kawase, Takashi Suzuki, Motoya Kishida
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Patent number: 7015091Abstract: A DRAM memory cell and a method of making a DRAM memory cell are provided. The DRAM memory cell includes a semiconductor substrate, including a trench formed therein and a buried plate region, at least a first doped region and a second doped region provided on a sidewall of the trench above the buried plate region in the substrate, where the first doped region contains carbon and the second doped region contains germanium provided in a portion of the first region, a dielectric layer formed on the bottom and sidewall of the trench, at least one polysilicon layer deposited in the trench and on the dielectric layer to cover the dielectric layer, and a transistor formed on a surface of the semiconductor substrate.Type: GrantFiled: November 18, 2004Date of Patent: March 21, 2006Assignee: ProMOS Technologies, Inc.Inventor: Yung Hsien Wu
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Patent number: 6987044Abstract: A method for forming a volatile memory structure. A buried trench capacitor in each of a pair of neighboring trenches formed in a substrate. An asymmetric collar insulating layer is formed over an upper portion of the sidewall of each trench and has a high and a low level portions. A conductive layer is formed overlying the buried trench capacitor and below the surface of the substrate. The high level portion is adjacent to the substrate between the neighboring trenches and the low level portion is covered by the conductive layer. A dielectric layer is formed overlying the conductive layer. Two access transistors are formed on the substrate outside of the pair of the neighboring trenches, respectively, which have source/drain regions electrically connecting to the conductive layer. A volatile memory structure is also disclosed.Type: GrantFiled: September 25, 2003Date of Patent: January 17, 2006Assignee: ProMOS Technologies Inc.Inventors: Shih-Lung Chen, Yueh-Chuan Lee
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Patent number: 6962847Abstract: A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided. A collar dielectric layer is conformally formed on the trench bottom portion, and the trench is filled with a conducting layer. The collar dielectric layer is etched below the level of the surface of the conducting layer to form a groove between the conducting layer and the trench. The groove is filled with a doped conducting layer. The dopant in the doped conducting layer is diffused to the semiconductor substrate in an ion diffusion area as a buried strap. The conducting layer and the doped conducting layer are etched below the ion diffusion area. A top trench insulating layer is formed on the bottom of the trench, wherein the top trench insulating layer is lower than the ion diffusion area.Type: GrantFiled: May 14, 2004Date of Patent: November 8, 2005Assignee: Nanya Technology CorporationInventors: Cheng-Chih Huang, Sheng-Wei Yang, Neng-Tai Shih, Chen-Chou Huang
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Patent number: 6953725Abstract: A method of fabricating a memory device having a deep trench capacitor is described. A first conductive layer is formed in the lower and middle portions of a deep trench in a substrate. An undoped semiconductor layer is formed in the upper portion of the deep trench. A mask layer is formed on the substrate, wherein the mask layercovers the periphery of the undoped semiconductor layer that is adjacent to the neighboring region, pre-defined for the active region of the deep trench. An ion implantation process is performed to implant dopants into the undoped semiconductor layer exposed by the mask layer so as to form a second conductive layer. The first and the second conductive layers constitute the upper electrode of the deep trench capacitor.Type: GrantFiled: August 14, 2003Date of Patent: October 11, 2005Assignee: Nanya Technology Corp.Inventors: Ping Hsu, Kuo-Chien Wu
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Patent number: 6946344Abstract: A method for forming a trench capacitor. A semiconductor substrate with a trench is provided, and a trench capacitor is formed in the trench with a storage node and a node dielectric layer. The top portion of the trench is ion implanted to a predetermined angle to form an ion doped area on a sidewall of the top portion of the trench and a top surface of the trench capacitor. The ion doped area is oxidized to form an oxide layer. A sidewall semiconductor layer is formed on another sidewall using the oxide layer as a mask, and then the oxide layer is removed. A barrier layer is conformally formed on the surface of the trench, and the trench is filled with a conducting layer.Type: GrantFiled: July 16, 2003Date of Patent: September 20, 2005Assignee: Nanya Technology CorporationInventors: Shih-Chung Chou, Yi-Nan Chen, Tzu-Ching Tsai
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Patent number: 6927123Abstract: A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and the semiconductor substrate to act as an isolation. The capacitor wire and the collar dielectric layer are etched to a predetermined depth, such that a gap is formed between the spacer and the capacitor wire and the collar dielectric layer. Ions are doped into the exposed semiconductor substrate to form an ion doped area acting as a buried strap. The spacer is removed, and an exposed collar dielectric layer is etched below the level of the surface of the capacitor wire, and a groove is formed between the capacitor wire and the trench sidewall to fill with a conducting layer.Type: GrantFiled: May 14, 2004Date of Patent: August 9, 2005Assignee: Nanya Technology CorporationInventors: Cheng-Chih Huang, Sheng-Wei Yang, Neng-Tai Shih, Chen-Chou Huang
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Patent number: 6908859Abstract: A transistor is formed in a semiconductor substrate. A deep n-well region is used in conjunction with a shallow n-well region. A lightly doped drain extension region is disposed between a drain region and a gate conductor. The use of the regions and against the backdrop of region provides for a very high breakdown voltage as compared to a relatively low channel resistance for the device.Type: GrantFiled: October 8, 2002Date of Patent: June 21, 2005Assignee: Texas Instruments IncorporatedInventors: Sameer P. Pendharkar, Taylor R. Efland, William Nehrer
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Patent number: 6902982Abstract: A trench capacitor process for preventing parasitic leakage. The process is capable of blocking leakage current from a parasitic transistor adjacent to the trench, and includes the steps of forming a doping layer and a cap layer covering portions of the sidewall of the trench and performing an annealing process on the doping layer to form a dopant region in the substrate adjacent to each sidewall of the trench and blocks leakage current from a parasitic transistor adjacent to the trench.Type: GrantFiled: October 9, 2003Date of Patent: June 7, 2005Assignee: Promos Technologies Inc.Inventor: Shih-Fang Chen
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Patent number: 6893921Abstract: In a nonvolatile memory cell, the floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.Type: GrantFiled: April 10, 2003Date of Patent: May 17, 2005Assignee: Mosel Vitelic, Inc.Inventor: Yi Ding
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Patent number: 6875653Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.Type: GrantFiled: August 2, 2002Date of Patent: April 5, 2005Assignee: ProMOS Technologies Inc.Inventor: Ting-Shing Wang
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Patent number: 6872621Abstract: A method for removal of hemispherical grained silicon (HSG) in a deep trench is described. A buried silicon germanium (SiGe) layer serving as an etch stop layer is formed in the collar region of the trench, followed by depositing a HSG layer. The HSG layer is then successfully striped by wet etching with a potassium hydroxide/propanone/water etchant, that is, without damage to the trench sidewalls, since a good etch rate selectivity between the HSG layer and the SiGe layer is obtained by the wet etchant. In addition, no etch stop layer exists between the HSG layer and the bottom of the trench when manufacturing trench capacitors in accordance with the method; capacitance degradation is therefore not of concern.Type: GrantFiled: January 14, 2004Date of Patent: March 29, 2005Assignee: Promos Technologies Inc.Inventor: Yung-Hsien Wu
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Patent number: 6838335Abstract: A semiconductor memory is fabricated with a vertical transistor situated in an upper section of a trench above a trench capacitor. First, an auxiliary insulation layer is applied to the conductive material of an inner electrode or to a connecting material of the trench capacitor. The connecting material is situated on the inner electrode, so that, during an epitaxial deposition, semiconductor material grows only on the uncovered sidewalls in the upper section of the trench. A nitride layer, is deposited conformally and the residual cavity between the inner electrode and the epitaxial semiconductor layer is filled with a doped further conductive material. The nitride layer isolates the epitaxial semiconductor layer from the further conductive material, so that no crystal lattice defects can propagate from there into the epitaxial semiconductor layer. Dopants are outdiffused from the further conductive material into the epitaxial semiconductor layer to form a doping region.Type: GrantFiled: July 25, 2003Date of Patent: January 4, 2005Assignee: Infineon Technologies AGInventors: Dietrich Bonart, Gerhard Enders, Peter Voigt
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Patent number: 6828191Abstract: A trench capacitor, in particular for use in a semiconductor memory cell, has a trench formed in a substrate; an insulation collar formed in an upper region of the trench; an optional buried plate in the substrate region serving as a first capacitor plate; a dielectric layer lining the lower region of the trench and the insulation collar as a capacitor dielectric; a conductive second filling material filled into the trench as a second capacitor plate; and a buried contact underneath the surface of the substrate. The substrate has, underneath its surface in the region of the buried contact, a doped region introduced by implantation, plasma doping and/or vapor phase deposition. A tunnel layer, in particular an oxide, nitride or oxinitride layer, is preferably formed at the interface of the buried contact. A method for producing a trench capacitor is also provided.Type: GrantFiled: July 28, 1999Date of Patent: December 7, 2004Assignee: Siemens AktiengesellschaftInventors: Kai Wurster, Martin Schrems, Jürgen Faul, Klaus-Dieter Morhard, Alexandra Lamprecht, Odile Dequiedt
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Patent number: 6821842Abstract: A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure. The doped region is formed in a self-aligned process by conducting a tilt implantation implanting ions into the substrate through the upper portion of the capacitor trench adjacent to the channel region after forming the trench but before the definition of the active region.Type: GrantFiled: February 18, 2004Date of Patent: November 23, 2004Assignee: ProMOS Technologies Inc.Inventors: Yueh-Chuan Lee, Shih-Lung Chen
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Patent number: 6770529Abstract: The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.Type: GrantFiled: June 30, 2003Date of Patent: August 3, 2004Assignee: Electronics and Telecommunications Research InstituteInventors: Dae Woo Lee, Tae Moon Roh, II Yong Park, Yil Suk Yang, Jong Dae Kim
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Patent number: 6767787Abstract: Methods of forming a channel region between isolation regions of an integrated circuit substrate are disclosed. In particular, a mask can be formed on an isolation region that extends onto a portion of the substrate adjacent to the isolation region to provide a shielded portion of the substrate adjacent to the isolation region and an exposed portion of the substrate spaced apart from the isolation region having the shielded portion therebetween. A channel region can be formed in the exposed portion of the substrate. Related integrated circuits are also discussed.Type: GrantFiled: June 26, 2001Date of Patent: July 27, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Gwan-byeob Koh, Ki-nam Kim
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Patent number: 6706577Abstract: A method of simultaneously forming differential gate oxide for both high and low voltage transistors using a two-step wet oxidation process is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas and wherein there is at least one low voltage area in which a low voltage transistor will be formed and at least one high voltage area in which a high voltage transistor will be formed. The surface of the semiconductor substrate is wet oxidized to form a first layer of gate oxide on the surface of the semiconductor substrate in the active areas. The low voltage active area is covered with a mask. The surface of the semiconductor substrate is wet oxidized again where it is not covered by the mask to form a second layer of gate oxide under the first gate oxide layer in the high voltage active area. The mask is removed.Type: GrantFiled: April 26, 1999Date of Patent: March 16, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jih-Churng Twu, Syun-Ming Jang, Chen-Hua Yu
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Patent number: 6635526Abstract: Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56 cover the dram array 12 and a gate oxide layer 42 and an undoped polysilicon layer 44 cover the support area 14. A common mask is applied and patterned over the substrate to define the wordlines line structures in the dram array 12 and the gate structures in the support 14. The unwanted portions of the layers 54, 56, 42 and 44 are removed by etching.Type: GrantFiled: June 7, 2002Date of Patent: October 21, 2003Assignee: Infineon Technologies AGInventors: Rajeev Malik, Rama Divakaruni, Rajesh Rengarajan
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Patent number: 6586300Abstract: A trench top isolation (TTI) layer (148) and method of forming thereof for a vertical DRAM. A first assist layer (134) is disposed over trench sidewalls (133) and trench capacitor top surfaces (131). A second assist layer (136) is disposed over the first assist layer (134). The second assist layer (136) is removed from over the trench capacitor top surface (131), and the first assist layer (134) is removed from the trench capacitor top surface (131) using the second assist layer (136) as a mask. The second assist layer (136) is removed, and a first insulating layer (140) is disposed over the first assist layer (134) and trench capacitor top surface (131). A second insulating layer (142) is disposed over the first insulating layer (140), and the second insulating layer (142) is removed from the trench sidewalls (133). The first insulating layer (140) and the first assist layer (134) are removed from the trench sidewalls (133).Type: GrantFiled: April 18, 2002Date of Patent: July 1, 2003Assignee: Infineon Technologies AGInventors: Klaus M. Hummler, Arnd R. Scholz
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Patent number: 6569728Abstract: A method for forming a capacitor by stacking impurity-doped polysilicon layers having different concentrations to form a bottom electrode, treating surfaces of the bottom electrode to prevent a low dielectric constant material from being generated on the surface of the bottom electrode, and forming a dielectric layer and a top electrode on the bottom electrode.Type: GrantFiled: August 28, 2001Date of Patent: May 27, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Tae-Hyeok Lee, Seung-Woo Jin, Hoon-Jung Oh
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Patent number: 6500707Abstract: A trench is formed in a substrate with an upper region and a lower region. The trench is subsequently widened in its upper region and in its lower region by isotropic etching. In the upper region, an insulating collar is formed that is designated as a buried insulating collar due to the widened trench. The insulating collar is removed in the vicinity of the surface of the substrate, through which the substrate is exposed in this region. Here, a selective epitaxial layer is subsequently grown in the trench, through which a subsequently formed selection transistor can be formed in perpendicular fashion over the trench, or very close to the trench. In addition, through the widened trench the electrode surface of the capacitor electrodes is enlarged, which ensures an increased storage capacity.Type: GrantFiled: March 19, 2002Date of Patent: December 31, 2002Assignee: Infineon Technologies AGInventor: Martin Schrems