Including Doping Of Trench Surfaces Patents (Class 438/246)
  • Patent number: 9269828
    Abstract: Devices and methods for forming charge storage regions are disclosed. In one embodiment, a semiconductor device comprises a semiconductor layer having a trench, charge storage layers formed at both side surfaces of the trench, a wordline buried in the trench in contact with the charge storage layers, and source-drain regions formed in the semiconductor layer at both sides of the trench.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: February 23, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventor: Shin Iwase
  • Patent number: 9245684
    Abstract: A method for manufacturing a transformer device includes providing a glass substrate having a first side and a second side arranged opposite the first side, forming a first recess in the glass substrate at the first side of the glass substrate, forming a second recess in the glass substrate at the second side of the glass substrate opposite to the first recess, forming a first coil in the first recess, and forming a second coil in the second recess.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: January 26, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Friedrich Kroener, Carsten von Koblinski
  • Patent number: 9142445
    Abstract: Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: September 22, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Albert Wu, Runzi Chang
  • Patent number: 9059132
    Abstract: A capacitor and method for fabricating the same. In one configuration, the capacitor has a silicon substrate, a first and a second silicon dioxide layer over the silicon substrate, and silicon nitride fins between the silicon dioxide layers. The capacitor further includes a dielectric layer over the silicon nitride fins and metal vias in the dielectric layer.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8940388
    Abstract: Methods of forming an insulative element are described, including forming a first metal oxide material having a first dielectric constant, forming a second metal oxide material having a second dielectric constant different from the first, and heating at least portions of the structure to crystallize at least a portion of at least one of the first dielectric material and the second dielectric material. Methods of forming a capacitor are described, including forming a first electrode, forming a dielectric material with a first oxide and a second oxide over the first electrode, and forming a second electrode over the dielectric material. Structures including dielectric materials are also described.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: January 27, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Vassil Antonov, Jennifer K. Sigman, Vishwanath Bhat, Matthew N. Rocklein, Bhaskar Srinivasan, Chris Carlson
  • Patent number: 8936992
    Abstract: Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 8846470
    Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 8835250
    Abstract: A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jonathan E. Faltermeier, Veeraraghavan S. Basker, Kangguo Cheng, Theodorus Eduardus Standaert
  • Patent number: 8796089
    Abstract: An embodiment relates to a method of forming a semiconductor structure, comprising: forming a first semiconductor layer; forming a second semiconductor layer over the first semiconductor layer; forming a third semiconductor layer over the second semiconductor layer; forming an opening in the first, second and third semiconductor layers; forming a conductive region within the first, the and third semiconductor layer, the conductive region surrounding the opening, the conductive region being electrically coupled to the first semiconductor layer; forming a dielectric layer in the opening and over the conductive region; and forming a conductive layer over the dielectric layer in the opening.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: August 5, 2014
    Assignee: Infineon Technologies AG
    Inventors: Detlef Wilhelm, Guenter Pfeifer, Bernd Eisener, Dieter Claeys
  • Patent number: 8642423
    Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian W. Messenger, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
  • Patent number: 8592883
    Abstract: An embodiment may be a semiconductor structure, comprising; a workpiece having a front side and a back side; and a capacitor disposed in the workpiece, the capacitor including a bottom electrode electrically coupled to a back side of said workpiece. In an embodiment, the bottom electrode may form a conductive pathway to the front side of the workpiece. In an embodiment, the capacitor may be a trench capacitor.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: November 26, 2013
    Assignee: Infineon Technologies AG
    Inventors: Dieter Claeys, Bernd Eisener, Guenter Pfeifer, Detlef Wilhelm
  • Patent number: 8563446
    Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ashima B. Chakravarti, Jacob B. Dadson, Paul J. Higgins, Babar A. Khan, John J. Moore, Christopher C. Parks, Rohit S. Takalkar
  • Patent number: 8557656
    Abstract: A non-planar transistor having floating body structures and methods for fabricating the same are disclosed. In certain embodiments, the transistor includes a fin having upper and lower doped regions. The upper doped regions may form a source and drain separated by a shallow trench formed in the fin. During formation of the fin, a hollow region may be formed underneath the shallow trench, isolating the source and drain. An oxide may be formed in the hollow region to form a floating body structure, wherein the source and drain are isolated from each other and the substrate formed below the fin. In some embodiments, independently bias gates may be formed adjacent to walls of the fin. In other embodiments, electrically coupled gates may be formed adjacent to the walls of the fin.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: October 15, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8557657
    Abstract: A semiconductor device includes a substrate having a first doped portion to a first depth and a second doped portion below the first depth. A deep trench capacitor is formed in the substrate and extends below the first depth. The deep trench capacitor has a buried plate that includes a dopant type forming an electrically conductive connection with second doped portion of the substrate and being electrically insulated from the first doped portion.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Wilfried E. Haensch, Effendi Leobandung, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8546234
    Abstract: A semiconductor process is provided. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. Using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening and the side wall is covered by the mask layer. Using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion. A conversion process is performed, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: October 1, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Wen-Chieh Wang, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8502294
    Abstract: A semiconductor process for a memory array with buried digit lines is described. A first trench is formed in a semiconductor substrate. A liner layer is formed on the sidewall of the first trench. A second trench is formed in the substrate under the first trench. A mask layer is formed at the bottom of the second trench. An isotropic doping process is performed using the liner layer and the mask layer as a mask to form a digit-side junction only in the substrate at the sidewall of the second trench.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: August 6, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Shyam Surthi, Lars Heineck
  • Patent number: 8491799
    Abstract: A method for forming a magnetic tunnel junction cell includes forming a pinning layer, a pinned layer, a dielectric layer and a free layer over a first electrode, forming a second electrode on the free layer, etching the free layer and the dielectric layer using the second electrode as an etch barrier to form a first pattern, forming a prevention layer on a sidewall of the first pattern, and etching the pinned layer and the pinning layer using the second electrode and the prevention layer as an etch barrier to form a second pattern.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: July 23, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin-Ki Jung
  • Publication number: 20130146957
    Abstract: A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.
    Type: Application
    Filed: December 9, 2011
    Publication date: June 13, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 8324014
    Abstract: The present invention relates to a process for depositing films on a substrate by chemical vapour deposition (CVD) or physical vapour deposition (PVD), said process employing at least one boron compound. This process is particularly useful for fabricating photovoltaic solar cells. The invention also relates to the use of boron compounds for conferring optical and/or electrical properties on materials in a CVD or PVD deposition process. This process is also particularly useful for fabricating a photovoltaic solar cell.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: December 4, 2012
    Assignee: L'Air Liquide Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges Claude
    Inventors: Audrey Pinchart, Denis Jahan
  • Patent number: 8299515
    Abstract: Aspects of the invention provide for methods of forming a deep trench capacitor structure. In one embodiment, aspects of the invention include a method of forming a deep trench capacitor structure, including: forming a deep trench within a semiconductor substrate; depositing a first liner within the deep trench; filling a lower portion of the deep trench with a filler material; depositing a second liner within an upper portion of the deep trench; removing the filler material, such that the lower portion of the deep trench includes only the first liner and the upper portion of the deep trench includes the first liner and the second liner; forming a high doped region around the lower portion of the deep trench; and removing the first liner within the lower portion of the deep trench and the second liner within the upper portion of the deep trench.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joseph E. Ervin, Yanli Zhang
  • Patent number: 8278703
    Abstract: A non-planar transistor having floating body structures and methods for fabricating the same are disclosed. In certain embodiments, the transistor includes a fin having upper and lower doped regions. The upper doped regions may form a source and drain separated by a shallow trench formed in the fin. During formation of the fin, a hollow region may be formed underneath the shallow trench, isolating the source and drain. An oxide may be formed in the hollow region to form a floating body structure, wherein the source and drain are isolated from each other and the substrate formed below the fin. In some embodiments, independently bias gates may be formed adjacent to walls of the fin. In other embodiments, electrically coupled gates may be formed adjacent to the walls of the fin.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: October 2, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8236710
    Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ashima B. Chakravarti, Jacob B. Dadson, Paul J. Higgins, Babar A. Khan, John J. Moore, Christopher C. Parks, Rohit S. Takalkar
  • Patent number: 8232162
    Abstract: A method of forming a deep trench structure for a semiconductor device includes forming a mask layer over a semiconductor substrate. An opening in the mask layer is formed by patterning the mask layer, and a deep trench is formed in the semiconductor substrate using the patterned opening in the mask layer. A sacrificial fill material is formed over the mask layer and into the deep trench. A first portion of the sacrificial fill material is recessed from the deep trench and a first dopant implant forms a first doped region in the semiconductor substrate. A second portion of the sacrificial fill material is recessed from the deep trench and a second dopant implant forms a second doped region in the semiconductor substrate, wherein the second doped region is formed underneath the first doped region such that the second doped region and the first doped region are contiguous with each other.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang, Yanli Zhang
  • Patent number: 8211769
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of active regions that are separated from each other by a plurality of trenches, respectively, wherein the trenches are formed by etching a substrate, forming an insulation layer having openings that each expose a portion of a first sidewall of each active region, forming a filling layer which fills the openings, forming a diffusion control layer over a substrate structure including the filling layer, and forming a junction on a portion of the first sidewall of each active region.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: July 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Bo-Mi Lee
  • Patent number: 8143659
    Abstract: A capacitor is described which includes a substrate with a doped area of the substrate forming a first electrode of the capacitor. A plurality of trenches is arranged in the doped area of the substrate, the plurality of trenches forming a second electrode of the capacitor. An electrically insulating layer is arranged between each of the plurality of trenches and the doped area for electrically insulating the trenches from the doped area. The doped area includes first open areas and at least one second open area arranged between neighboring trenches of the plurality of trenches, wherein the at least one open area is arranged below the at least one substrate contact. A shortest first distance between neighboring trenches is separated by the first open areas and is shorter than a shortest second distance between neighboring trenches separated by the at least one second open area.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: March 27, 2012
    Assignee: Infineon Technologies AG
    Inventor: Stefan Pompl
  • Patent number: 8084322
    Abstract: Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: December 27, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Chandra Mouli
  • Patent number: 7955927
    Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: June 7, 2011
    Assignee: Nanya Technology Corporation
    Inventors: Shian-Jyh Lin, Yu-Pi Lee, Ming-Yuan Huang, Jar-Ming Ho, Shun-Fu Chen, Tse-Chuan Kuo
  • Patent number: 7951666
    Abstract: Disclosed herein are embodiments of a deep trench capacitor structure and a method of forming the structure that incorporates a buried capacitor plate contact that is simultaneously formed using an adjacent deep trench. This configuration eliminates the need for additional photolithographic processing, thereby, optimizing process windows. This configuration further eliminates the need to form the deep trench capacitor through an N-doped diffusion region connector and, thereby, allows for greater design flexibility when connecting the deep trench capacitor to another integrated circuit structure (e.g., a memory cell or decoupling capacitor array). Also, disclosed herein are embodiments of another integrated circuit structure and method, and more specifically, a memory cell (e.g., a static random access memory (SRAM) cell)) and method of forming the memory cell that incorporates one or more of these deep trench capacitors in order to minimize or eliminate soft errors.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: May 31, 2011
    Assignee: International Business Machines Corporation
    Inventors: Herbert L. Ho, Steven M. Shank
  • Patent number: 7915162
    Abstract: A method of forming a semiconductor device. A first dielectric layer is deposited on and in direct mechanical contact with the substrate. A first hard mask is deposited on the first dielectric layer. A first and second trench is formed within the first dielectric layer and the first hard mask. The second trench is wider than the first trench. A first conformal liner is deposited over the first hard mask and within the first and second trenches, a portion of which is removed, leaving a remaining portion of the first conformal liner in direct physical contact with the substrate, the first dielectric layer, and the first hard mask, and not on the first hard mask. Copper is deposited over the first conformal liner to overfill fill the first and second trenches and is planarized to remove an excess thereof to form a planar surface of the copper.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Jeffrey P. Gambino, Anthony K. Stamper
  • Patent number: 7910486
    Abstract: A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: March 22, 2011
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Patent number: 7883984
    Abstract: A method of manufacturing a flash memory device may include forming a trench, defining at least a common source region, on a semiconductor substrate, forming a gate poly over the semiconductor substrate, performing an ion implantation process employing a first photoresist pattern and the gate poly as a mask, wherein the ion implantation process forms a source/drain junction on the semiconductor substrate, forming a recess common source region in the trench by using a second photoresist pattern, and performing an ion implantation process on the recess common source region.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: February 8, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Ji-Hwan Park
  • Patent number: 7879672
    Abstract: A deep trench structure process for forming a deep trench in a silicon on insulator (SOI) substrate. The SOI substrate has a bulk silicon layer, a buried oxide (BOX) layer and an SOI layer. In the process, the trench fill is recessed only to a level within the SOI layer so as to avoid lateral etching of the BOX layer. The buried strap is then formed followed by the STI oxide.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Byeong Yeol Kim, James Patrick Norum
  • Patent number: 7863130
    Abstract: System and method for creating stressed polycrystalline silicon in an integrated circuit. A preferred embodiment includes manufacturing an integrated circuit, including forming a trench in an integrated circuit substrate, forming a cavity within the integrated circuit substrate, wherein the cavity is linked to the trench, depositing a dielectric layer within the cavity, and depositing polycrystalline silicon over the dielectric layer, wherein an inherent stress is induced in the polycrystalline silicon that grows on the dielectric layer. The dielectric layer may be, for example, silicon aluminum oxynitride (SiAlON), mullite (3Al2O3.2SiO2), and alumina (Al2O3).
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: January 4, 2011
    Assignee: Infineon Technologies AG
    Inventors: Matthias Hierlemann, Chandrasekhar Sarma
  • Patent number: 7859026
    Abstract: A semiconductor device and methods for its fabrication are provided. The semiconductor device comprises a trench formed in the semiconductor substrate and bounded by a trench wall extending from the semiconductor surface to a trench bottom. A drain region and a source region, spaced apart along the length of the trench, are formed along the trench wall, each extending from the surface toward the bottom. A channel region is formed in the substrate along the trench wall between the drain region and the source region and extending along the length of the trench parallel to the substrate surface. A gate insulator and a gate electrode are formed overlying the channel.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: December 28, 2010
    Assignee: Spansion LLC
    Inventor: William A. Ligon
  • Patent number: 7808029
    Abstract: A mask structure and process for forming trenches in a silicon carbide or other wafer, and for implanting impurities into the walls of the trenches using the same mask where the mask includes a thin aluminum layer and a patterned hard photoresist mask. A thin LTO oxide may be placed between the metal layer and the hard photoresist mask.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: October 5, 2010
    Assignee: Siliconix Technology C.V.
    Inventors: Luigi Merlin, Giovanni Richieri, Rossano Carta
  • Patent number: 7803701
    Abstract: A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: September 28, 2010
    Assignee: Nanya Technology Corporation
    Inventors: Shian-Jyh Lin, Shun-Fu Chen, Tse-Chuan Kuo, An-Hsiung Liu
  • Patent number: 7785959
    Abstract: A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jack A. Mandelman, Carl J. Radens, Geng Wang
  • Publication number: 20100213523
    Abstract: A deep trench structure process for forming a deep trench in a silicon on insulator (SOI) substrate. The SOI substrate has a bulk silicon layer, a buried oxide (BOX) layer and an SOI layer. In the process, the trench fill is recessed only to a level within the SOI layer so as to avoid lateral etching of the BOX layer. The buried strap is then formed followed by the STI oxide.
    Type: Application
    Filed: February 23, 2009
    Publication date: August 26, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Byeong Yeol Kim, James Patrick Norum
  • Patent number: 7759191
    Abstract: The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate and comprises an outer electrode, an inner electrode, and a node dielectric layer located between the outer electrode and the inner electrode. The vertical transistor is located over the trench capacitor and comprises a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The channel region of the vertical transistor is located in a tensilely or compressively strained semiconductor layer that is oriented perpendicularly to a surface of the semiconductor substrate. Preferably, the tensilely or compressively strained semiconductor layer is embedded in an insulator structure, so that the vertical transistor has a semiconductor-on-insulator (SOI) configuration.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Jack A. Mandelman
  • Patent number: 7741178
    Abstract: A method for fabricating a vertical channel transistor in a semiconductor device includes forming a plurality of pillars arranged in a first direction and a second direction crossing the first direction over a substrate, wherein each of the pillars includes a hard mask pattern thereon, forming a bit line region in the substrate between the pillars, forming a first sidewall insulation layer on a sidewall of each of the pillars, forming an insulation layer for filling a space between the pillars, forming a mask pattern for exposing the substrate between lines of the pillars arranged in the first direction over a resulting structure including the insulation layer, etching the insulation layer and the substrate using the mask pattern as an etch barrier to form a trench for defining a bit line in the substrate, and forming a second sidewall insulation layer over a resulting structure including the trench.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: June 22, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hong-Gu Yi
  • Patent number: 7713814
    Abstract: Method of limiting the lateral extent of a trench capacitor by a dielectric spacer in a hybrid orientations substrate is provided. The dielectric spacer separates a top semiconductor portion from an epitaxially regrown portion, which have different crystallographic orientations. The deep trench is formed as a substantially straight trench within the epitaxially regrown portion such that part of the epitaxially regrown portion remains overlying the dielectric spacer. The substantially straight trench is then laterally expanded to form a bottle shaped trench and to provide increased capacitance. The lateral expansion of the deep trench is self-limited by the dielectric spacer above the interface between the handle substrate and the buried insulator layer.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni
  • Patent number: 7709346
    Abstract: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Jin Kim, Kyeong-Koo Chi, Chang-Jin Kang, Hyoung-Sub Kim, Mybong-Cheol Kim, Tae-Rin Chung, Sung-Hoon Chung, Ji-Young Kim
  • Patent number: 7700434
    Abstract: A semiconductor fabrication method. First, a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench includes a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. Next, portions of the blocking layer on the {110} side wall surfaces are removed without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: April 20, 2010
    Assignee: International Businesss Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni
  • Patent number: 7651933
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate in which a gate insulating layer and a pad layer are formed in an active region. A first trench is formed in an isolation region of the substrate. A passivation film is formed to cover the pad layer and fill the first trench. A second trench is formed by patterning the pad layer and removing an exposed semiconductor substrate, the second trench being formed within the first trench. An ion implantation process is performed on the semiconductor substrate exposed through the second trench.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: January 26, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Guee-Hwang Sim
  • Patent number: 7642892
    Abstract: In one aspect, a negative voltage coefficient resistor is provided. The negative voltage coefficient resistor includes an insulative layer positioned between a polycrystalline silicon resistive layer and a silicide layer. Upon application of an appropriate voltage bias at the silicide layer of the resistor, a tunneling current is established across the insulative layer and is supplied to the polycrystalline silicon resistive layer. The tunneling current limits the current flow through the polycrystalline silicon layer, producing a resistor having a negative voltage coefficient of resistance and a reduced temperature coefficient of resistance.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: January 5, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventor: Soon Won Kang
  • Patent number: 7638391
    Abstract: A method for fabricating a semiconductor memory device. A pair of neighboring trench capacitors is formed in a substrate. An insulating layer having a pair of connecting structures therein is formed on the substrate, in which the pair of connecting structures is electrically connected to the pair of neighboring trench capacitors. An active layer is formed on the insulating layer between the pair of connecting structures so as to cover the pair of connecting structures. A pair of gate structures is formed on the active layer to electrically connect to the pair of trench capacitors. A semiconductor memory device is also disclosed.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: December 29, 2009
    Assignee: Nanya Technology Corporation
    Inventors: Chien-Li Cheng, Shian-Jyh Lin, Ming-Yuan Huang
  • Patent number: 7622351
    Abstract: A method of manufacturing a semiconductor device, includes: forming a first and a second trench regions adjacent from each other in a first conductivity type semiconductor base; forming a second conductivity type semiconductor region in the semiconductor base between the first and second trench regions; forming a mask on the second conductivity type semiconductor region, the mask covering a central portion between the first and second trench regions; performing ion implantation of a first conductivity type impurity in the second conductivity type semiconductor region with the mask to form a first conductivity type first region and a first conductivity type second region separated from the first conductivity type first region; and performing heat treatment to diffuse the impurity in the first and second regions and to form a connection region between the first and second regions, connection region being shallower than the first and second regions after the heat treatment.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: November 24, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Kenya Kobayashi
  • Patent number: 7601596
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming trenches in a first side of a semiconductor material and forming a thick oxide layer on the trenches and on the first side. A part of the first side and the trenches is masked using a first mask, and the semiconductor material is doped by implantation through the thick oxide layer while the first mask is present. At least part of the thick oxide layer is removed while the first mask remains.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: October 13, 2009
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Zundel, Franz Hirler, Rudolf Zelsacher, Erwin Bacher
  • Patent number: 7575970
    Abstract: Methods of forming a deep trench capacitor through an SOI substrate, and a capacitor are disclosed. In one embodiment, a method includes forming a trench opening into the SOI substrate to the silicon substrate; depositing a sidewall spacer in the trench opening; etching to form the deep trench into the silicon substrate; forming a first electrode by implanting a dopant into the silicon substrate, whereby the sidewall spacer protects the BOX layer and the silicon layer; removing the sidewall spacer; depositing a node dielectric within the deep trench; and forming a second electrode by depositing a conductor in the deep trench. Implanting creates a substantially uniform depth doped region except at a portion adjacent to a lowermost portion of the deep trench, which may be substantially bulbous. The BOX layer is protected from undercutting by the sidewall spacer, and the implantation removes the need for out-diffusing dopant from silica glass.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: August 18, 2009
    Assignee: International Business Machines Corporation
    Inventors: Herbert L. Ho, Kangguo Cheng, Yoichi Otani, Kevin R. Winstel
  • Patent number: 7553722
    Abstract: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface, wherein the substrate has a first conductive type; a first trench extending from the first surface of the semiconductor substrate in a depth direction; and an epitaxial semiconductor layer having a second conductive type, wherein the epitaxial semiconductor layer is disposed in the first trench. The first trench includes an inner wall as an interface between the semiconductor substrate and the epitaxial semiconductor layer so that the interface provides a PN junction. The first trench has an aspect ratio equal to or larger than 1.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: June 30, 2009
    Assignee: DENSO CORPORATION
    Inventors: Jun Sakakibara, Hitoshi Yamaguchi, Naohiro Suzuki