Abstract: A method of fabricating of a capacitor with low voltage coefficient of capacitance is described. A silicon substrate with field oxide isolations is provided. A buried layer is formed by doping N-type impurities into the substrate as the bottom plate of the capacitor. A dielectric layer is formed by thermal oxidation for the capacitor, and then a polysilicon layer is formed by the low pressure chemical vapor deposition method. A thermal diffusion step is performed to dope phosphorus into the polysilicon layer. After formation of a polysilicide layer by the low pressure chemical vapor deposition method, arsenic ions are implanted into the polysilicon layer and the polysilicide layer. Finally the polysilicide layer and the polysilicon layer are partially etched in consequence, and the top plate of the capacitor is formed.

Abstract: A stacked capacitor that has a large capacitance per unit area (Co), very low voltage coefficient (Kv), and an acceptable parasitic capacitance factor (Kp) is described that uses only one polysilicon layer. The stacked capacitor is formed at the surface of a semiconductor substrate of a first conductivity type. The stacked capacitor has a bottom plate that is formed by a lightly doped well diffused into the surface of the semiconductor substrate. The bottom plate also has a first plurality of interconnected conductive layers of a first conductive material disposed above and aligned with the well, whereby a first conductive layer of the first plurality of conductive layers is connected to the well by multiple contacts distributed over an area of the well.

Abstract: The invention includes a capacitor. The capacitor has a first conductive capacitor electrode, a second conductive capacitor electrode, and a capacitor dielectric material intermediate the first and second capacitor electrodes. The dielectric material contacts both of the first and second capacitor electrodes. All of the dielectric material intermediate the first and second capacitor plates consists of silicon nitride.

Abstract: A method of fabricating a dielectric layer which is application to be used in a capacitor. A first conductive layer is provided. A nitridation step is performed on the first conductive layer, so that a nitride layer is formed on a surface of the first conductive layer. A dielectric layer with a high dielectric constant is formed, followed by a thermal treatment and an oxygen plasma treatment to terminate dangling bonds of the dielectric layer. Consequently, oxygen is distributed on a surface of the dielectric layer and bonded with dangling bonds of the dielectric layer distributed on the surface.

Abstract: A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of the substrate (30) to form a part of a depletion NMOS memory capacitor (21) to be associated with the n-channel MOS memory transistor (12). The implant is performed concurrently with a patterned implant with the same impurity to adjust the threshold and punch-through of the p-channel transistor (44).

Abstract: The phosphorus concentration of an upper electrode and the phosphorus concentration of a lower electrode can be made equally high without loss of adhesion between the polysilicon and a metallic layer. It includes a step of forming a stacked layer structure consisting of: a lower electrode layer provided on an underlay, a dielectric layer provided on this lower electrode layer, and an upper electrode layer consisting of an impurity-doped layer and a metallic layer successively provided on this dielectric layer, and a step of doping the metallic layer with the same impurity as the impurity in the impurity-doped layer prior to heat treatment of the stacked layer structure.

Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.

Abstract: A method for fabricating an integrated circuit includes the steps of forming an isolating insulation film on a portion of a semiconductor substrate, forming a gate insulating film, a first conductive layer, an insulating film and a second conductive layer successively on the semiconductor substrate including the isolating insulation film, selectively removing the second conductive layer and the insulating film to pattern an upper electrode of a capacitor in a capacitor forming region and a dummy gate electrode in a transistor forming region, respectively, forming a lower electrode mask in the capacitor forming region, and selectively removing the first conductive layer and the gate insulating film by using the lower electrode mask and the dummy gate electrode as masks, to form a lower electrode of the capacitor and the gate electrode of the transistor.

Abstract: Methods of forming integrated circuit memory devices, such as DRAM memory cells, include the steps of simultaneously forming storage electrode and bit line contact regions of first conductivity type in a semiconductor region of second conductivity type. The contact regions preferably receive a double dose of first conductivity type dopants. This double dose compensates for etching damage caused during processing and improves the memory cell's refresh characteristics. The preferred methods of forming DRAM memory cells include the steps of forming an electrically insulating layer on a face of a semiconductor substrate containing a region of second conductivity type therein (e.g., P-type) extending to the face, and then forming a word line (or segment thereof) on the electrically insulating layer, opposite the region of second conductivity type.

Abstract: Disclosed are planar DRAM cells including a storage capacitor having a high dielectric constant capacitor dielectric. The DRAM cell also includes an access transistor having a gate dielectric which does not include the high dielectric constant material. A single polysilicon layer is employed to form the gate electrode of the access transistor and a reference plate of the storage capacitor. A disclosed fabrication process forms the high dielectric constant material that is limited to a capacitor region of the DRAM cell and then forms the gate dielectric over an entire active region including both the high dielectric constant material layer at the capacitor region and the semiconductor substrate at the access transistor region. In this manner, a high quality gate dielectric (e.g., silicon oxide) is formed at the access transistor region and a high dielectric constant dielectric layer (e.g., silicon nitride) is formed at the capacitor region.

Abstract: A multilevel capacitor structure compatible with CMOS processing for use in switched capacitor circuits is disclosed. The capacitor structure has an associated parasitic capacitor which is placed in such a way so as to minimize the impact on the performance of a the switched capacitor circuit. The parasitic capacitor is formed between a first plate of the shielded capacitor and a diffusion well within a substrate. The diffusion well is connected to a quiet voltage reference source to isolate the shielded capacitor from noise present on the substrate. The shielded capacitor has a first plate that is fabricated from a first conductive material such as polycrystalline silicon or polycide, a second plate fabricated from a second conductive material such as a first level of metal on an integrated circuit, and a third capacitor plate fabricated from a second level of metal of an integrated circuit.

Abstract: A high-precision, linear MOS-transistor-gate capacitor device is provided by applying a source/drain high-energy, high-dose ion implantation through implant windows in a polysilicon top plate of the capacitor. The ion implantation may be a step of generic MOS source/drain process flow.

Abstract: An improved process of fabricating a read only memory device (ROM's) wherein the buried N+ lines have desirable very narrow widths and are closely spaced. The process provides that masking stripes are formed with vertical sidewalls and that spacers are formed on the sidewalls. The areas between the spacers are filled in. The spacers are etched away to form narrow closely spaced openings. Ions are implanted through the openings to form closely spaced buried lines.

Abstract: A semiconductor memory device includes a semiconductor substrate, a cell array region storing data on the substrate, a periphery circuit region on the substrate, the periphery circuit region controlling input and output of the data stored in the cell, a plurality of word-lines and bit-lines on the cell array region, and a plurality of dummy pattern layers on the periphery circuit region.

Abstract: In the semiconductor device according to the invention, a tubular storage node is formed, then slanting rotation implantation of impurity phosphorus ions is executed for changing the phosphorus concentration and the etching rate at the thermal phosphoric acid treatment time is changed for roughening the surface under good control. Since the surface roughening does not extend to the center of the film of the storage node, the strength of the storage node can be held sufficient. Therefore, the capacitance can be increased.

Abstract: An improved semiconductor device including an MOS capacitance is provided, having enhanced MOS capacitance accuracy. A well of a first conductivity type is formed at the main surface of a semiconductor substrate. The above-described well is removed immediately under a capacitance dope layer.

Abstract: A dielectric layer is formed on a main surface of a semiconductor substrate. A silicon layer is formed on dielectric layer. MOS transistors are formed in silicon layer and include impurity regions in a semiconductor layer. A capacitor is formed by cooperation of the impurity region, the dielectric layer, and the semiconductor substrate. The dielectric layer also serves as an insulating film of an SOI structure. Thus, a semiconductor memory device which achieves high performance and allows high integration can easily be obtained in a DRAM having an SOI structure.

Abstract: An improved method for depositing the polysilicon layer from which a gate pedestal is later formed is described. Deposition takes place in two stages. Initially, the conventional deposition temperature of about 630.degree. C. is used. Then, when the intended thickness of polysilicon has been grown, the temperature is ramped down to about 560.degree. C., without interrupting the deposition process, and growth of the film continues to completion. This is followed by a standard doping step using POCl.sub.3. Polysilicon films formed in this way have been found to have very smooth surfaces because the topmost layer is less subject to uncontrolled grain growth. As a consequence, dielectric layers obtained by oxidizing such films exhibit superior breakdown voltages.

Abstract: A new method of forming an improved buried contact junction is described. Word lines are provided over the surface of a semiconductor substrate. A first insulating layer is deposited overlying the word lines. The first insulating layer is etched away where it is not covered by a buried contact mask to provide an opening to the semiconductor substrate. A layer of tetraethoxysilane (TEOS) silicon oxide is deposited over the first insulating layer and over the semiconductor substrate within the opening. The TEOS layer is anisotropically etched to leave spacers on the sidewalls of the word lines and of the first insulating layer. A first layer of polysilicon is deposited overlying the first insulating layer and within the opening. The first polysilicon layer is doped with dopant which is driven in to form a buried contact junction within the semiconductor substrate under the opening.

Abstract: An integrated circuit is provided having both NMOS transistors and PMOS transistors. The NMOS transistor junction regions are preferably formed before the PMOS transistor junction regions with pre-defined anneal temperatures applied after select implant steps. Both the NMOS and PMOS transistor junction are graded such that the drain areas include a relatively large LDD implant area and the source junctions do not. Whatever LDD area pre-existing in the source implanted with a higher concentration source/drain or MDD implant. The ensuing integrated circuit is therefore a CMOS circuit having asymmetrical transistor junctions and carefully controlled implant and anneal sequences. The asymmetrical junctions are retained, or at least optimized, by controlling the anneal temperatures such that diffusivity distances of n-type implants are relatively similar to p-type implants. Diffusivity is controlled by regulating the post-implant anneal temperatures of p-type implants lesser than previous n-type implants.

Abstract: A fabrication method of a semiconductor device that makes it possible to reduce the number of necessary process steps. After an insulating layer is formed on a semiconductor substructure, a polysilicon layer is formed on the insulating layer. Then, dopant atoms are implanted into the polysilicon layer so that the peak depth of the distribution of the implanted dopant atoms is located at approximately the middle level of the polysilicon layer. The implanted polysilicon layer is subjected to a heat-treatment to thereby form a dielectric region at the middle level of the polysilicon layer due to reaction of the implanted dopant atoms with silicon atoms existing in the polysilicon layer. The remaining lower and upper parts of the polysilicon layer form lower and upper polysilicon regions, respectively. Subsequently, the implanted and heat-treated polysilicon layer is patterned to have a predetermined shape. As the dopant atom to be implanted, oxygen (O) and/or nitrogen (N) is preferably used.

Abstract: A semiconductor processing method of forming dynamic random access memory circuitry includes, a) providing an electrically conductive capacitor cell plate substrate; b) providing an electrically insulative layer over the cell plate; c) providing a layer of semiconductive material on the insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; d) patterning and etching the SOI layer to define active area region islands and isolation trenches between the islands; e) filling the isolation trenches with insulative material; f) providing capacitor openings through the SOI layer and insulative layer into the cell plate substrate; g) providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; h) providing respective capacitor storage nodes over the dielectric layer within the capacitor openings, the respective storage nodes being in ohmic connection with the SOI layer; i) after providing the storage nodes, filling any remaining portions of the capacitor cont

Abstract: A CMOS DRAM integrated circuit includes paired P-type and N-type wells in a substrate. The wells are fabricated using a self-aligning process. Similarly, FETs of the DRAM circuit are fabricated in the wells of the substrate using a self-aligning process to provide FETs of opposite polarity in a DRAM which may have paired memory cells and dummy cells for symmetry of circuitry. One or more layers having an irregular top surface topology may be planarized using mechanical or chemical-mechanical polishing of the topological layer.

Abstract: Methods of forming integrated circuit memory devices, such as DRAM memory cells, include the steps of performing a relatively low dose plug implantation step preferably prior to and after formation of a buried contact hole to expose a storage electrode contact region in a semiconductor substrate. By performing a plug implantation step at a low level prior to formation of a buried contact hole (and after), a memory cell having improved refresh characteristics can be achieved. In particular, the performance of the plug implantation step prior to and after formation of the buried contact hole compensates for substrate damage caused during formation of field oxide isolation regions adjacent the memory cell and during formation of the buried contact hole when the storage electrode contact region is exposed to an etchant.

Abstract: Various circuit techniques to implement continuous-time filters with improved performance are disclosed. The present invention uses RMC type integrators that exhibit lower harmonic distortion. In one embodiment, a novel high-gain two-pole operational amplifier is used along with RMC architecture to achieve lower harmonic distortion. In another embodiment, the present invention uses dummy polysilicon resistors to accurately compensate for the distributed parasitics of the polysilicon resistors used in RMC integrator. In yet another embodiment, the present invention provides an on-chip tuner with a differential architecture for better noise immunity.

Abstract: A capacitor for a semiconductor device is formed by selectively processing a portion of a layer (41, 113) to form an electrode (411, 81, 101, 111) for the capacitor. The selective processing includes selective doping, selective silicidation, selective oxidation, or the like. Contacts can be made to the electrode (411) with a reduced likelihood of the contact electrically shorting the electrodes of the capacitor together. When forming contact openings, misalignment tolerance is increased.