Abstract: In cleaning a substrate which has a metal material and a semiconductor material both exposed at the surface and which has been subjected to a chemical mechanical polishing treatment, the substrate is first cleaned with a first cleaning solution containing ammonia water, etc. and then with a second cleaning solution containing (a) a first complexing agent capable of easily forming a complex with the oxide of said metal material, etc. and (b) an anionic or cationic surfactant.

Abstract: A photoresist pattern through which a first well forming region and a second well forming region are exposed is formed over a semiconductor substrate, used as the mask to dope the semiconductor substrate with an impurity thereby to form buried n-wells, and further used as the mask to dope the same with an impurity thereby to form shallow p-wells in a self-alignment manner over the buried n-wells. Subsequently, the photoresist pattern is removed. After this, a photoresist pattern through which the outer peripheral region of the first well forming region and a third well forming region are exposed is formed over the major surface of the semiconductor substrate, and used as the mask to dope the semiconductor substrate with an impurity thereby to form shallow p-wells.

Abstract: The invention relates to a method for fabricating a capacitor of a semiconductor device including the steps of: forming storage nodes for being connected with predetermined portions of a semiconductor substrate; forming a surface nitride layer by performing a surface nitrification process for preventing formation of an oxide layer on the surface of the storage nodes that deteriorates dielectric characteristic of the layer; forming an alumina (Al2O3) layer as a dielectric layer on the surface nitride layer in a perovskite structure with superior electrical and mechanical strength; and forming a plate electrode on the dielectric layer, thereby forming a capacitor with capacitance high enough to achieve high integration of the semiconductor device.

Abstract: A method for ion implantation of high dielectric constant materials with dopants to improve sidewall stoichiometry is disclosed. Particularly, the invention relates to ion implantation of (Ba,Sr)TiO3 (BST) with Ti dopants. The invention also relates to varying the ion implantation angle of the dopant to uniformly dope the high dielectric constant materials when they have been fabricated over a stepped structure. Additionally, the invention relates to forming a capping layer over a horizontal portion of the BST film to reduce excess dopant from being implanted into the horizontal section of the BST film. The invention also relates to integrated circuits having a thin film high dielectric material with improved sidewall stoichiometry used as an insulating layer in a capacitor structure.

Abstract: A method for forming a lower electrode structure of a capacitor of a semiconductor device, includes the steps of: forming an active region in a semiconductor substrate; forming an insulation layer atop the semiconductor substrate having the active region formed therein; forming a contact hole in the insulation layer, the contact hole exposing the active region; forming a conductive plug connected to the active region through the contact hole, the conductive plug having an upper contact surface; forming a silicide contact on the upper contact surface of the conductive plug; forming a lower electrode layer in electrical contact with the silicide contact, by depositing titanium aluminum nitride on the insulation layer; and patterning the lower electrode layer to form a lower electrode having an upper surface. A natural oxide film is prevented from generating between the interface of the plug and the lower electrode.

Abstract: A method for fabricating poly-spacers used in a semiconductor substrate, comprising: forming an undoped first polysilicon layer on the semiconductor substrate; performing a first ion implantation with a first angle to implant impurities into the first polysilicon layer; performing a second ion implantation with a second angle to implant the impurities into the first polysilicon layer; forming a second polysilicon layer on the first polysilicon layer; and etching the first polysilicon layer and the second polysilicon layer to form spacers.

Abstract: In a semicondutor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material. In another embodiment, a capacitor storage node is formed having an uppermost surface and a side surface joined therewith. A protective cap is formed over the uppe-most surface and a capacitor dielectric layer is formed over the side surface and protective cap. A cell electrode layer is formed over the side surface of the capacitor storage node.

Abstract: There is disclosed a method of manufacturing a capacitor of a semiconductor device by which a CVD TiN film and a MOCVD TiN film, and a polysilicon film are sequentially stacked in forming an electrode on a Ta2O5 dielectric thin film. Therefore, it can prevent changes in thickness of the effective oxide film of the Ta2O5 capacitor against the characteristics of each of the CVD TiN film and the MOCVD TiN film, even after a rapid thermal process. It can also improve the step coverage, thus greatly improving the stability and reliability of the capacitor.

Abstract: A capacitor divider includes two capacitors coupled in series between two voltage sources. A first capacitor is a floating gate capacitor having one plate being the control gate of a floating gate transistor structure and the other plate being a source, drain, and channel region of the floating gate transistor structure. The capacitive divider has the advantage of having at least one floating gate capacitor, can be implemented in a voltage regulator, and works for a variety of voltages across the capacitors.

Abstract: A method of making a capacitor on a conductive surface, preferably on a polysilicon surface includes contamination cleaning the surface with a high density plasma (HDP) of a first gaseous agent, such as hydrogen, then growing a silicon nitride barrier layer on the surface using a high density plasma (HDP) of nitrogen. A layer of tantalum oxide is then deposited on the silicon nitride layer to form a capacitor dielectric layer. A second silicon nitride layer is then grown on the capacitor dielectric layer, also using an HDP nitrogen plasma with the addition of a silicon containing gas, such as silane. Finally, a conductive layer is deposited on the second silicon nitride layer to form the capacitor. The HDP plasma is heated using an inductively coupled radio frequency generator. The invention also includes a capacitor constructed on a conductive surface by the method of the invention.

Abstract: The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-Si on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently.

Abstract: A technique for forming an integrated circuit device having a self-aligned gate layer. The method includes a variety of steps such as providing a substrate, which is commonly a silicon wafer. Field isolation regions including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second trench isolation regions. The isolation regions are made using a reactive ion etching technique. A thickness of material such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region. The substantially planar material region is self-aligned into the recessed region using the removing step.

Abstract: An analog semiconductor device capable of preventing open of interconnection lines and notching due to step between transistor and capacitor regions is disclosed. An analog semiconductor device according to the present invention, includes a semiconductor substrate; a first, a second, and a third isolating layer of trench type formed on the substrate and defining a transistor region and a capacitor region, respectively; a lower electrode of a capacitor formed in the surface of the substrate of the capacitor region; an oxide layer formed under the lower electrode and insulating the lower electrode and the substrate; an gate insulating layer formed on the substrate of the transistor region; an dielectric layer formed on the lower electrode; a gate formed on the gate insulating layer; an upper electrode of the capacitor formed on the dielectric layer.

Abstract: A photoresist pattern through which a first well forming region and a second well forming region are exposed is formed over a semiconductor substrate, used as the mask to dope the semiconductor substrate with an impurity thereby to form buried n-wells, and further used as the mask to dope the same with an impurity thereby to form shallow p-wells in a self-alignment manner over the buried n-wells. Subsequently, the photoresist pattern is removed. After this, a photoresist pattern through which the outer peripheral region of the first well forming region and a third well forming region are exposed is formed over the major surface of the semiconductor substrate, and used as the mask to dope the semiconductor substrate with an impurity thereby to form shallow p-wells.

Abstract: A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source/drain regions are formed on the substrate adjacent to opposite sides of the gate electrodes. N-type impurities, preferably phosphorous atoms, are then implanted into the first source/drain region which will serve as the capacitor buried contact.

Abstract: A method of forming a DRAM capacitor. A hemispherical grain structure is formed on the surface of the bottom electrode of the capacitor. By employing an additional annealing under a dopant contained ambient, the dopant is diffused into the hemispherical grain structure and distributed at the surface area of the hemispherical grain region.

Abstract: An integrated circuit memory device includes a substrate divided into a cell array region, a core region, and a peripheral circuit region. A plurality of memory cells in the memory cell region each comprise a memory cell transistor having first spaced apart source/drain regions of the substrate with a predetermined conductivity. A sensing circuit in the core region of the substrate includes a sensing transistor having second spaced apart source/drain regions of the substrate. Each of the second source/drain regions includes high and low concentration regions of the predetermined conductivity wherein the high and low concentration regions are doped with a common dopant. A peripheral circuit in the peripheral region of the substrate includes a peripheral transistor having third spaced apart source/drain regions wherein each of the third source/drain regions has high and low concentration regions thereof.

Abstract: A method of forming a dynamic random access memory cell such that the gate conductive layer, the bit line contact, the node contact, the bit line and the node contact plug are all formed using self-aligned processes. By employing the self-aligned method of forming DRAM cell, isolation structures are no longer etched in the process of forming the node contact opening. In addition, the aspect ratio of the node contact opening is reduced and processing window is thereby widened.

Abstract: A method of fabricating of a capacitor with low voltage coefficient of capacitance is described. A silicon substrate with field oxide isolations is provided. A buried layer is formed by doping N-type impurities into the substrate as the bottom plate of the capacitor. A dielectric layer is formed by thermal oxidation for the capacitor, and then a polysilicon layer is formed by the low pressure chemical vapor deposition method. A thermal diffusion step is performed to dope phosphorus into the polysilicon layer. After formation of a polysilicide layer by the low pressure chemical vapor deposition method, arsenic ions are implanted into the polysilicon layer and the polysilicide layer. Finally the polysilicide layer and the polysilicon layer are partially etched in consequence, and the top plate of the capacitor is formed.

Abstract: The present invention provides a fabricating method and structure of a dynamic random access memory. In this method, a substrate having a transistor thereon is provided. A bit line is formed on the substrate. The bit line is electrically coupled with the transistor through a contact hole. A second dielectric layer having a node contact opening is formed on the bit line. An etching step is performed to etch the bit line. A concave surface is formed on the sidewall of the bit line. Spacer layers are formed on the sidewalls of the node contact opening. Each spacer layer is used to insulate the concave surface. Thus, from the top-view layout, a portion of the node contact opening can overlap with the bit line. Thus, the size of DRAM is effectively reduced.

Abstract: Methods of forming integrated circuit memory devices, such as DRAM memory cells, include the steps of simultaneously forming storage electrode and bit line contact regions of first conductivity type in a semiconductor region of second conductivity type. The contact regions preferably receive a double dose of first conductivity type dopants. This double dose compensates for etching damage caused during processing and improves the memory cell's refresh characteristics. The preferred methods of forming DRAM memory cells include the steps of forming an electrically insulating layer on a face of a semiconductor substrate containing a region of second conductivity type therein (e.g., P-type) extending to the face, and then forming a word line (or segment thereof) on the electrically insulating layer, opposite the region of second conductivity type.

Abstract: A method of manufacturing a capacitor whose top and bottom electrodes have the nearly equal doping concentrations. In the method, a top surface of the capacitor top electrode is polished by a CMP (chemical mechanical polishing) and then doped using the same doping process as the capacitor bottom electrode, so that other elements can be isolated during the doping process. After forming the capacitor bottom electrode, thermal oxidation is performed so that the injected impurity ions of the capacitor bottom electrode are segregated toward a top surface portion thereof. With this method, a doping concentration at the top surface portion of the capacitor bottom electrode becomes higher than that at other portions thereof, and thereby the capacitor top and bottom electrodes may have a nearly same doping concentration at the interface therebetween.

Abstract: A high-precision, linear MOS-transistor-gate capacitor device is provided by applying a source/drain high-energy, high-dose ion implantation through implant windows in a polysilicon top plate of the capacitor. The ion implantation may be a step of generic MOS source/drain process flow.

Abstract: A new method of fabricating a capacitor and PMOS devices in a mixed-mode product production in which a composite polysilicon top plate electrode is provided which prevents out-diffusion of dopant from the capacitor plate so that there is no auto-doping of the PMOS channel region is described. A layer of gate silicon oxide is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate silicon oxide layer. The first polysilicon layer and gate oxide layer are etched away where they are not covered by a mask to provide a PMOS gate electrode in a first region of the wafer and a bottom plate electrode for the capacitor in a second region of the wafer. A capacitor dielectric layer is deposited over the surface of the wafer. A composite polysilicon layer is deposited overlying the capacitor dielectric layer wherein the composite polysilcon layer comprises a lower doped polysilcon layer and an upper undoped polysilicon layer.

Abstract: A process for fabricating a mixed signal integrated circuit on a substrate, wherein the substrate is partially covered with a field oxide layer. An oxide layer is formed over a portion of the substrate, wherein the portion of the substrate is not covered with the field oxide layer. First impurities are implanted into the substrate, wherein the first impurities damage the oxide layer. A buffer layer is formed over the oxide layer. A polysilicon layer is formed over the buffer layer. Second impurities are implanted into the polysilicon layer, wherein the buffer layer prevents the oxide layer form being damaged by the second impurities. The polysilicon layer is etched to remove the polysilicon layer, wherein the buffer layer prevents the oxide layer and the substrate from being etched. The portion of buffer layer and the damaged oxide layer over the substrate are removed. The gate oxide layer is formed over the substrate.

Abstract: A fabricating method for a DRAM capacitor is provided. A DRAM is formed on a substrate, wherein a transistor has been formed. A first oxide layer is formed over the substrate and a contact window is formed on the first oxide layer to expose a source region of the transistor. Then, a bit line is formed in the contact window, wherein the bit line is connected to the source region of the transistor. A second oxide layer is formed on the bit line and the first oxide layer. Then, a third oxide layer is formed on the second oxide layer. A second contact window is further defined to expose a drain region of the transistor, wherein the drain region has a native oxide layer formed on it. Next, a first polysilicon film is formed on the exposed drain region of the second contact window. A high dosage implantation is used to remove the native oxide layer. Then, a second polysilicon layer is formed over the substrate. Finally, the finishing process followed is performed to complete the fabrication of a DRAM capacitor.

Abstract: In the semiconductor device according to the invention, a tubular storage node is formed, then slanting rotation implantation of impurity phosphorus ions is executed for changing the phosphorus concentration and the etching rate at the thermal phosphoric acid treatment time is changed for roughening the surface under good control. Since the surface roughening does not extend to the center of the film of the storage node, the strength of the storage node can be held sufficient. Therefore, the capacitance can be increased.

Abstract: A method of forming a capacitor includes, a) providing a series of alternating first and second layers of semiconductive material over a node location, a first of the first and second layers having an average conductivity enhancing dopant concentration of greater than about 5.times.10.sup.19 ions/cm.sup.3, a second of the first and second layers having an average conductivity enhancing dopant concentration from 0 ions/cm.sup.3 to about 5.times.10.sup.19 ions/cm.sup.

Abstract: A gate silicon oxide layer is formed on the silicon substrate. A doped layer of polysilicon is formed over the gate silicon oxide layer. The polysilicon layer is patterned to provide the gate electrodes of the transistor. Source/drain regions are formed through ion implantation followed by spacer formation. A node contact oxide is blanket deposited and an opening is formed therein to the silicon substrate at the location of the buried contact. A dual layer of polysilicon is deposited over the node contact oxide and within the opening to the substrate. This dual layer consists of a bottom layer of undoped polysilicon and a top layer of in-situ doped polysilicon wherein the relative thicknesses of the two layers have been determined to optimize both concentration of dopant at the surface of the capacitor node and junction depth. The substrate is annealed to drive in the buried junction. The dual polysilicon layers are patterned to form the capacitor node.

Abstract: A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the active areas; g) a bit line plug extending through the insulating layer and electrically interconnecting the bit line with the other active area, the bit line plug comprising an electrically conductive annular ring. Integrated circuitry, beyond memory devices, utilizing an annular interconnection ring are also disclosed. Such constructions having additional radially inward insulating annular rings and conductive rings are also disclosed. A method of forming a bit line over capacitor array of memory cells having such rings is also disclosed.