Including Additional Field Effect Transistor (e.g., Sense Or Access Transistor, Etc.) Patents (Class 438/258)
  • Patent number: 10449755
    Abstract: A movable member is gripped in a delamination-start configuration, and the other-end side of a rib of a delamination member is pressed towards the other-end side of a flexible plate. The flexible plate then warps and deforms about the other end side of the flexible plate, which is supported by a support member, the flexible plate deforming along the direction in which delamination progresses. In concert with the delamination action, a reinforcing plate also warps and deforms along with the flexible plate, the reinforcing plate being vacuum-chucked to an air-permeable electroconductive sheet on the flexible plate, and the reinforcing plate is sequentially delaminated from a substrate 2 along the direction in which delamination progresses.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: October 22, 2019
    Assignee: AGC Inc.
    Inventors: Yasuaki Watanabe, Koji Nakamura, Tsubasa Kondo, Yasunori Ito, Yuki Hori, Hiroshi Utsugi
  • Patent number: 10236300
    Abstract: A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex sidewall portions.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: March 19, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Masanori Tsutsumi, Shinsuke Yada, Sayako Nagamine, Johann Alsmeier
  • Patent number: 10204914
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first buried gate and a second buried gate in the substrate on the memory region; forming a first silicon layer on the substrate on the periphery region; forming a stacked layer on the first silicon layer; forming an epitaxial layer on the substrate between the first buried gate and the second buried gate; and forming a second silicon layer on the epitaxial layer on the memory region and the stacked layer on the periphery region.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: February 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Cheng Tsai, Feng-Ming Huang, Ying-Chiao Wang, Chien-Ting Ho, Li-Wei Feng, Tsung-Ying Tsai
  • Patent number: 10204915
    Abstract: A method of forming a dynamic random access memory (DRAM) includes the following steps. A substrate includes a memory area and a logic area. A stacked structure is formed on the substrate of the memory area and a gate structure is formed on the substrate of the logic area. A first mask layer is formed on the stacked structure and the gate structure. A densification process is performed to densify the first mask layer. A second mask layer is formed on the first mask layer. A part of the second mask layer and a part of the first mask layer are removed to form a first spacer on sidewalls of the gate structure.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: February 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Shan Su, Chia-Wei Wu
  • Patent number: 10177040
    Abstract: Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly doped source and dram regions. This technique of reusing a photoresist mask can be employed for creating lightly doped source and drain regions of one conductivity followed by using the technique a second time to create lightly doped source and drain regions of the complementary conductivity type. This may prevent use of at least one hard mask during manufacturing.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: January 8, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Unsoon Kim
  • Patent number: 10141194
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first polysilicon layer is formed on a substrate. A planarization process to the first polysilicon layer is performed. A first etching back process to the first polysilicon layer is performed after the planarization process. A second etching back process to the first polysilicon layer is performed after the first etching back process. A first wet clean process to the first polysilicon layer is performed after the first etching back process and before the second etching back process.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELETRONICS CORP.
    Inventors: Zhi Qiang Mu, Chow Yee Lim, Hui Yang, Yong Bin Fan, Jianjun Yang, Chih-Chien Chang
  • Patent number: 9966477
    Abstract: Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: May 8, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Shenqing Fang, Unsoon Kim, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. Haddad
  • Patent number: 9922833
    Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: March 20, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mark Ramsbey, Chun Chen, Sameer Haddad, Kuo Tung Chang, Unsoon Kim, Shenqing Fang, Yu Sun, Calvin Gabriel
  • Patent number: 9685451
    Abstract: A nonvolatile memory device includes cell strings, each including a plurality of memory cells over a substrate, extending in a direction, channel layers, connected with one sides and the other sides of the cell strings, extending in another direction perpendicular to the substrate, select gate electrodes, located over the cell strings, surrounding side surfaces of the channel layers with a gate dielectric layer interposed therebetween, and conductive lines connected with upper ends of the channel layers.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: June 20, 2017
    Assignee: SK Hynix Inc.
    Inventor: Nam-Jae Lee
  • Patent number: 9570610
    Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 14, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koichi Toba, Hiraku Chakihara, Yoshiyuki Kawashima, Kentaro Saito, Takashi Hashimoto
  • Patent number: 9564451
    Abstract: A semiconductor device may include a substrate, conductive patterns stacked to be spaced apart from each other on the substrate, contact plugs coming in contact with the respective conductive patterns, and first and second slit insulating layers of a first group penetrating the conductive patterns. The substrate may include a cell area and a contact area extending along a first direction from the cell area. The conductive patterns may be form a step structure. The first slit insulating layers of the first group may be opposite to each other in a second direction with any one of the contact plugs, interposed therebetween. The second slit insulating layers of the first group, which extend along the first direction in the contact area, may be opposite to each other in the second direction with the first slit insulating layers of the first group and the contact plugs, interposed therebetween.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: February 7, 2017
    Assignee: SK HYNIX INC.
    Inventors: Hack Seob Shin, Sang Hyuk Nam, Byung Soo Park, Jong Ho Jung
  • Patent number: 9431417
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers and a plurality of connecting portions. The stacks are disposed on the substrate. Each of the stacks comprises alternately-stacked conductive layers and insulating layers. The memory layers are disposed on sidewalls of the stacks, respectively. The channel layers are disposed on the memory layers, respectively, wherein each of the channel layers comprises a surface being exposed. The connecting portions connect the surface of each of the channel layers to the substrate, respectively.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: August 30, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Yen-Hao Shih
  • Patent number: 9431503
    Abstract: An integrated circuit comprises a first poly-silicon region including a first poly-silicon layer, a second poly-silicon layer disposed over the first poly-silicon layer, a first poly-silicon finger associated with the first poly-silicon layer, and a second poly-silicon finger associated with the second poly-silicon layer. The first poly-silicon finger and the second poly-silicon finger are oriented in a substantially orthogonal manner relative to each other. The integrated circuit comprises a second poly-silicon gate region including the first poly-silicon layer. The first polysilicon gate region and the second polysilicon gate region each have different poly-silicon gate structures.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: August 30, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Chuan Lin, Hidehiko Shiraiwa, Bradley Marc Davis, Lei Xue, Simon S. Chan, Kenichi Ohtsuka, Angela T. Hui, Scott Allan Bell
  • Patent number: 9401362
    Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, a second field effect transistor formed in the substrate structure, and a third field effect transistor formed in the substrate structure. The first field effect transistor can include a first gate stack configuration, and a first threshold voltage. The second field effect transistor can include a second gate stack configuration, and a second threshold voltage. The third field effect transistor can include a third gate stack configuration, and a third threshold voltage.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: July 26, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Hui Zang
  • Patent number: 9396952
    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: July 19, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Jeff Hu
  • Patent number: 9355860
    Abstract: A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: May 31, 2016
    Assignee: Synopsys, Inc.
    Inventor: Tsu-Jae King Liu
  • Patent number: 9219132
    Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: December 22, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
  • Patent number: 9209275
    Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes removing a central plug from between a first memory cell and a second memory cell to define a center gap. Each of the first and second memory cells include a control gate with a control gate height, a cap overlying the control gate, a select gate adjacent to the control gate, and a select gate dielectric between the control gate and the select gate. The select gate is recessed to a select gate height while the cap overlies the control gate, where the select gate height is less than the control gate height. A memory spacer is formed overlying the select gate dielectric and adjacent to the control gate.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zheng Zou, Alex See
  • Patent number: 9129996
    Abstract: A method of making a semiconductor device includes depositing a layer of polysilicon in a non-volatile memory (NVM) region and a logic region of a substrate. The layer of polysilicon is patterned into a gate in the NVM region while the layer of polysilicon remains in the logic region. A memory cell is formed including the gate in the NVM region while the layer of polysilicon remains in the logic region. The layer of polysilicon in the logic region is removed and the substrate is implanted to form a well region in the logic region after the memory cell is formed. A layer of gate material is deposited in the logic region. The layer of gate material is patterned into a logic gate in the logic region.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: September 8, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Frank K. Baker, Jr., Cheong Min Hong
  • Patent number: 9111865
    Abstract: An oxide-containing layer is formed directly on a semiconductor layer in an NVM region, and a first partial layer of a first material is formed over the oxide-containing layer in the NVM region. A first high-k dielectric layer is formed directly on the semiconductor layer in a logic region. A first conductive layer is formed over the first dielectric layer in the logic region. A second partial layer of the first material is formed directly on the first partial layer in the NVM region and over the first conductive layer in the logic region. A logic device is formed in the logic region. An NVM cell is formed in the NVM region, wherein the first and second partial layer together are used to form one of a charge storage layer if the cell is a floating gate cell or a select gate if the cell is a split gate cell.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: August 18, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mehul D. Shroff, Mark D. Hall, Frank K. Baker, Jr.
  • Patent number: 9087913
    Abstract: A thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and control gate defining a select gate location laterally adjacent the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 21, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff, Frank K. Baker, Jr.
  • Publication number: 20150144695
    Abstract: An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus is provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.
    Type: Application
    Filed: April 7, 2014
    Publication date: May 28, 2015
    Applicant: The United States of America as represented by the Secretary of the Navy
    Inventors: Matthew Gadlage, Matthew Kay, James D. Ingalls, Adam Duncan, Austin Roach
  • Publication number: 20150123189
    Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatma Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan
  • Publication number: 20150123188
    Abstract: Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Zhenyu Lu, Roger W. Lindsay, Andrew Bicksler, Yongjun J. Hu, Haitao Liu
  • Publication number: 20150117110
    Abstract: Technologies are generally related to a connecting storage gate memory device, system, and method of manufacture.
    Type: Application
    Filed: October 30, 2014
    Publication date: April 30, 2015
    Inventor: Zhijiong Luo
  • Publication number: 20150104915
    Abstract: A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.
    Type: Application
    Filed: December 17, 2014
    Publication date: April 16, 2015
    Inventors: Shyue Seng TAN, Eng Huat TOH, Elgin QUEK, Yanzhe TANG
  • Patent number: 8999785
    Abstract: Flash-to-ROM conversion is performed by converting single transistor flash memory cells to single transistor ROM cells. An S-Flash memory cell is converted to a programmed ROM cell by introducing a threshold voltage implant into the channel region of the S-Flash memory cell. Alternately, an S-Flash memory cell is converted to a programmed ROM cell by introducing a threshold voltage implant into a substrate region in alignment with an edge of the gate electrode of the S-Flash memory cell. The width of the mask through which this threshold voltage implant is performed can be varied, such that the threshold voltage implant region can have different dopant concentrations, thereby allowing multiple bits to be represented by the programmed ROM cell. In another embodiment, a Y-flash memory cell is converted to a programmed ROM cell by adjusting the length of a floating gate extension region of the Y-Flash memory cell.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: April 7, 2015
    Assignee: Tower Semiconductor Ltd.
    Inventors: Itzhak Edrei, Yakov Roizin
  • Patent number: 8993398
    Abstract: Methods and apparatuses directed to high density holes and metallization are described herein. A method may include providing a dielectric layer including a plurality of holes, forming a fill material over a top surface of the dielectric layer and in the plurality of holes, and reflowing the fill material to substantially remove any voids in the plurality of holes. Other embodiments are also described.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: March 31, 2015
    Assignee: Marvell International Ltd.
    Inventors: Pantas Sutardja, Runzi Chang
  • Patent number: 8980710
    Abstract: An impurity layer is formed in a first region of a semiconductor substrate, a silicon layer is grown on the semiconductor substrate, a tunnel gate insulating film is formed on a first silicon layer of a second region, a first conductor layer is formed on the tunnel gate insulating film, a first silicon oxide film and a silicon nitride film are formed on a second silicon layer, in a reduced pressure state, oxygen and hydrogen are independently introduced into an oxidation furnace to expose the silicon nitride film to active species of the oxygen and active species of the hydrogen to thereby oxidize the silicon nitride film to form a second silicon oxide film, a gate insulating film is formed on the silicon layer of the first region, a second conductor layer is formed on the second silicon oxide film and on the gate insulating film, the second conductor layer and the first conductor layer of the second region are patterned to form a stack gate of a nonvolatile memory transistor, and the second conductor layer a
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: March 17, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Mitsuaki Hori, Kazushi Fujita, Makoto Yasuda, Katsuaki Ookoshi
  • Patent number: 8969153
    Abstract: A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: March 3, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Donovan Lee, Vinod Purayath, James Kai, George Matamis
  • Publication number: 20150054050
    Abstract: A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 26, 2015
    Inventors: ASANGA H. PERERA, Cheong Min Hong, Sung-Taeg Kang, Janes A. Yater
  • Patent number: 8963224
    Abstract: Provided is a semiconductor device including, on the same semiconductor substrate, a transistor element, a capacitor, and a resistor. The capacitor is formed on an active region, and the resistor is formed on an element isolation region, both formed of the same polysilicon film. By CMP or etch-back, the surface is ground down while planarizing the surface until a resistor has a desired thickness. Owing to a difference in height between the active region and the element isolation region, a thin resistor and a thick upper electrode of the capacitor are formed to prevent passing through of a contact.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: February 24, 2015
    Assignee: Seiko Instruments Inc.
    Inventors: Ayako Inoue, Kazuhiro Tsumura
  • Patent number: 8957469
    Abstract: A semiconductor storage device according to an embodiment comprises a memory cell string in which a plurality of memory cells each having a gate are serially connected to each other. A selective transistor is connected to an end memory cell at an end of the memory cell string. A sidewall film covers a side surface of a gate of the end memory cell and a side surface of a gate of the selective transistor between the end memory cell and the selective transistor. An air gap is provided between the sidewall film of the end memory cell and the sidewall film of the selective transistor.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryosuke Isomura, Wataru Sakamoto, Hiroyuki Nitta
  • Patent number: 8951863
    Abstract: A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 10, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Frank K. Baker, Jr., Mehul D. Shroff
  • Patent number: 8952446
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a channel body, a memory film, first and second insulating separation films, a first and a second inter-layer insulating films, a selection gate, a conductive layer, and resistance elements. The substrate includes a memory cell array region and a peripheral region. The stacked body includes electrode films and insulating films. The channel body extends in a stacking direction. The memory film includes a charge storage film. The first insulating separation films divide the stacked body. The first and the second inter-layer insulating films are on the stacked body and on the conductive layer, respectively. The selection gate is on the first inter-layer insulating film. The conductive layer is on the peripheral region. The resistance elements are on the second inter-layer insulating film. The second insulating separation films divide the conductive layer.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyasu Tanaka
  • Patent number: 8951832
    Abstract: Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8951861
    Abstract: Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: February 10, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Scott Brad Herner, Maitreyee Mahajani
  • Patent number: 8951862
    Abstract: The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: February 10, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Hang-Ting Lue, Yen-Hao Shih
  • Publication number: 20150037950
    Abstract: A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Inventors: Johann Alsmeier, Raghuveer S. Makala, Xiying Costa, Yanli Zhang
  • Patent number: 8946022
    Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 3, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Robert Purayath, James K Kai, Masaaki Higashitani, Takashi Orimoto, George Matamis, Henry Chien
  • Patent number: 8946003
    Abstract: A semiconductor transistor is formed as follows. A gate electrode is formed over but is insulated from a semiconductor body region. A first layer of insulating material is formed over the gate electrode and the semiconductor body region. A second layer of insulating material different from the first layer of insulating material is formed over the first layer of insulating material. Only the second layer of insulating material is etched to form spacers along the side-walls of the gate electrode. Impurities are implanted through the first layer of insulating material to form a source region and a drain region in the body region. A substantial portion of those portions of the first layer of insulting material extending over the source and drain regions is removed.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: February 3, 2015
    Assignee: SK hynix Inc.
    Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
  • Patent number: 8940604
    Abstract: The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 27, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • Publication number: 20150021609
    Abstract: Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.
    Type: Application
    Filed: October 10, 2014
    Publication date: January 22, 2015
    Inventor: Toru Tanzawa
  • Patent number: 8932948
    Abstract: A NAND flash memory chip is formed by depositing two N-type polysilicon layers. The upper N-type polysilicon layer is then replaced with P-type polysilicon and barrier layer in the array area only, while maintaining the upper N-type polysilicon layer in the periphery. In this way, floating gates are substantially P-type while gates of peripheral transistors are N-type.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: January 13, 2015
    Assignee: SanDisk Technologies, Inc.
    Inventors: Jongsun Sel, Tuan Pham, Ming Tian
  • Patent number: 8921136
    Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
  • Publication number: 20140377921
    Abstract: An impurity layer is formed in a first region of a semiconductor substrate, a silicon layer is grown on the semiconductor substrate, a tunnel gate insulating film is formed on a first silicon layer of a second region, a first conductor layer is formed on the tunnel gate insulating film, a first silicon oxide film and a silicon nitride film are formed on a second silicon layer, in a reduced pressure state, oxygen and hydrogen are independently introduced into an oxidation furnace to expose the silicon nitride film to active species of the oxygen and active species of the hydrogen to thereby oxidize the silicon nitride film to form a second silicon oxide film, a gate insulating film is formed on the silicon layer of the first region, a second conductor layer is formed on the second silicon oxide film and on the gate insulating film, the second conductor layer and the first conductor layer of the second region are patterned to form a stack gate of a nonvolatile memory transistor, and the second conductor layer a
    Type: Application
    Filed: May 30, 2014
    Publication date: December 25, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Mitsuaki Hori, Kazushi Fujita, Makoto Yasuda, Katsuaki Ookoshi
  • Patent number: 8916470
    Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: December 23, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Durga Panda, Jaydip Guha, Robert Kerr
  • Patent number: 8906770
    Abstract: Gate cross diffusion in a semiconductor structure is substantially reduced or eliminated by forming multiple n-type gate regions with different dopant concentrations and multiple p-type gate regions with different dopant concentrations so that the n-type gate region with the lowest dopant concentration touches the p-type gate region with the lowest dopant concentration.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: December 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Manoj Mehrotra
  • Patent number: 8906764
    Abstract: A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over an NVM work function setting metal, the NVM work function setting metal is on a high-k dielectric, and a metal logic gate of a logic transistor is similarly formed over work function setting and high-k dielectric materials. The logic transistor is formed while portions of the metal select gate of the NVM cell are formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: December 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mehul D. Shroff, Mark D. Hall
  • Patent number: 8900945
    Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: December 2, 2014
    Assignee: Micron Technology, Inc.
    Inventors: John Moore, Joseph F. Brooks