Abstract: A process for manufacturing a semiconductor device including a plurality of transistors in each of a memory cell portion and a peripheral circuit portion formed on the same semiconductor substrate, comprising: (a) forming a gate of transistors in a peripheral circuit portion; (b) forming first sidewall spacers on sides of the gates; (c) forming a gate of transistors in a memory cell portion; (d) forming second sidewall spacers on sides of the gates in the peripheral circuit portion and the memory cell portion, so that single sidewall spacers are formed on the transistors in the memory cell portion and dual sidewall spacers are formed on the transistors in the peripheral circuit portion; and (e) forming source/drain regions in the peripheral circuit portion and the memory cell portion to obtain a plurality of transistors.

Abstract: A method to form an embedded FLASH integrated circuit with reduced processing steps is described. In the method a partial etch is performed on the control gate region of a polycrystalline silicon film (21). A multiple etch process is then used to simultaneously form the FLASH memory cell gate stack (54), the NMOS gate structure (94) and the PMOS gate structure (96).

Abstract: Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a plagiarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines e.g., memory cell bit lines and comprising gate regions made up of a first conducting layer, an intermediate dielectric layer and a second conducting layer with said regions being insulated from each other by insulation regions to form said architecture with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer of the second conducting layer and of the intermediate dielectric layer respectively, and a following isotropic etching of the first conducting layer.

Abstract: An improved method of making semiconductor memory structures that include a memory matrix having non-volatile memory cells, each with a floating gate transistor and a selection transistor, each transistor provided with a gate electrode. Associated with the memory matrix is control circuitry, which also have control gates. The method includes forming the gate electrodes on top of the semiconductor substrate and then depositing a dielectric layer over the whole memory structure. A screening layer is deposited over the whole surface of the memory structure, and then part of it is removed, exposing a portion of the control circuitry. A portion of the dielectric layer is etched away in the non-covered portion of the control circuitry to form spacer regions, and the non-covered portion of the control circuitry is then implanted with a dopant.

Abstract: A process for fabricating a memory cell, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a masking layer overlying the ONO layer, patterning the masking layer into a resist mask, implanting the semiconductor substrate with a p-type dopant to create a p-type region, and laterally diffusing the p-type region. In one preferred embodiment, the lateral diffusing of the p-type region includes exposing the semiconductor substrate to a thermal cycle. Preferably, the thermal cycle is a rapid thermal anneal or a furnace anneal.

Abstract: There is disclosed a method of manufacturing a floating gate in a flash memory device. In order to minimize the distance between floating gates, the method includes patterning a polysilicon film using a first PSG pattern in which a second PSG spacer is formed on and at the sidewall of the polysilicon film, and removing the first PSG film pattern and the second PSG film spacer using 50:1 HF or 9:1 BOE. Therefore, it can minimize the size of the device without damaging a polysilicon film and a field oxide.

Abstract: A process for producing a memory structure is disclosed. According to the process, an insulating portion and a conductive portion are formed with substantially equal thickness, and arranged in an alternate way to be a field oxide structure and a floating gate structure. This can be achieved by applying a conductive layer first, creating a trench in the conductive layer, filling the trench with an insulating material, and polishing the resulting layer. Because the insulating portion is formed adjacent to the conductive portion by filling the insulating material in the trench adjacent to the conductive portion, the field oxide structure and the floating gate structure are self-aligned while forming. Accordingly, no misalignment occurs, and thus the integration of the device can be improved.

Abstract: An improved split gate flash memory cell is disclosed whose floating gate is formed to have a reentrant angle such that its width increases with increased distance from the substrate so as to minimize the possibility of defects in the poly oxide layer overlaying the floating gate.

Abstract: A process for manufacturing electronic semiconductor integrated memory devices having a virtual ground and comprising at least a matrix of floating gate memory cells is presented. In the memory device, the matrix is formed on a semiconductor substrate with a number of continuous bit lines extending across the substrate as discrete parallel strips. The process begins by growing an oxide layer over the matrix region and depositing over the semiconductor throughout a stack structure which comprises a first conductor layer, a first dielectric layer, and a second conductor layer. Then a second dielectric layer is deposited over the stack structure, and floating gate regions are defined by photolithography using a mask of “POLY1 along a first direction”, to thereby define in the dielectric layer, a plurality of parallel strips which delimit a first dimension of floating gate regions.

Abstract: A halo implant (42, 44) for an MOS transistor (10) is formed in a semiconductor substrate (12) at a shallow implant angle, relative to normal to the substrate surface (29). A polysilicon gate structure (32, 33) is formed over a gate oxide (28) and then a hard mask (70), such as a TEOS-generated layer of silicon oxide, is deposited on an upper surface (68) of the gate. The mask is etched with a blanket anisotropic etch to form a cap-shaped mask (72). The shape of the cap causes the dopant for the halo implant to penetrate to a depth which follows the contour of the cap. Thus, halo implants may be formed which extend under the gate structure without the need for large angle implants and resultant shadowing problems caused by adjacent devices.

Abstract: A method of forming a non-volatile memory cell having a floating gate with sharp corners is disclosed. First, a first dielectric layer and a first silicon layer are formed on a semiconductor substrate. An etching stop layer is next formed on the first silicon layer. After patterning the etching stop layer to form an opening, a dish-shaped hole is formed by performing an isotropic etching process to partially etch the first silicon layer through the opening. After removing the etching stop layer, a second dielectric layer is formed to refill the dish-shaped hole. After that, a dielectric stud is formed by performing a planarization process to remove a portion of the second dielectric layer outside the dish-shaped hole. Thereafter, a floating gate with sharp corners is formed by performing an anisotropical etching process to etch an exposed portion of the first silicon layer using the dielectric stud as an etching mask. Finally, the dielectric stud is removed.

Abstract: A method for making a flash memory having a passivation layer that is not transparent to ultraviolet light. The method comprises forming a semiconductor substrate that includes a flash memory cell having a floating gate, then forming a conductive layer on the substrate. Process induced charge that has accumulated on the flash cell floating gate is then neutralized and a passivation layer, which is not transparent to ultraviolet light, is formed on the conductive layer.

Abstract: A manufacturing process including: forming a first insulating region on top of an active area; forming a tunnel region at the side of the first insulating region; depositing and defining a semiconductor material layer using a floating gate mask to form a floating gate region. The floating gate mask has an opening with an internal delimiting side extending at a preset distant from a corresponding outer delimiting side of the mask, so that the floating gate region forms inner a hole, and the tunnel region is defined, as regards its length, by the floating gate ask alone. The hole is filled with a dielectric material layer. The surface of the floating gate region is planarized, and an insulating region of dielectric material is made. A control gate region and conductive regions in the active area are then formed.

Abstract: A fieldless array of floating gate transistors is fabricated by forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate. A mask is formed over the ONO layer, the mask having openings that define a plurality of bit line regions of the floating gate transistors in the substrate. A first impurity is implanted into the bit line regions of the substrate, wherein the first impurity is implanted through the ONO layer, through the openings of the mask. The first impurity is implanted at various angles, such that the first impurity is implanted in the substrate at locations beneath the mask. The upper oxide and nitride layers of the ONO layer are subsequently etched through the mask openings. A second impurity is implanted in the substrate through the openings of the mask. The mask is removed, and the substrate is oxidized, thereby forming bit line oxide regions over the bit line regions, and floating gate structures.

Abstract: A fully recessed device structure and method for low power applications comprises a trenched floating gate and a trenched control gate formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography for low power applications. The trenched floating gate is electrically isolated from the trenched control gate by an inter-gate dielectric layer formed inside the trench and on a top surface of the trenched floating gate. The trenched control gate is formed on a top surface of the inter-gate dielectric layer and preferably, has a top surface which is substantially planar with a top surface of the semiconductor substrate. The fully recessed structure further comprises a buried source region, a buried drain region and a channel region. The buried source region and the buried drain region are formed in the well junction region and are laterally separated by the trench.

Abstract: The invention relates to a flash EEPROM cell and method of manufacturing the same.

Abstract: A method of forming an improved interpoly oxide-nitride-oxide (ONO) stricture in stacked gate memory cells is provided. The top oxide layer of an interpoly ONO stack is formed using Low Pressure Chemical Vapor Deposition (LPCVD) of tetraethylorthosilicate (TEOS). As a result of the relatively low processing temperatures necessary for this step, degradation of the tunnel oxide and memory cell performance associated with high thermal-budget oxide growth processes is greatly reduced. Steam densification of the TEOS layer produces a robust top oxide for the ONO dielectric, and thus, greatly reduces erosion of the top layer TEOS during subsequent processing steps (i.e., in the context of a memory array embedded in CMOS core technology).

Abstract: A method of fabricating a flash memory device including an array of split gate cells, comprising the steps of: providing a silicon substrate having a top surface; implanting ions into a predefined area of the substrate to form a common source region of the substrate; forming at least one floating gate over the substrate, each floating gate being associated with one of the cells and having a portion which overlies a portion of the common source region, the overlying portion of each floating gate providing for a high coupling ratio for the associated flash cell; forming a select gate over at least a portion of each floating gate; and forming a drain region associated with each cell. The high coupling ratio flash cell device of the present invention overcomes limitations associated with conventionally formed split gate flash cells by forming the common source region first and then forming the floating gates over the common source region in order to provide a high coupling ratio for the cells.

Abstract: The present invention discloses the new structure with regard to a nonvolatile semiconductor memory which can store therein an information corresponding to a plurality of bits. The nonvolatile semiconductor memory according to the present invention has a charge trapping layer 4 for accumulating electrons, in an end of a gate electrode. In the nonvolatile semiconductor memory according to the present invention, the electrons are stored in this charge trapping layer 4 to thereby store the information corresponding to the plurality of bits.

Abstract: A second polysilicon layer (218) and an ONO insulator film (216) are etched using mask insulator films (220a and 220b) as masks to form a control gate (218a), a second gate electrode (218b) and intergate insulator films (216a and 216b). Then, a resist mask (224) for a first gate electrode (214b) is formed in a peripheral transistor forming region or a selecting transistor forming region. Subsequently, a first polysilicon layer (214) is etched using the resist mask and the mask insulating films (220a and 220b) as masks to form a floating gate (214a) and a first gate electrode (214b). Thus, the mask insulator film (220b) has no difference in level, so that the surface of an interlayer insulator film (228) can be flattened.

Abstract: A memory cell array is provided at a non-volatile semiconductor storage apparatus. In a memory cell array, the unit cell includes a memory cell field effect transistor and a select field effect transistor. The memory cell field effect transistor has a floating gate and a control gate. The select field effect transistor has a drain connected to a source of the memory cell field effect transistor. The floating gate and control gate extends to a position above a gate of the select field effect transistor.

Abstract: A method of fabricating a flash memory provides a substrate having a tunnel oxide layer, a first conductive layer and a first material layer thereon. A conductive spacer is formed on the sidewalls of the first conductive layer and the first material layer. A second material layer is formed on the substrate. A portion of the second material layer is removed, until a part of the conductive spacer has been exposed. The remaining portion of the second and first material layers are removed, to expose the first conductive layer and the conductive spacer. The first conductive layer and the conductive spacer, together then form a floating gate. A dielectric film layer is then formed on the substrate, and a second conductive layer is subsequently formed above the dielectric film layer.

Abstract: The present invention relates to a nonvolatile semiconductor memory device; which contains, in a memory cell, a memory transistor having a floating gate that is set over a tunnel insulating film on a semiconductor substrate, and a control gate that is set over an interlayer insulating film on this floating gate; and a select transistor having a select gate that is set over a gate insulating film on the semiconductor substrate; wherein the thickness of the gate insulating film in the above-mentioned select transistor is less than the thickness of the tunnel insulating film in the above-mentioned memory transistor. The present invention can provide a nonvolatile semiconductor memory device capable to operate at a high speed with a good stability.

Abstract: The present invention discloses a single poly non-volatile memory structure includeing a semiconductor substrate with two active areas divided by isolation regions. A control gate doped with N-type impurities is embedded in the first active area, and a first floating gate is formed thereon. A second floating gate is formed on the substrate of the second active area, and two doped regions are implanted at opposite sides of the second active areas in the substrate. A floating gate line is employed to connect the first and second floating gate for making sure that the two floating gates are in the same potential. When the control gate is biased to a voltage level, the voltage level would be coupled to the first floating gate so as to keep the second floating gate in the same potential with the first floating gate.

Abstract: In a semiconductor device, a plurality of transistor elements, each of which is formed by a channel region, a source region, and a drain region, are provided on a substrate, this semiconductor device further having a first element separation region that is made of insulating material and formed by a foot that protrudes form the substrate surface between the transistor elements of a pair of neighboring transistors (6) and (6′) or (6′) and (6″) toward the inside of the substrate and a wing that is connected to the foot (7), and that extends so as to cover the top of either the drain region or the source regions of each of the neighboring transistor elements (6) and (6′).

Abstract: A non-volatile memory device that can prevent a functional failure in the programming process of a cell from occurring in an overwriting process, by stopping a current path from being formed through the sources of a previously programmed cell and that of a currently selected cell which is to be programmed. The present device includes a modified structure for a memory cell of an EEPROM device. The present device includes an additional overwrite transistor to separate a sense transistor from a source in the region of an active area which is expanded toward the source of the sense transistor. The overwriting transistor includes a gate formed in a single layered structure of a second conductivity layer, integrally connected with the second conductivity layer of the sense transistor. Further, a second gate insulating layer is formed between the source and the sense transistor on the substrate.

Abstract: A new capacitor structure for Flash memory (Flash) cells on a supporting substrate's existing topography, including existing topography provided by adjacent word lines is provided. The gate of the Flash memory cell is constructed as an integral part of the new capacitor cell structure. An increased capacitive coupling ratio is achieved whereby reduced programming voltage is required while yielding more a more compact memory cell structure. Hence, the requirements of low power densely packed integrated circuits is realized for smaller, portable microprocessor devices. Methods for forming the above stated novel capacitor for Flash memory (Flash) cells on a supporting substrate's existing topography is similarly included.

Abstract: A method (200) of forming a NAND type flash memory device includes the steps of forming an oxide layer (202) over a substrate (102) and forming a first conductive layer (106) over the oxide layer. The first conductive layer (106) is etched to form a gate structure (107) in a select gate transistor region (105) and a floating gate structure (106a, 106b) in a memory cell region (111). A first insulating layer (110) is then formed over the memory cell region (111) and a second conductive layer (112, 118) is formed over the first insulating layer (110). A word line (122) is patterned in the memory cell region (111) to form a control gate region and source and drain regions (130, 132) are formed in the in the substrate (102) in a region adjacent the word line (122) and in a region adjacent the gate structure (107).

Abstract: A method is used to fabricate an electrically erasable programmable read only memory. First, a substrate is provided. Then, a doped polysilicon pillar is formed on the substrate. Furthermore, a source is formed in the substrate beneath the doped polysilicon pillar. Finally, the other structures of the memory are completed in sequence.

Abstract: A nonvolatile memory device and a manufacturing method therefor are provided. The nonvolatile memory device includes source pad lines connecting source regions of neighboring cells, parallel to word lines. Thus, the number of common source lines necessary for the overall cell array area can be reduced. Also, the distance between a word line and a contact hole is minimized by providing self-aligned bit line contact holes, thereby minimizing the size of a cell array area.

Abstract: The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate which is capacitively coupled to the floating gate via a second insulating film. The first insulating film includes a first gate insulating film portion formed in the first surface region, and, a second gate insulating film portion formed in the step side region and the second surface region.

Abstract: A method of fabricating a gate is described. A first dielectric layer having a first opening is formed on a substrate. A gate dielectric layer is formed in the opening. A lower portion of a floating gate is formed on the gate dielectric layer. A source/drain region is formed in the substrate beside the lower portion of the floating gate. A conductive layer is formed on the first dielectric layer to completely fill the first opening. The conductive layer is patterned to form a second opening in the conductive layer. The second opening is above the first opening and does not expose the first dielectric layer. The second opening has a tapered sidewall and a predetermined depth. A mask layer is formed to cover the conductive layer and fill the second opening. The mask layer outside the second opening is removed to expose the conductive layer. A portion of the mask layer is removed to leave a first etching mask layer in the second opening.

Abstract: A semiconductor device comprises a first MOSFET and a second MOSFET. The first MOSFET includes a first gate insulating film formed on a semiconductor substrate and having a relatively large thickness and a first gate electrode composed of a polysilicon film formed on the first gate insulating film. The second MOSFET includes a second gate insulating film formed on the semiconductor substrate and having a relatively small thickness and a second gate electrode composed of a metal film made of a refractory metal or a compound of a refractory metal and formed on the second gate insulating film.

Abstract: A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming a mask layer overlying the semiconductor substrate. Thereafter, an etch process is performed to form a trench in the semiconductor substrate. Next, the mask layer is removed and the trench in the semiconductor substrate is filled with a silicon oxide layer. To form a bit-line oxide layer, a planarization process is utilized to planarize the silicon oxide layer and form a planar surface continuous with an upper surface of the semiconductor substrate.

Abstract: A method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is formed over the top surface of the floating gate. An interpoly oxide layer is formed over the semiconductor structure, the poly-oxide portion and the poly-oxide portion. The interpoly oxide layer having an initial thickness and includes: a word line region portion over at least a portion of the semiconductor structure adjacent the floating gate portion; side wall area portions over the floating gate portion side walls; and a top portion over the poly-oxide portion. The initial thickness of the top portion of the interpoly oxide layer is reduced to a second thickness without reducing the initial thickness of the interpoly oxide word line region portion or an appreciable portion of the interpoly oxide side wall area portion.

Abstract: A non-volatile semiconductor memory device is provided with a circuit that protects a tunnel oxide film from the charging phenomenon. This circuit comprises a first junction diode including an N+-type diffusion layer and a P-type well, and a second junction diode including a P-type well and an N-type well. When a voltage applied to the control gate is greater than all of a write voltage, a read voltage, and an erasure voltage that would be applied to the control gate, a current is guided through that circuit.

Abstract: In one embodiment, the present invention relates to a method of forming a NAND type flash memory device involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; annealing the first oxide layer and the second oxide layer under an inert gas and at least one of N2O and NO for a period of time from about 1 minute to about 15 minutes; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous

Abstract: A method for fabricating a metal oxide semiconductor having a double-diffused drain, which is applicable to the fabrication of an electrostatic discharge protection present fabrication method for a metal oxide semiconductor does not require additional masks. Only an additional ion implantation step is sufficient to form a double diffused drain metal-oxide-semiconductor for an electrostatic discharge protection circuit, in which the electrostatic discharge protective capability of the electrostatic discharge protection circuit is enhanced.

Abstract: A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floating gate and control gate, respectively, of the split-gate flash memory cell. Furthermore, the thin interpoly oxide of the cell, rather than the thick poly-oxide over the floating gate is used as the insulator between the plates of the capacitor. The resulting capacitor yields high storage capacity through high capacitance per unit area.

Abstract: A method of forming source and drain regions for LV transistors that includes the steps of forming sacrificial spacers laterally to LV gate regions; forming LV source and drain regions in a self-aligned manner with the sacrificial spacers; removing the sacrificial spacers; forming HV gate regions of HV transistors; forming gate regions of selection transistors; forming control gate regions of memory transistors; simultaneously forming LDD regions self-aligned with the LV gate regions, HV source and drain regions self-aligned with the HV gate regions, source and drain regions self-aligned with the selection gate region and floating gate region; depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask; anisotropically etching the dielectric layer, to form permanent spacers laterally to the LV gate regions; removing the protection silicide mask; and forming silicide regions on the LV source and drain regions and on the LV gate regions.

Abstract: A fabrication method for a high voltage electrically erasable read only memory is described, wherein a substrate comprising a memory device region and a peripheral high voltage circuit region is provided. A floating gate is formed on the substrate in the device region, while a gate electrode is formed on the substrate in the peripheral circuit region. Thereafter, an oxide/nitride/oxide layer is formed on the substrate, wherein the oxide/nitride/oxide layer is formed by stacking from bottom to top a first oxide layer, a nitride layer and a second oxide layer. The second oxide layer in the peripheral high voltage circuit region is then removed, followed by removing the nitride layer in the peripheral high voltage circuit region. An oxidation on the second oxide layer and a double diffused drain implantation are conducted to form a bird's beak structure at the bottom corner of the gate electrode and to form a double diffused drain structure in the substrate on both sides of the gate electrode.

Abstract: Disclosed is a method for manufacturing a semiconductor device. The method comprises the steps of forming a bit line contact plug and a storage electrode contact plug which are connected to a semiconductor substrate; etching a capping nitride film above a word line which is positioned at a peripheral circuit part of the semiconductor substrate; forming a bit line which is connected to the bit line contact plug and the word line; etching a capping nitride film above the bit line of the peripheral circuit part; and forming a metal wiring contact hole which reveals the semiconductor substrate, the word line and the bit line.

Abstract: In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.

Abstract: A split-gate flash memory cell having self-aligned source and floating gate self-aligned to control gate is disclosed as well as a method of forming the same. This is accomplished by depositing over a gate oxide layer on a silicon substrate a poly-1 layer to form a vertical control gate followed by depositing a poly-2 layer to form a spacer floating gate adjacent to the control gate with an intervening intergate oxide layer. The source is self-aligned and the floating gate is also formed to be self-aligned to the control gate, thus making it possible to reduce the cell size. The resulting self-aligned source alleviates punch-through from source to control gate while the self-aligned floating gate with respect to the control gate provides improved programmability. The method also replaces the conventional poly oxidation process thereby yielding improved sharp peak of floating gate for improved erasing and writing of the split-gate flash memory cell.

Abstract: A method of fabricating a flash memory cell includes the steps of forming a field insulating layer on a substrate, forming a first gate oxide layer on the substrate, forming a floating gate, a first insulating layer and a control gate on the first gate oxide layer, forming sidewall insulating layers at both sides of the floating gate and the control gate, forming sidewall conductive layers on the sidewall insulating layers, and forming a source and drain region in the substrate.

Abstract: A method of fabricating a buried vertical split gate memory cell is disclosed. First, a first trench is created in an SOI substrate for accommodating a floating gate. A second trench, having a smaller width than that of the first trench, is then created at the bottom of the first trench for accommodating a word line/control gate. Simultaneously, a silicon sidewall step structure is produced and functions as a vertical channel of the buried vertical split gate memory cell, wherein the vertical control gate channel length (LCG) and the floating gate channel length (LFG) is 0.25 micrometers and about 3.5 nm, respectively.

Abstract: A two-transistor flash EPROM cell for high-speed high-density PLD applications is provided. The two-transistor cell includes a storage transistor connected in series to an access transistor. The storage transistor prevents problems associated with both over-erase and punch-through, and allows for scaling of the gate length to realize 5V cell programming.

Abstract: A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a poly tunnel oxide between the floating gate and the erase gate. The floating gate is defined by the control gate sidewall spacer which is formed before the floating gate poly self-aligned etch step. The polysilicon sidewall spacer erase gate is formed after growing a poly tunnel oxide on the sidewall of the floating gate poly. Since the poly tunnel oxide thickness is minimized, a fast programming with a low power consumption can be achieved. By using poly-to-poly tunneling erase scheme, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further Vcc scaling becomes possible.

Abstract: The method for forming a flash memory cell mainly includes the steps as follows. At first, a semiconductor substrate having isolation regions thereon and having a well region provided between the isolation regions is provided. A tunnel oxide layer is formed on the well region and a first silicon layer is formed over the substrate. A dielectric layer is formed on the first silicon layer and a portion of the first silicon layer and the dielectric layer is removed to define a control gate opening within the first silicon layer on a portion of the well region. Next, the substrate is doped in the region under the control gate opening to adjust a threshold voltage of the flash memory cell. A gate oxide layer is grown from the substrate in the control gate opening and a second silicon layer is formed on the substrate to fill within the control gate opening and to cover the remaining dielectric layer.

Abstract: A semiconductor device in which polysilicon is used to form source and drain regions in an initial process step so as to reduce resistance of bit lines and minimize a junction capacitance and thus improve its reliability, and a method for fabricating the same are disclosed, the semiconductor device including a semiconductor substrate, trenches formed in predetermined areas of the semiconductor substrate, an insualting layer formed in the trenches and beneath a surface of the substrate to have a recess, a polysilicon layer formed on the insualting layer in the trench, source and drain regions formed at both sides of the polysilicon layer beneath a surface of the semiconductor substrate, and gates formed over the semiconductor substrate.