Abstract: A process for a memory transistor (e.g. flash-EEPROM cell), which includes forming an isolation-spacer between a control gate and an erase line of over a floating gate by first growing a thin thermal oxide to be in contact with the first sidewall of control gate and thereafter depositing fluorinated-TEOS or tetramethylsilane (TMS) based LPCVD oxide a low temperature of about 250 degrees centigrade. The choice of deposited have lower dielectric constant than that of thermal silicon dioxide which lowers the parasitic capacitance between word lines and erase lines and thereby increases speed performances. The process prevents the formation of a poly-oxide beak under the control gate, thereby the first insulator between the control gate and the floating gate has a uniform thickness. The transistor programs efficiently, is reliable, has low manufacture cost and is physically and electrically down scalable.

Abstract: One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming a first set of memory cell gates over the charge trapping dielectric in the core region; forming a conformal insulation material layer around the first set of memory cell gates; and forming a second set of memory cell gates in the core region, wherein each memory cell gate of the second set of memory cell gates is adjacent to at least one memory cell gate of the first set of memory cell gates, each memory cell gate of the first set of memory cell gates is adjacent at least one memory cell gate of the second set of memory cell gates, and the conformal insulation material layer is positioned between each adjacent memory cell gate.

Abstract: A silicon oxide film is formed by thermal oxidation on condition that the thickness thereof on the surface of a diffusion layer is about 3 nm. As a result, the silicon oxide film with a thickness of about 12 nm is formed on the surface of a source diffusion layer due to enhanced oxidation. Subsequently, after a silicon nitride film is formed on the entire surface, the silicon nitride film in a peripheral transistor region is removed. Thereafter, the resist film is removed, and thermal oxidation is performed in order to grow the silicon oxide film formed on the surface of the diffusion layer. On this occasion, the silicon oxide film formed on the surface of each of the source diffusion layer and the drain diffusion layer is covered with the silicon nitride film, and hence it does not grow.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.

Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: A high performance 1T RAM cell in a system-on-a-chip is formed using an asymmetric LDD structure that improves pass gate performance and storage node junction leakage. The asymmetric LDD structure is formed using selective ion implantation of the core and I/O LDDs. The node junctions are both pocket implant-free and source/drain implant-free. Further, silicide formation is avoided within the storage node junctions by forming nearly merged sidewall spacers within the node junctions and by forming optional blocking portions over the nearly merged sidewall spacers.

Abstract: The present invention relates to a method of manufacturing a nonvolatile memory cell. The present invention uses tungsten (W) as an upper layer of a control gate electrode in order to integrate the memory cell and performs an ion implantation process for forming a source region and a drain region before a selective oxidization process that is performed to prevent abnormal oxidization of tungsten (W). Therefore, the present invention can reduce a RC delay time of word lines depending on integration of the memory cell and also secure a given distance between a silicon substrate and a tunnel oxide film. As a result, the present invention can solve a data retention problem of the flash memory.

Abstract: A method of fabricating a flash memory cell. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer; forming a barrier layer; removing a portion of the barrier layer to form a first opening; performing an angled implant on the exposed surface of the first conductive layer; forming a floating gate insulating layer; removing the barrier layer; forming a floating gate and a first gate insulating layer; forming a second insulating layer; forming a second conductive layer; removing portions of the second conductive layer and the second insulating layer to form a second opening and a third opening; forming a source region on the substrate; forming spacers on the sidewalls of the second opening and the third opening; and forming drain regions on the substrate within the third opening.

Abstract: The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and self-aligned vias in a first layer disposed over the array to form contacts to each of the source and drain junction in the array. Further, self-aligned local area slotted vias are formed in a second layer that is disposed over the first layer to form local area interconnects that electrically shunt all of the source contacts/junctions. Further, discrete self-aligned drain extensions are formed over each of the formed drain contacts to electrically connect the junctions, and source contacts to the extensions. The formed vias, extensions, and slotted local area vias are simultaneously plugged and filled with a conductive material to form the memory cell array.

Abstract: A double-bit non-volatile memory structure and a method of forming the structure. The main body of the structure is an array of double-bit memory cells partitioned out by mutually crossing isolation lines and bit lines. Each memory cell includes a pair of stacked gate structures, a doped region in between the stacked gate structures and a pair of common source/drain regions for the pair of stacked gate structures. Each control gate within the pair of stacked gate structures connects electrically with a neighboring word line and each source/drain region connects electrically with a bit line. To form the structure, a plurality of isolation lines is formed over a substrate and then a plurality of linear multi-layered structures perpendicular to the isolation lines are formed over the isolation lines. A pair of neighboring linear multi-layered structures forms a grid unit. Thereafter, source/drain regions and bit lines are formed between various grid units.

Abstract: A method of manufacturing a memory device that includes a plurality of cells, each having a first electrode coupled to a first location on semiconductor material, a second electrode coupled to a second location disposed away from the first location on the semiconductor material and a plurality of islands of semiconductor material. The islands are surrounded by an insulator. The islands and the surrounding insulator are formed in pores extending into the semiconductor material between the first and second electrodes. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.

Abstract: A method of forming an electrically erasable non-volatile memory cell array. Each memory cell includes a floating gate, a block of insulation material over the floating gate, and a control gate disposed laterally adjacent to and over the floating gate. The insulation material block is formed with a planarized upper surface (using a dummy poly layer as a planarization etch stop). The control gate is formed with a planarized upper surface (using the insulation material block upper surface as a planarization etch stop).

Abstract: A scalable stacked-gate flash memory device and its high-density memory arrays are disclosed by this invention. There are four different spacer techniques used to fabricate a scalable stacked-gate flash memory device: the first spacer technique is used to form the buffer-oxide spacers for implanting the channel stops of shallow-trench-isolation and oxidizing the etched surface of shallow trenches without sacrificing the active width of non-volatile semiconductor memory devices; the second spacer technique is used to highly adjust the coupling ratio of the self-aligned floating gate using a shallow-trench-isolation (STI) structure so that the applied control-gate voltage for programming and erase can be reduced; the third spacer technique is used to define the gate length of a scalable stacked-gate structure; and the fourth spacer technique is used to form the sidewall spacers for self-aligned source/drain implant, self-aligned source/drain or common buried-source silicidation, and self-aligned contacts.

Abstract: A system and method detecting the presence of polysilicon stringers on a memory array using a polysilicon stringer monitor. The polysilicon stringer monitor includes a continuous type-2 layer of polysilicon forming a first row and a second row across the active region and covering the active region in-between the first and second rows. The polysilicon stringer monitor further includes a continuous type-1 layer of polysilicon extending under the first row, wherein the type-1 layer also covers the active area in-between the first and second rows as well as covers the active area under the second row.

Abstract: A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; forming a protective layer extending on top of the substrate and between the multilayer stacks and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks includes the step of defining the control gate region on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer isolates the multilayer stacks from each other at the sides. Word lines of metal extend above the protective layer and are in electrical contact with the gate regions.

Abstract: A shallow junction EEPROM device and process for fabricating the device includes the formation of a control-gate region and a tunnel region in a semiconductor substrate in which the control-gate region has a substantially higher total doping concentration than the tunnel region. To compensate for rate enhanced oxidation of the silicon surface overlying the control-gate region, nitrogen is selectively introduced into the control-gate region, such that the resulting dielectric layer thickness overlying the control-gate region is substantially the same as that overlying the tunnel region. The relatively high doping concentration of the control-gate region enables fabrication of an EEPROM device having high capacitance coupling, shallow junctions, and a relatively small capacitor area.

Abstract: A process for manufacturing a semiconductor memory device comprises the steps of: (a) forming a tunnel oxide film, a first (1st) conductive film to be a lower floating gate, a 1st insulating film and a second (2nd) insulating film in this order on a semiconductor substrate and patterning the 2nd insulating film, the 1st insulating film, the 1st conductive film and the tunnel oxide film into a desired configuration; (b) forming a third (3rd) insulating film on the entire surface of the resulting substrate; (c) reducing the 3rd insulating film until the 2nd insulating film is exposed; (d) removing the 2nd insulating film; (e) removing the 1st insulating film while further reducing the 3rd insulating film; (f) forming a 2nd conductive film to be an upper floating gate on the 1st conductive film and the 3rd insulating film; (g) flattening the 2nd conductive film until the 3rd insulating film is exposed; and (h) forming an interlayer capacitance film and a 3rd conductive film to be a control gate on the 2nd conduc

Abstract: A nonvolatile memory device with a reduced size floating gate and an increased coupling ratio is disclosed. The nonvolatile memory device includes two isolation structures protruding above a semiconductor substrate. Two dielectric spacers are disposed on a pair of opposing sidewalls of the two isolation structures. The two dielectric spacers are spaced from one another at a distance that defines a gate width which is beyond lithography limit. A tunnel dielectric and a floating gate are provided on substrate and confined between the two dielectric spacers. The floating gate has a smaller bottom surface area relative to its top surface area and has a surface substantially coplanar with a surface of the isolation structures. On the coplanar surface, an inter-gate dielectric and a control gate are provided. Optionally, a lightly doped region is provided beside the floating gate 118 and within the substrate. A manufacturing method for forming such memory device is also disclosed.

Abstract: A method of manufacturing a flash memory cell. The method includes controlling a wall sacrificial oxidization process, a wall oxidization process and a cleaning process of a trench insulating film that are performed before/after a process of forming the trench insulating film for burying a trench to etch the trench insulating film to a desired space. Therefore, it is possible to secure the coupling ratio of a floating gate by maximum and implement a device of a smaller size.

Abstract: The present invention relates to a method of manufacturing a flash memory cell. A tunnel oxide film is formed before a trench is formed and an exposed portion is then etched by a given thickness. Therefore, a phenomenon that the corner of the trench is thinly formed by a sidewall oxidization process is prevented and an active region of a desired critical dimension can be secured.

Abstract: The present invention relates to an array of flash memory cells whose unit cell includes a single transistor of MONOS/SONOS structure (Metal/poly-Silicon Oxide Nitride Oxide Semiconductor) and to data programming and erasing using the same. The array of the flash memory cells includes a plurality of flash memory cells arranged in a form of a matrix. The matrix includes a plurality of word lines arranged in one line direction and connected to gates of the flash memory cells is a row, a plurality of selection lines arranged in a direction perpendicular to the word lines and connected to the sources of the flash memory cells arranged in a column, and a plurality of bit lines arranged in a direction parallel to the selection lines and connected to the drains of the flash memory cells of the same column. To program and erase the cells, different biasing conditions are applied to the word lines, selection lines, bit lines, and the wells of the transistors.

Abstract: Within a stacked gate field effect transistor (FET) device, as well as a method for fabrication thereof and a method for operation thereof, there is provided a stacked gate field effect transistor (FET) device comprising a layered stack of a tunneling dielectric layer, a floating gate electrode, an inter-gate electrode dielectric layer and a control gate electrode formed upon a semiconductor substrate. To enhance performance of the stacked gate field effect transistor (FET) device, at least one of: (1) the floating gate electrode is formed with a pointed edge tip at its outer sidewall; (2) the floating gate electrode in formed with a pointed linear recess centered within its linewidth; and (3) a pair of source/drain regions is formed asymmetrically penetrating beneath the pair of opposite edges of the floating gate electrode and not laterally spaced from a floating gate electrode sidewall.

Abstract: A structure is disclosed to improve the coupling ratio of top gate to floating gate in flash memory cells. Parallel active regions are surrounded by isolation regions and are disposed over a semiconductor region of a substrate. The isolation regions have a portion within and a portion above the semiconductor region. The semiconductor region under the active regions is doped in the vicinity of the surface to adjust the threshold voltage. Insulator spacers are disposed against the sidewalls of the portion of the isolation regions that are above the semiconductor region and they taper so they arc wider near the semiconductor region, and thus the spacing between neighboring insulator spacers on the same active region decreases closer to the semiconductor region. Conductive floating gates spaced along the active regions are separated from the semiconductor region by a floating gate insulator layer, are disposed between insulator spacers and extend about to the height of the isolation regions.

Abstract: A new structure is disclosed for source/drain bit lines in arrays of MOSFET devices. Rows of conducting regions are formed by ion implantation through openings adjacent to gate structures and in isolation regions separating columns of active areas of the arrays. The openings are filled with insulating material.

Abstract: In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

Abstract: A self-aligned split-gate flash memory cell and its contactless NOR-type memory array are disclosed by the present invention, which comprise a shallow-trench-isolation structure having an integrated floating-gate structure and the embedded double-sides erase cathodes; a self-aligned split-gate flash memory cell having a steep or one-side tapered floating-gate structure; a bit line integrated with planarized common-drain conductive islands; and a common-source conductive bus line. Therefore, the present invention offers a smaller cell area, a higher coupling ratio through an integrated floating-gate structure, a higher erasing speed through the embedded double-sides erase cathodes, higher contact integrity for shallow junction through a common-drain conductive island, and lower bus-line resistance and capacitance through a common-source conductive bus line.

Abstract: A scalable stack-gate flash memory cell and its contactless memory array are disclosed by the present invention, in which the control-gate length and the implanted region of a scalable stack-gate flash memory cell are separately defined by two sidewall dielectric spacers formed over a sidewall on the common-source region and, therefore, can be controlled to be smaller than a minimum-feature-size of technology used; a contactless memory array comprises a plurality of common-source/drain conductive bus lines being formed alternately over the flat beds and a plurality of word lines together with the control-gates of scalable stack-gate flash memory cells being patterned and etched simultaneously by a set of hard masking layers are formed transversely to the plurality of common-source/drain conductive bus lines.

Abstract: In a flash memory device, electrical connections between segment transistors and memory cells are accurately achieved by forming the segment transistors before forming the memory cells. When forming the segment transistors, a first impurity is implanted into a substrate to form a first source and a first drain. A second impurity is then implanted into the substrate to form a conductive line to be used as a common bit line for the memory cells, and simultaneously form a second source below the first source and a second drain below the first drain of the segment transistor. As such, the common bit lines of the memory cells and the second sources of the segment transistors are formed to be electrically connected together with more reliability.

Abstract: In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.

Abstract: Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.

Abstract: A non-volatile semiconductor memory device comprising a device isolation insulation layer, formed on a semiconductor substrate, for defining a device region, a floating gate formed on the device region and having a pair of first side faces opposed to a side face of the device isolation insulation layer, which the side face is located on the device region side, a control gate formed above the floating gate, and a booster electrode having faces opposed to a pair of second surfaces which are substantially perpendicular to the pair of first side faces. A distance between the pair of first side faces of the floating gate is less than a width of the device region defined by the device isolation insulation layer.

Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them.

Abstract: A method for making reduced-size FLASH EEPROM memory circuits, and to the resulting memory circuit. An FET integrated circuit having two different gate oxide thicknesses deposited at a single step, where a portion of the thickness of the thicker oxide is formed, that oxide is removed from the area of the chip to have the thinner oxide, then the rest of the thicker oxide is grown during the time that the thinner oxide is grown on the area of the chip to have the thinner oxide. Layers for the floating gate stacks are deposited. Trenches are etched in a first, and then a second perpendicular direction, and the perpendicular sides of the stacks are covered with vertical-plane nitride layers in two separate operations. Tungsten word lines and bit contacts are deposited. Aluminum-copper lines are deposited on the bit lines.

Abstract: A method of fabricating an improved flash memory device having core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer and oxide layer into the substrate to create source and drain regions, without using a self aligned etch. The flash memory device has an intermetallic dielectric layer placed over the core stacks and the periphery stacks. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device.

Abstract: A non-volatile memory device for retention of data when electrical power is terminated. The non-volatile memory device includes at least one memory cell and a charge pump for stepping up the incoming voltage supply. The charge pump includes at least one capacitor, wherein the dielectric of the charge pump capacitor and the dielectric of the memory cell are formed during the same processing step.

Abstract: A method of forming minimally spaced word lines is disclosed. A double exposure technique is employed at the gate formation level. A small trench is defined through gate stack layers by using a tapered etch or spacers to achieve the desired width of the trench. A filler material fills the trench and forms a filler plug. The gate layers adjacent to the trench are then patterned and etched and the filler plug is removed to obtain gate stacks spaced apart by a distance of less than about 400 Angstroms.

Abstract: A semiconductor transistor comprising a substrate having an active layer formed thereon, a source and a drain formed in the active layer, a gate insulating layer formed on the active layer and a gate electrode formed on the insulating layer, wherein the gate electrode is split, the active layer has a doped region located between the source and the drain and aligned with the split in the gate electrode, and the gate electrode is aligned with the drain so as not to overlap the drain. The transistor may be formed using a method comprising the steps of: providing a semiconductor layer in which the source and drain are to be formed; forming a gate insulating layer on the semiconductor layer; forming a split gate electrode on the gate insulating layer; and using the split gate electrode as a mask in the doping of a portion of the semiconductor layer between the source and the drain of the final transistor.

Abstract: A process for manufacturing a semiconductor memory device includes double polysilicon level non-volatile memory cells and shielded single polysilicon level non-volatile memory cells in the same semiconductor material chip. A first memory cell includes a MOS transistor having a first gate electrode and a second gate electrode superimposed and respectively formed by definition in a first and a second layer of conductive material. A second memory cell is shielded by a layer of shielding material for preventing the information stored in the second memory cell from being accessible from the outside. The second memory cell includes a MOS transistor with a floating gate electrode formed simultaneously with the first gate electrode of the first cell by definition of the first layer of conductive material. The layer of shielding material is formed by definition of the second layer of conductive material.

Abstract: An EEPROM memory cell integrated in a semiconductor substrate comprises a floating gate MOS transistor having a source region, a drain region, and a gate region projecting from the substrate and is isolated from the substrate by an oxide layer including a thinner tunnel portion and heavily doped regions formed under said tunnel portion and extending to beneath the drain region, and a selection transistor having a source region, a drain region and a gate region, wherein said source region is heavily doped and formed simultaneously with said heavily doped regions.

Abstract: A method of fabricating a flash memory cell. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer; forming a barrier layer; removing a portion of the barrier layer to form a first opening; performing an angled implant on the exposed surface of the first conductive layer; forming a floating gate insulating layer; removing the barrier layer; forming a floating gate and a first gate insulating layer; forming a second insulating layer; forming a second conductive layer; removing portions of the second conductive layer and the second insulating layer to form a second opening and a third opening; forming a source region on the substrate; forming spacers on the sidewalls of the second opening and the third opening; and forming drain regions on the substrate within the third opening.

Abstract: A new method is provides for the creation of a hardmask over a layer of polysilicon for the etching of floating gate for split-gate flash memory devices. A layer of gate oxide is created over the surface of a substrate, a layer of polysilicon is deposited over the surface of the layer of gate oxide. In a first embodiment of the invention, a layer of native oxide is grown over the surface of the layer of gate material, this layer of gate oxide is used to enhance oxidation of exposed portions of the layer of gate material. In a second embodiment of the invention, enhanced oxidation of exposed portions of the layer of polysilicon is achieved by modifying the conventional sequence of the oxidation process. This latter modification is realized by modifying the forward motion of the substrates through the oxidation furnace or by modifying the sequence in which the substrates move through the oxidation furnace.

Abstract: A split-gate semiconductor device is fabricated by forming floating gates on the sidewalls of the control gates of transistors, then using a bottom anti-reflective coating as a mask while removing unnecessary floating gates, preferably by an isotropic dry etching process that removes floating-gate material from the sidewalls faster than it removes dielectric material from the upper parts of the control gates. Alternatively, control gate structures are formed, floating-gate material is deposited, removed, then deposited again to form floating gates on the sidewalls of the control gate structures, and the central parts of the control gate structures are etched to leave control gates with floating gates on one sidewall each.

Abstract: A novel flash memory structure is disclosed, which includes a tunnel oxide layer on a semiconductor substrate, an array of gate electrode stacks formed on the tunnel oxide layer, and alternating source/drain regions formed between the stacks. A first dielectric layer is formed over the stacks and the substrate with a source line opening down to the source regions. A source line is formed above the source regions, partially filling the source line opening. The source line is located between the gate electrode stacks and has a surface level below a top surface of the stacks. A second dielectric layer is formed over the source line and the first dielectric layer with a plug opening down to the drain regions. A drain metal plug is formed over the drain regions, filling the plug opening. A metal bit line is formed over the second dielectric layer contacting the drain metal plug.

Abstract: A method of manufacturing a flash memory device is characterized by preventing photoresist patterns from being formed directly on or removed directly from a surface of the substrate or the dielectric layer. This is accomplished by separately forming a control gate layer of transistors in a cell area of the substrate and a gate layer of transistors in a peripheral circuit area of the substrate. The method of the present invention includes the steps of forming in a peripheral circuit area of the substrate a gate insulating layer for both high and low voltage regions of the peripheral circuit area and then forming the gate conduction layer on the gate insulating layer. The method of the present invention further comprises the steps of forming in a cell area of the substrate a transistor structure composed of a tunneling gate insulating layer, a floating gate layer, a dielectric layer, and a control gate layer.

Abstract: An improved method of fabricating a non-volatile semiconductor device having a BPTEOS oxide film is provided. The present method utilizes the step of performing a RTA at a temperature of about 800° C. immediately after the deposition of the BPTEOS film so as to densify and stabilize the same. Then, a CMP step is performed so as to planarize the BPTEOS film.

Abstract: A method for fabricating a nonvolatile semiconductor memory device according to the present invention includes patterning an insulating film for forming a tunnel insulating film and a conductor film for forming a floating gate electrode and forming a well region of a first conductivity type in the logic circuit portion of a semiconductor substrate. This prevents the well region in the logic circuit portion from experiencing a thermal budget resulting from the formation of the insulating film and the conductor film.

Abstract: First of all, a semiconductor substrate has the poly regions thereon. Then the souse/drain regions are formed in the semiconductor substrate by performing the ion-implant method. Next, the dielectric layers are formed on the souse/drain regions and between the poly regions. For increasing the coupling ratio of the flash memory, the photoresist layers, individually, are defined on the dielectric layers and the poly regions. Afterward, the dielectric layers are etched by performing an etched process and the photoresist layers as etched masks, wherein the dielectric layers have the swing-like surfaces with large surface area after the etched process is finished. The photoresist layers are then removed. A polysilicon layer is formed along swing-like surfaces of dielectric layers and the surfaces of the poly regions by conforming method, while the polysilicon layer is patterned to form the first gates. Then an ONO layer is formed along the surfaces of the first poly gates by conforming method.

Abstract: A method for fabricating split gate flash memory cell. The method includes sequentially forming conductive layers and insulating layers on a semiconductor substrate, followed by forming a first opening in the conductive layers and the insulating layers. Next, a shallow trench isolation is defined in the first opening and an insulating layer is defined simultaneously in the active area within the shallow trench isolation to form a first gate isolation layer. Then, a conductive sidewall layer is formed on the sidewalls of the first gate insulating layer. The first gate insulating layer and the conductive sidewall layer are used as a hard mask to remove the conductive layer not covered by the hard mask, thus forming a floating gate comprised of the conductive sidewall layer and the conductive layer underneath. A second gate insulating layer, control gate and source/drain are then formed conventionally.

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.