Abstract: A split gate (flash) EEPROM cell and a method for manufacturing the same is disclosed, in which a control gate and a floating gate are formed in a vertical structure, to minimize a size of the cell, to obtain a high coupling ratio, and to lower a programming voltage. The split gate EEPROM cell includes a semiconductor substrate having a trench; a tunneling oxide layer at sidewalls of the trench; a floating gate, a dielectric layer and a control gate in sequence on the tunneling oxide layer; a buffer dielectric layer at sidewalls of the floating gate and the control gate; a source junction in the semiconductor substrate at the bottom surface of the trench; a source electrode in the trench between opposing buffer dielectric layers, electrically connected to the source junction; and a drain junction on the surface of the semiconductor substrate outside the trench.

Abstract: A semiconductor storage cell includes a first source/drain region underlying a first trench defined in a semiconductor layer. A second source/drain region underlies a second trench in the semiconductor layer. A first select gate in the first trench and a second select gate in the second trench are lined by a select gate dielectric. A charge storage stack overlies the select gates and a control gate overlies the stack. The DSEs may comprise discreet accumulations of polysilicon. An upper surface of the first and second select gates is lower than an upper surface of the first and second trenches. The control gate may be a continuous control gate traversing and running perpendicular to the select gates. The cell may include contacts to the semiconductor layer. The control gate may include a first control gate overlying the first select gate and a second control gate overlying the second select gate.

Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure.

Abstract: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.

Abstract: A method for manufacturing a semiconductor device includes: forming a lower gate electrode over a substrate; forming a sacrifice film over the substrate such that the lower gate electrode is overlapped with the sacrifice film; forming a semiconductor film over the sacrifice film such that the semiconductor film crosses over the lower gate electrode; removing the sacrifice film; forming a lower gate insulating film in an empty space between the lower gate electrode and the semiconductor film, the empty space being obtained by removing the sacrifice film; forming an upper gate insulating film over the semiconductor film; and forming an upper gate electrode over the upper gate insulating film, the upper gate electrode being electrically connected to the lower gate electrode.

Abstract: Method for fabricating a semiconductor device, including the steps of providing a first conductive type semiconductor substrate having a cell region and a logic region defined thereon, forming a first insulating film, second conductive type polysilicon, and a second insulating film in succession on the semiconductor substrate, selectively removing the first insulating film, the polysilicon, and the second insulating film, to form a floating gate pattern at the cell region, elevating a temperature initially in a state O2 gas is injected, maintaining a fix temperature, and dropping the temperature in a state N2 gas is injected, to form a gate oxide film on a surface of the semiconductor substrate at the logic region, and forming a gate electrode pattern at each of the cell region and the logic region, whereby preventing a threshold voltage of a semiconductor device from dropping due to infiltration of impurities from doped polysilicon at the cell region to the active channel region.

Abstract: An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure.

Abstract: Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic array in a high density field programmable logic array (FPLA). The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will provide an indication of the stored data at this location in the memory array within the EEPROM or will act as the absence of a transistor at this location in the logic array within the FPLA.

Abstract: A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the layer tunnel junction barrier. The device further includes a second gate insulator layer on a sidewall of the tunnel junction barrier, a third gate insulator on a second portion of the substrate adjacent the tunnel junction barrier and a gate electrode on the second gate insulator and the third gate insulator. First and second impurity-doped regions are disposed in the substrate and are coupled by a channel through the first and second portions of the substrate. Fabrication of such a device is also describes.

Abstract: Methods for fabricating flash memory devices are disclosed. A disclosed method comprises: forming a polysilicon layer on a semiconductor substrate; injecting dopants having stepped implantation energy levels into the polysilicon layer; forming a photoresist pattern on the polysilicon layer; and etching the polysilicon layer to form a floating gate.

Abstract: A process for forming an electronic device can be performed, such that as little as one gate electric layer may be formed within each region of the electronic device. In one embodiment, the electronic device can include an NVM array and other regions that have different gate dielectric layers. By protecting the field isolation regions within the NVM array and other regions while gate dielectric layer are formed, the field isolation regions may be exposed to as little as one oxide etch between the time any of the gate dielectric layers are formed the time such gate dielectric layers are covered by gate electrode layers. The process helps to reduce field isolation erosion and reduce problems associated therewith.

Abstract: A semiconductor memory device provided with a memory cell region having first gate electrodes and a peripheral circuit region having second gate electrodes includes first gate electrodes arranged a first distance apart from each other on a semiconductor substrate, second gate electrodes arranged a second distance, which is larger than the first distance, apart from each other on the semiconductor substrate, first diffusion layers formed in the semiconductor substrate, the first diffusion layers sandwiching the first gate electrodes, second diffusion layers formed in the semiconductor substrate, the second diffusion layers sandwiching the second gate electrodes, a first insulating film formed on the first diffusion layer, second insulating films formed on the side surfaces of the second gate electrodes, first silicide films formed on the first gate electrodes, second silicide films formed on the second gate electrodes, and third silicide films formed on the second diffusion layers.

Abstract: Embodiments relate to a method of manufacturing a semiconductor device that may simplify a manufacturing process and may reduce process costs. According to embodiments, the method may include simultaneously forming a first gate of a first device area and a second gate of a second device area, patterning a PMD layer to form a first contact hole exposing the first gate, depositing and planarizing a high dielectric constant material and first and second metallic materials on the semiconductor substrate to expose PMD layer, forming an insulating layer, a metal layer and a third gate in the first contact hole, patterning the PMD layer to form a second contact hole exposing the second gate, and depositing a third metallic material on the semiconductor substrate and planarizing it such that the PMD layer is exposed, thereby forming a contact in the second contact hole.

Abstract: A nonvolatile memory device includes a semiconductor substrate; a source region that is formed in the semiconductor substrate; a gate insulating film that is formed so as to partially overlap the source region on the semiconductor substrate; a floating gate that is formed on the gate insulating film so as to have a structure forming a uniform electric field in the portion that overlaps the source region; a control gate that is formed so as to be electrically isolated along one sidewall of the floating gate from an upper part of the floating gate, an inter-gate insulating film that is interposed between the floating gate and the control gate, and a drain region that is formed so as to be adjacent the other side of the control gate.

Abstract: A manufacturing method of a non-volatile memory includes first providing a substrate for defining multiple pairs of active regions; forming a control gate in one of each pair of the active regions of the substrate; sequentially forming a gate oxide layer, a conductor layer, and a patterned mask layer on the substrate, wherein the patterned mask layer exposes a portion of the conductor layer; forming a first dielectric layer on the exposed portion of the conductor layer; removing the patterned mask layer; removing the conductor layer without covering the first dielectric layer, and using the remained conductor layer as the floating gate; forming a second dielectric layer on sidewalls of the floating gate; forming an erase gate above the floating gate and correspondingly above the control gate, and forming a source region and a drain region in the other one of each pair of the active regions.

Abstract: The method for fabricating the semiconductor device includes the steps of: forming an insulating film 20, a conductive film 22 and an insulating film 24 over a semiconductor substrate 10 having a first to a third region; removing an insulating film 24, the conductive film 22 and an insulating film 20 formed in the second region and the third region; forming an insulating film 38 in the second region and the third region; removing the insulating film 24 in the first region and the insulating film 38 in the third region; forming an insulating film 44 in the third region; after a conductive film 52 has been formed, patterning the conductive films 22, 52 in the first region to form a gate electrode 58; and patterning the conductive film 52 to form gate electrodes 62 in the second region and the third region while removing the conductive film 52 over the gate electrode 58.

Abstract: A method of manufacturing a non-volatile memory device includes the steps of forming gates respectively having a structure in which a gate insulating layer, a first conductive layer, a dielectric layer, a second conductive layer and a metal-silicide layer are laminated over a semiconductor substrate, annealing the metal-silicide layer at a temperature, which is the same as or lower than an annealing temperature of the dielectric layer, forming a buffer oxide layer on the entire surface, and forming a nitride layer on the buffer oxide layer.

Abstract: A storage device structure (10) has two bits of storage per control gate (34) and uses source side injection (SSI) to provide lower programming current. A control gate (34) overlies a drain electrode formed by a doped region (22) that is positioned in a semiconductor substrate (12). Two select gates (49 and 50) are implemented with conductive sidewall spacers adjacent to and lateral to the control gate (34). A source doped region (60) is positioned in the semiconductor substrate (12) adjacent to one of the select gates for providing a source of electrons to be injected into a storage layer (42) underlying the control gate. Lower programming results from the SSI method of programming and a compact memory cell size exists.

Abstract: A method of forming a semiconductor device includes forming line patterns on a substrate, the line patterns defining narrow and wide gap regions, forming spacer patterns in the narrow and wide gap regions on sidewalls of the line patterns, spacer patterns in the wide gap regions exposing an upper surface of the substrate, and spacer patterns in the narrow gap regions contacting each other to fill the narrow gap regions, forming an insulating interlayer to cover the spacer patterns and the line patterns, forming at least one opening through the insulating interlayer, the opening including at least one contact hole selectively exposing the upper surface of the substrate in the wide gap region, the contact hole being formed by using the spacer patterns in the narrow gap region as an etching mask, and forming a conductive pattern to fill the opening.

Abstract: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

Abstract: A semiconductor memory device comprises: a plurality of transistors having a stacked-gate structure, each transistor including a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a silicide suppression region between the aperture and the gate insulator to suppress diffusion of metal atoms from the silicided upper gate.

Abstract: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate, and can be electrically connected to the source region.

Abstract: A salicide treatment is performed on a common source line to reduce surface resistance and contact resistance, thereby improving a cell current characteristic. Therefore, a chip can be reduced in size and chips per wafer can be increased, thereby achieving high yield. In addition, it is possible to overcome the structural limitation of the flash cell when the semiconductor memory device is highly integrated and shrunken.

Abstract: A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and along first and second sides of the pillar. A gate material layer is formed over the gate dielectric and pillar. An etch is performed to leave a first portion of the gate material laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate.

Abstract: A method of fabricating a flash memory is provided. The method includes forming a tunneling insulating film, a charge storage film, and a blocking insulating film on a semiconductor substrate; performing High Temperature (HT) anneal for the resultant semiconductor substrate; and performing Low Temperature (LT) wet vapor anneal for the resultant semiconductor substrate.

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Abstract: A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed of nanoparticles. The nanowires may be ambipolar carbon nanotubes (CNTs). The first element may be a channel layer. The second element may be a charge trap layer. In this regard, the semiconductor device may be a transistor or a memory device.

Abstract: The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.

Abstract: A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.

Abstract: A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches.

Abstract: Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.

Abstract: Nonvolatile memory devices and methods of fabricating and driving the same are disclosed. Disclosed devices and method comprises: growing an oxide layer on a substrate and depositing a nitride layer on the oxide layer; patterning the nitride layer; forming injection gates on the lateral faces of the nitride layer; depositing a first polysilicon, a dielectric layer and a second polysilicon on the surface of the resulting structure, sequentially; patterning the second polysilicon, the dielectric layer and the second polysilicon to form gate electrodes; removing the nitride layer between the injection gates; forming source and drain extension regions around each of the gate electrodes by performing an ion implantation process; forming sidewall spacers on the lateral faces of the gate electrodes; and forming source and drain regions in the substrate by performing an ion implantation process with the sidewall spacers as an ion implantation mask.

Abstract: Disclosed is a floating gate of a flash memory device, wherein a tunneling oxide layer is formed on a semiconductor substrate, and a floating gate is formed in the shape of a lens having a convex top surface.

Abstract: A manufacturing method of a non-volatile memory includes first providing a substrate for defining multiple pairs of active regions; forming a control gate in one of each pair of the active regions of the substrate; sequentially forming a gate oxide layer, a conductor layer, and a patterned mask layer on the substrate, wherein the patterned mask layer exposes a portion of the conductor layer; forming a first dielectric layer on the exposed portion of the conductor layer; removing the patterned mask layer; removing the conductor layer without covering the first dielectric layer, and using the remained conductor layer as the floating gate; forming a second dielectric layer on sidewalls of the floating gate; forming an erase gate above the floating gate and correspondingly above the control gate, and forming a source region and a drain region in the other one of each pair of the active regions

Abstract: A sensing memory device disposed on a substrate is provided, which includes a first conductive layer, a second conductive layer and a charge trapping layer. The second conductive layer covers the first conductive layer. The charge trapping layer is disposed between the first conductive layer and the second conductive layer.

Abstract: A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.

Abstract: Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic array in a high density field programmable logic array (FPLA). The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will provide an indication of the stored data at this location in the memory array within the EEPROM or will act as the absence of a transistor at this location in the logic array within the FPLA.

Abstract: A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure overlies the dielectric layer and has a first current electrode and a second current electrode separated by a channel. A floating gate has a vertical portion that is adjacent to and electrically insulated from a side of the channel and has a horizontal portion overlying the first dielectric layer and extending laterally away from the channel. The floating gate stores electrical charge. A second dielectric layer is adjacent the floating gate. A control gate adjacent the second dielectric layer and physically separated from the floating gate by the second dielectric layer. The “L-shape” of the floating gate enhances capacitive coupling ratio between the control gate and the floating gate.

Abstract: A scalable two-transistor memory (STTM) device includes a planar transistor and a vertical transistor on a semiconductor substrate. The planar transistor includes spaced apart metal silicide source/drain regions on the substrate and a floating gate electrode on the substrate between the metal silicide source/drain regions that controls a channel region of the planar transistor. The vertical transistor includes a tunnel junction structure on the floating gate electrode and a control gate electrode on a sidewall of the tunnel junction structure that controls a channel region of the vertical transistor. Related methods of forming STTM devices are also discussed.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: A method of manufacturing a nonvolatile semiconductor memory comprising: forming a gate insulating film formed on a surface of a semiconductor substrate; forming a source region and a drain region in the semiconductor substrate; forming a floating gate electrode on the gate insulating film; forming a inter-gate insulating film on the floating gate electrode; forming a control gate electrode on the inter-gate insulating film; forming a source contact region wherein the source contact region is electrically contact to said source region, and top part of said source contact region is lower than bottom part of said control gate electrode.

Abstract: A semiconductor device is provided. The semiconductor device according to the present invention includes a semiconductor substrate, a second insulation layer, a buffer insulation layer adjacent to the second insulation layer, a third insulation layer and transistors. A high voltage device region and a low voltage device region are defined in the semiconductor substrate. The second and third insulation layers are formed in the high and low voltage device regions, respectively. The transistors are formed on the second and third insulation layers, respectively.

Abstract: Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.

Abstract: Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.

Abstract: A method for manufacturing a memory unit capable of storing multibits binary information. A gate is formed on a dielectric layer over a semiconductor substrate. Next, a first etching is performed to etch the semiconductor substrate by using the gate acting as an etching mask to remove exposed surface of the dielectric layer. Subsequently, a first oxide layer is conformally formed on the gate and the semiconductor substrate. An charge-trapping layer is conformally formed on the first oxide layer, and subsequently a second oxide layer is conformally formed on the isolating layer. Next, a second etching is performed to etch the second oxide layer and the charging-trapping layer to form sandwich spacers composed of the second oxide layer/the isolating layer/the first oxide layer on the substrate and the gate sidewall.

Abstract: A semiconductor device includes a gate electrode having a straight portion, a dummy electrode located at a point on the extension of the straight portion, a stopper insulating film, a sidewall insulating film, an interlayer insulating film, and a linear contact portion extending, when viewed from above, parallel to the straight portion. The longer side of the rectangle defined by the linear contact portion is, when viewed from above, located beyond the sidewall insulating film and within the top region of the gate electrode and the dummy electrode. A gap G between the gate electrode and the dummy electrode appearing, when viewed from above, in the linear contact portion is filled with the sidewall insulating film such that the semiconductor substrate is not exposed.

Abstract: A flash memory device includes trenches that are formed at regions on a semiconductor substrate spaced apart from one another at predetermined distances, buried floating gates buried into the trenches, a plurality of isolation structures formed between the buried floating gates, and a dielectric film and a control gate formed on the buried floating gates.

Abstract: A method for manufacturing a flash memory device including the steps of forming a gate oxide film for high voltage on the whole surface of a semiconductor substrate on which a cell region, a low voltage region and a high voltage region have been formed, etching the gate oxide film for high voltage formed in the cell region and the low voltage region by a predetermined depth, by forming photoresist patterns to expose the gate oxide film for high voltage formed in the cell region and the low voltage region, and performing a wet etching process using the photoresist patterns as an etching mask, removing the entire gate oxide film for high voltage formed in the cell region and the low voltage region, by performing a cleaning process on the resulting structure, removing the photoresist patterns, forming a floating gate electrode and a control gate electrode, by sequentially forming a tunnel oxide film, a first polysilicon film, a second polysilicon film, a dielectric film, a third polysilicon film and a metal sili

Abstract: A self-aligned split gate bitcell includes first and second regions of charge storage material separated by a gap devoid of charge storage material. Spacers are formed along sidewalls of sacrificial layer extending above and on opposite sides of the bitcell stack, wherein the spacers are separated from one another by at least a gap length. Etching the bitcell stack, selective to the spacers, forms a gap that splits the bitcell stack into first and second gates which together form the split gate bitcell stack. A storage portion of bitcell stack is also etched, wherein etching extends the gap and separates the corresponding layer into first and second separate regions, the extended gap being devoid of charge storage material. Dielectric material is deposited over the gap and etched back to expose a top surface of the sacrificial layer, which is thereafter removed to expose sidewalls of the split gate bitcell stack.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first floating gate formed on a main surface of the semiconductor substrate, a second floating gate formed on the main surface of the semiconductor substrate, a first control gate formed on the first floating gate, a second control gate formed on the second floating gate, an interlayer insulating film, and a gap formed in the interlayer insulating film in at least a portion located between the first and second floating gates. Accordingly, a nonvolatile semiconductor memory device for which variations in threshold voltage of a memory cell can be suppressed and an appropriate read operation can be carried out, as well as a method of manufacturing the nonvolatile semiconductor memory device are provided. Further, a capacitance formed between interconnect lines can be reduced and the drive speed can be improved.