Utilizing Epitaxial Semiconductor Layer Grown Through An Opening In An Insulating Layer Patents (Class 438/269)
  • Patent number: 10964717
    Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming, on a substrate, a stack of alternating layers including a first layer of material and a second layer of material different from the first layer of material; forming a memory hole in the stack of alternating layers of the first layer of material and the second layer of material; depositing a layer of blocking oxide on sides defining the memory hole; depositing a layer of silicon atop the layer of blocking oxide to form a silicon channel; deposit core oxide to fill the silicon channel; removing the first layer of material to form spaces between the alternating layers of the second material; and one of depositing a third layer of material to partially fill the spaces to leave air gaps therein or depositing a fourth layer of material to fill the spaces.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 30, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sung-Kwan Kang, Gill Lee, Chang Seok Kang, Tomohiko Kitajima
  • Patent number: 10804296
    Abstract: A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: October 13, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. Hall, Gordon M. Grivna
  • Patent number: 10770474
    Abstract: A manufacturing method of a semiconductor device includes: forming pillars in a first region of a stack structure in which interlayer insulating layers and sacrificial insulating layers are alternately stacked; forming a slit in a second region of the stack structure; and removing the sacrificial insulating layers in the first region. In the removing of the sacrificial insulating layers in the first region, a portion of each of the sacrificial insulating layers, which is adjacent to the slit, and a portion of each of the sacrificial insulating layers, which is disposed between the pillars, may be removed using different etching materials.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: September 8, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang Hyon Kwak, Duk Eui Lee, Nam Gyu Kim
  • Patent number: 10714342
    Abstract: Semiconductor devices and method of forming the same are disclosed. One of the semiconductor devices includes a substrate, a gate structure, a plug and a hard mask structure. The gate structure is disposed over the substrate. The plug is disposed over and electrically connected to the gate structure. The hard mask structure is disposed over the gate structure and includes a first hard mask layer and a second hard mask layer. The first hard mask layer surrounds and is in contact with the plug. The second hard mask layer surrounds the first hard mask layer and has a bottom surface at a height between a top surface and a bottom surface of the first hard mask layer. A material of the first hard mask layer is different from a material of the second hard mask layer.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Che Chiang, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 10516048
    Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Chih Chen, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
  • Patent number: 10475807
    Abstract: A method for manufacturing three-dimensional memory, comprising the steps of: forming a stack structure composed of a plurality of first material layers and a plurality of second material layers on a substrate; etching the stack structure to expose the substrate, forming a plurality of first vertical openings; forming a filling layer in each of the first openings; etching the stack structure around each of the first openings to expose the substrate, forming a plurality of second vertical openings; forming a vertical channel layer and a drain in each of the second openings; removing the filling layer by selective etching, re-exposing the first openings; partially or completely removing the second material layers by lateral etching, leaving a plurality of recesses; forming a plurality of gate stack structure in the recesses; forming a plurality of common sources on and/or in the substrate at the bottom of each of the first openings.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: November 12, 2019
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zongliang Huo, Ming Liu, Lei Jin
  • Patent number: 10410932
    Abstract: A method for producing a pillar-shaped semiconductor device includes forming, above a NiSi layer serving as a lower wiring conductor layer and connecting to an N+ layer of an SGT formed within a Si pillar, a first conductor W layer that extends through a NiSi layer serving as an upper wiring conductor layer and connecting to a gate TiN layer and that extends through a NiSi layer serving as an intermediate wiring conductor layer and connecting to an N+ layer; forming an insulating SiO2 layer between the NiSi layer and the W layer; and forming a second conductor W layer so as to surround the W layer and have its bottom at the upper surface layer of the NiSi layer, to achieve connection between the NiSi layer and the NiSi layer.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 10, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 10243037
    Abstract: According to one embodiment, a semiconductor device includes first to fourth semiconductor regions, a first electrode, and a first insulating film. The first semiconductor region includes a first partial region and a second partial region. The second semiconductor region is separated from the first partial region. The third semiconductor region is provided between the first partial region and the second semiconductor region. The third semiconductor region includes a third partial region and a fourth partial region. The first electrode is separated from the second partial region and is separated from the second semiconductor region and the third semiconductor region. The first insulating film includes a first insulating region and a second insulating region. The fourth semiconductor region includes a first portion. The first portion is provided between the fourth partial region and at least a portion of the first insulating film.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: March 26, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Kyogoku, Ryosuke Iijima
  • Patent number: 10199278
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate, wherein a hardmask is formed on each of the plurality of fins, forming a gate structure around the plurality of fins, selectively depositing a dummy dielectric on the hardmask on each of the plurality of fins, depositing a dielectric layer on the gate structure and around the dummy dielectrics, selectively removing the dummy dielectrics and the hardmasks with respect to the dielectric layer and the gate structure to create a plurality of openings exposing portions of the gate structure, and selectively removing the exposed portions of the gate structure through the plurality of the openings.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: February 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9842857
    Abstract: A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening through the stack, forming an aluminum oxide layer having a horizontal portion at a bottom of the memory opening and a vertical portion at least over a sidewall of the memory opening, where the horizontal portion differs from the vertical portion by at least one of structure or composition, and selectively etching the horizontal portion selective to the vertical portion.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: December 12, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Sateesh Koka, Raghuveer S. Makala, Srikanth Ranganathan, Mark Juanitas, Johann Alsmeier
  • Patent number: 9786679
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a mask layer on the stacked body. The method includes forming a stopper film in a part of the mask layer. The method includes forming a plurality of mask holes in the mask layer. The mask holes include a first mask hole overlapping on the stopper film. The method includes, by etching using the mask layer, forming holes in the stacked body under other mask holes than the first mask hole on the stopper film, but not forming holes in the stacked body under the stopper film. The method includes forming memory films and channel bodies in the holes.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: October 10, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi, Mitsuhiro Omura
  • Patent number: 9780096
    Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-yong Park, Kee-jeong Rho, Hyeong Park, Tae-wan Lim
  • Patent number: 9673216
    Abstract: Disclosed herein are methods of forming memory cell films in 3D memory. An opening having a sidewall may be formed through a stack of alternating layers of silicon oxide and silicon nitride. Bird's beaks may be formed in the silicon nitride at interfaces with the silicon oxide. In one aspect, bird's beaks are formed using a wet SiN etch. In one aspect, bird's beaks are formed by oxidizing SiN. A dilute hydrofluoric acid (DHF) clean may be performed within the opening after forming the bird's beaks in the silicon nitride. A memory cell film may be formed in the opening after performing the DHF clean. The memory cell film is straight, or nearly straight, from top to bottom in a memory hole. The memory cell film is not as susceptible to parasitic charge trapping as a memory cell film having a wavy contour. Therefore, neighbor WL interference may be reduced.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: June 6, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Ashish Baraskar, Liang Pang, Yingda Dong, Ching-huang Lu
  • Patent number: 9627220
    Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. The methods may include two or more nitride removal steps during formation of gate layers in vertical memory cells. The two or more nitride removal steps may allow for wider gate layers increasing the gate fill-in, reducing the occurrence of voids, and thereby improving the word line resistance.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: April 18, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Jr-Meng Wang, Chih-Yuan Wu, Kuanf-Wen Liu, Jung-Yi Guo, Chun-Min Cheng
  • Patent number: 9613979
    Abstract: Manufactured in a method of manufacturing according to an embodiment is a semiconductor memory device including: control gate electrodes; a semiconductor layer; and a charge accumulation layer. In this method of manufacturing, inter-layer insulating layers and sacrifice layers are stacked alternately, an opening that penetrates the inter-layer insulating layers and sacrifice layers is formed, a first insulating layer, the charge accumulation layer, and the semiconductor layer are formed in the opening, the sacrifice layer and part of the first insulating layer are removed, and the control gate electrodes are formed. An internal diameter of the opening is smaller the more downwardly a portion of the opening is positioned. A film thickness of the first insulating layer is smaller the more downwardly a portion of the first insulating layer is positioned.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: April 4, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshihiko Iinuma
  • Patent number: 9530899
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: December 27, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bi O Kim, Jin-Tae Noh, Su-Jin Shin, Jae-Young Ahn, Ki-Hyun Hwang
  • Patent number: 9490331
    Abstract: A semiconductor arrangement and methods of formation are provided. A semiconductor arrangement includes a semiconductor column on a buffer layer over a substrate. The buffer layer comprises a conductive material. Both a first end of the semiconductor column and a bottom contact are connected to a buffer layer such that the first end of the semiconductor column and the bottom contact are connected to one another through the buffer layer, which reduces a contact resistance between the semiconductor column and the bottom contact. A second end of the semiconductor column is connected to a top contact. In some embodiments, the first end of the semiconductor column corresponds to a source or drain of a transistor and the second end corresponds to the a drain or source of the transistor.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Georgios Vellianitis
  • Publication number: 20150145020
    Abstract: A method of fabricating a three-dimensional (3D) semiconductor memory device is provided. Sacrificial layers and insulating layers are alternately and repeatedly stacked on a top surface of a substrate to form a thin layer structure. A channel structure penetrating the thin layer structure is formed to be in contact with the substrate. A trench penetrating the thin layer structure is formed. The sacrificial layers, the insulating layers and the substrate are exposed in the trench. A recess region formed in the substrate exposed by the trench. A semiconductor pattern filling is formed the recess region. The sacrificial layers exposed by the trench are replaced with gate patterns.
    Type: Application
    Filed: October 9, 2014
    Publication date: May 28, 2015
    Inventors: CHAEHO KIM, KIHYUN HWANG, DONGWOO KIM, WOONG LEE, JUNGGEUN JEE
  • Publication number: 20150137210
    Abstract: A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.
    Type: Application
    Filed: November 18, 2014
    Publication date: May 21, 2015
    Inventors: Phil-Ouk NAM, Jun-Kyu YANG, Jin-Gyun KIM, Jae-Young AHN, Hun Hyeong LIM, Ki-Hyun HWANG
  • Publication number: 20150137209
    Abstract: A semiconductor device includes a first channel layer, a second channel layer protruding from the first channel layer, a pipe gate including a silicide area surrounding the first channel layer, a tunnel insulating layer surrounding the second channel layer, a data storage layer surrounding the second channel layer with the tunnel insulating layer interposed therebetween, and interlayer insulating layers and conductive patterns which are alternately stacked while surrounding the second channel layer with the data storage layer and the tunnel insulating layer interposed therebetween.
    Type: Application
    Filed: March 11, 2014
    Publication date: May 21, 2015
    Applicant: SK hynix Inc.
    Inventor: Nam Jae LEE
  • Patent number: 9029219
    Abstract: A method for manufacturing a semiconductor wafer includes a carbon layer formation step, a through hole formation step, a feed layer formation step, and an epitaxial layer formation step. In the carbon layer formation step, a carbon layer (71) is formed on a surface of a substrate (70) made of polycrystalline SiC. In the through hole formation step, through holes (71c) are formed in the carbon layer (71) formed on the substrate (70). In the feed layer formation step, a Si layer (72) and a 3C—SiC polycrystalline layer (73) are formed on a surface of the carbon layer (71). In the epitaxial layer formation step, the substrate (70) is heated so that a seed crystal made of 4H—SiC single crystal is formed on portions of the surface of the substrate (70) that are exposed through the through holes (71c), and a close-spaced liquid-phase epitaxial growth of the seed crystal is caused to form a 4H—SiC single crystal layer.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: May 12, 2015
    Assignees: Kwansei Gakuin Educational Foundation, Toyo Tanso Co., Ltd.
    Inventors: Tadaaki Kaneko, Noboru Ohtani, Shoji Ushio, Ayumu Adachi, Satoru Nogami
  • Patent number: 9018064
    Abstract: A method of doping the polycrystalline channel in a vertical FLASH device is disclosed. This method uses a plurality of high energy ion implants to dope the channel at various depths of the channel. In some embodiments, these ion implants are performed at an angle offset from the normal direction, such that the implanted ions pass through at least a portion of the surrounding ONO stack. By passing through the ONO stack, the distribution of ranges reached by each ion may differ from that created by a vertical implant.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: April 28, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Andrew M. Waite, Jonathan Gerald England, Rajesh Prasad
  • Publication number: 20150099339
    Abstract: A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.
    Type: Application
    Filed: December 12, 2014
    Publication date: April 9, 2015
    Inventors: Min-Soo KIM, Dong-Sun SHEEN, Seung-Ho PYI, Sung-Jin WHANG
  • Patent number: 8987071
    Abstract: A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: March 24, 2015
    Assignee: National Applied Research Laboratories
    Inventors: Min-Cheng Chen, Chang-Hsien Lin, Chia-Yi Lin, Tung-Yen Lai, Chia-Hua Ho
  • Publication number: 20150072492
    Abstract: A method for fabricating a non-volatile memory device includes alternately stacking a plurality of inter-layer dielectric layers and a plurality of sacrificial layers over a substrate, forming at least a channel hole that exposes the substrate by selectively etching the inter-layer dielectric layers and the sacrificial layers, forming a protective layer on sidewalls of the sacrificial layers that are exposed through the channel hole, sequentially forming a memory layer and a channel layer on the sidewalls of the channel hole, forming slit holes that penetrate through the inter-layer dielectric layers and the sacrificial layers on both sides of the channel hole, removing the sacrificial layers that are exposed through the slit holes, removing the protective layer, and forming gate electrodes in space from which the sacrificial layers and the protective layer are removed.
    Type: Application
    Filed: November 13, 2014
    Publication date: March 12, 2015
    Inventors: Seok-Min JEON, Sun-Kak HWANG
  • Publication number: 20150069499
    Abstract: According to one embodiment, the stacked body includes a plurality of electrode layers and a plurality of insulating layers alternately stacked on the substrate. The plurality of contact parts are provided in a protruding shape on respective end parts of the plurality of electrode layers. The plurality of contact parts do not overlap each other in the stacking direction. The plurality of contact parts are displaced in a surface direction of the substrate. The plurality of plugs extends from the respective contact parts toward the respective circuit interconnections and electrically connects the respective contact parts with the respective circuit interconnections.
    Type: Application
    Filed: March 11, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi NAKAKI
  • Publication number: 20150061007
    Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Shou-Wei Lee, Shao-Chi Yu, Hong-Seng Shue, Kun-Ming Huang, Po-Tao Chu
  • Patent number: 8969156
    Abstract: An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Publication number: 20150056771
    Abstract: A semiconductor device with a super-junction structure is provided, including: a semiconductor substrate having a first conductivity type; an epitaxial layer having the first conductivity type formed over the semiconductor substrate; a first doping region having the first conductive type formed in a portion of the epitaxial layer; a second doping region having a second conductivity type formed in a portion of the of the epitaxial layer; a third doping region having the second conductivity type formed in a portion of the of the epitaxial layer, wherein the doping region partially comprises doped polysilicon materials having the second conductivity type; a gate dielectric layer formed over the epitaxial layer, partially overlying the well region; and a gate electrode formed over a portion of the gate dielectric layer.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 26, 2015
    Inventor: Tsung-Hsiung LEE
  • Patent number: 8962432
    Abstract: A method for forming semiconductor devices using damascene techniques provides self-aligned conductive lines that have an end-to-end spacing less than 60 nm without shorting. The method includes using at least one sacrificial hardmask layer to produce a mandrel and forming a void in the mandrel. The sacrificial hardmask layers are formed over a base material which is advantageously an insulating material. Another hardmask layer is also disposed over the base material and under the mandrel in some embodiments. Spacer material is formed alongside the mandrel and filling the void. The spacer material serves as a mask and at least one etching procedure is carried out to translate the pattern of the spacer material into the base material. The patterned base material includes trenches and raised portions. Conductive features are formed in the trenches using damascene techniques.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Publication number: 20150041879
    Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Srikant Jayanti, Fatma Arzum Simsek-Ege, Pavan Kumar Reddy Aella
  • Publication number: 20150017772
    Abstract: A method of doping the polycrystalline channel in a vertical FLASH device is disclosed. This method uses a plurality of high energy ion implants to dope the channel at various depths of the channel. In some embodiments, these ion implants are performed at an angle offset from the normal direction, such that the implanted ions pass through at least a portion of the surrounding ONO stack. By passing through the ONO stack, the distribution of ranges reached by each ion may differ from that created by a vertical implant.
    Type: Application
    Filed: July 10, 2013
    Publication date: January 15, 2015
    Inventors: Andrew M. Waite, Jonathan Gerald England, Rajesh Prasad
  • Publication number: 20150014760
    Abstract: In an example, a device comprises a vertical stack of memory cells. Each memory cell of the vertical stack may include more than one memory element. A first vertical gate line may be coupled to a first one of the memory elements in each memory cell, and a second vertical gate line may be coupled to a second one of the memory elements in each memory cell. The first vertical gate line may be electrically isolated from the second vertical gate line.
    Type: Application
    Filed: June 25, 2014
    Publication date: January 15, 2015
    Inventor: Bruce Lynn Bateman
  • Patent number: 8927347
    Abstract: A semiconductor device includes: an n?-type base layer; a p-type base layer formed in a part of a front surface portion of the n?-type base layer; an n+-type source layer formed in a part of a front surface portion of the p-type base layer; a gate insulating film formed on the front surface of the p-type base layer between the n+-type source layer and the n?-type base layer; a gate electrode that faces the p-type base layer through the gate insulating film; a p-type column layer formed continuously from the p-type base layer in the n?-type base layer; a p+-type collector layer formed in a part of a rear surface portion of the n?-type base layer; a source electrode electrically connected to the n+-type source layer; and a drain electrode electrically connected to the n?-type base layer and to the p+-type collector layer.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: January 6, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Toshio Nakajima, Syoji Higashida
  • Patent number: 8921182
    Abstract: A method for fabricating a nonvolatile memory device includes forming a stacked structure having a plurality of interlayer dielectric layers and a plurality of sacrificial layers wherein interlayer dielectric layers and sacrificial layers are alternately stacked over a substrate, forming a first hole exposing a part of the substrate by selectively etching the stacked structure, forming a first insulation layer in the first hole, forming a second hole exposing the part of the substrate by selectively etching the first insulation layer, and forming a channel layer in the second hole.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sung-Wook Jung, Yun-Kyoung Lee, Young-Soo Ahn, Tae-Hwa Lee
  • Patent number: 8916445
    Abstract: Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench structure and deep trench structure. The method further includes forming active areas of the material separated by shallow trench isolation structures. The shallow trench isolation structures are formed by: removing the material from within the deep trench structure and portions of the shallow trench structure to form trenches; and depositing an insulator material within the trenches.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Publication number: 20140370676
    Abstract: The semiconductor device includes a vertical channel layer formed on a substrate; conductive layer patterns and insulating layer patterns alternately formed around a length of each of the vertical channel layer; and a charge storing layer pattern formed between each of the vertical channel layers and the conductive layer patterns, where each of the charge storing layer patterns is isolated by the insulating layer patterns.
    Type: Application
    Filed: September 4, 2014
    Publication date: December 18, 2014
    Inventor: Sang Bum LEE
  • Patent number: 8912053
    Abstract: A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over a substrate, forming a channel layer that is coupled with a portion of the substrate by penetrating through the stacked structure, forming a slit that penetrates through the second sacrificial layers by selectively etching the stacked structure, removing the second sacrificial layers that are exposed through the slit, forming an epitaxial layer over the channel layer exposed as a result of the removal of the second sacrificial layers, and forming a gate electrode layer filling a space from which the second sacrificial layers are removed, and a memory layer interposed between the gate electrode layer and the epitaxial layer.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hyun-Seung Yoo
  • Patent number: 8912064
    Abstract: A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventors: Yong Seok Eun, Tae Kyun Kim, Kyong Bong Rouh, Eun Shil Park
  • Publication number: 20140363938
    Abstract: A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.
    Type: Application
    Filed: August 21, 2014
    Publication date: December 11, 2014
    Inventors: Wataru SAITO, Syotaro ONO, Toshiyuki NAKA, Shunji TANIUCHI, Hiroaki YAMASHITA
  • Publication number: 20140349455
    Abstract: In a semiconductor memory device, a plurality of control gates is stacked in a first region and a second region of a substrate. A plurality of interlayer insulating layers is stacked in a portion of the second region of the substrate. Each interlayer insulating layer is formed at the same level as a corresponding one of the control gates. A plurality of sub-control gates is stacked in the first and second regions region of the substrate and interposed between the control gates and the interlayer insulating layers. A common node penetrates the interlayer insulating layers and the sub-control gates.
    Type: Application
    Filed: August 4, 2014
    Publication date: November 27, 2014
    Inventor: Young Soo AHN
  • Patent number: 8889564
    Abstract: A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, James J. Demarest, Balasubramanian S. Haran
  • Publication number: 20140332875
    Abstract: A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps.
    Type: Application
    Filed: February 19, 2014
    Publication date: November 13, 2014
    Inventors: Jung-Hwan Kim, Jun-Kyu Yang, Hun-Hyeong Lim, Jae-ho Choi, Ki-Hyun Hwang
  • Patent number: 8883596
    Abstract: A semiconductor device with vertical channel transistors and a method of fabricating the same are provided. A method of fabricating the semiconductor device includes patterning a substrate to form a trench that defines an active region, forming a sacrificial pattern in a lower region of the trench, forming a spacer on an upper sidewall of the trench, recessing a top surface of the sacrificial pattern to form a window exposing a sidewall of the active region between the spacer and the sacrificial pattern, doping a sidewall of the trench through the window to form a doped region in the active region, and forming a wiring in the trench to be connected to the doped region.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seonghwee Cheong, Mansug Kang, Joon Kim, Kihong Nam, Gyuwan Choi
  • Patent number: 8877587
    Abstract: A method for fabricating a nonvolatile memory device includes forming a stacked structure over a substrate defining a cell area and a peripheral area and having a source region, the stacked structure including interlayer dielectric layers and sacrifice layers, forming channel layers connected to the substrate through the stacked structure of the cell area, forming a first slit in the stacked structure of the cell area, forming a second slit in the stacked structure, the second slit including a first portion and a second portion, removing the sacrifice layers exposed through the first and second slits, forming conductive layers to fill spaces from which the sacrifice layers are removed, forming an insulating layer in the second slit, and forming a source contact by burying a conductive material in the first portion of the second slit having the insulating layer formed therein.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: November 4, 2014
    Assignee: SK Hynix Inc.
    Inventor: Yoo-Hyun Noh
  • Publication number: 20140308789
    Abstract: According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors.
    Type: Application
    Filed: June 25, 2014
    Publication date: October 16, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuya Kai, Yoshio Ozawa, Ryota Fujitsuka, Yoshitaka Tsunashima
  • Patent number: 8853030
    Abstract: The present invention discloses a method for production of selective growth masks using underfill dispensing and sintering. The method includes steps of: providing a sapphire substrate, growing a gallium nitride base layer on the sapphire substrate, coating a photoresist layer, performing imprint lithography, exposure and development, performing underfill dispensing, and performing sintering. The production method of the present invention can be applied in the atmosphere, and vacuum chambers as known production approaches are unnecessary. The selective growth masks produced by the method of the present invention make the growth of nanowires cylindrical and perpendicular to the gallium nitride base layer, and each nanowire is parallel to one another.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: October 7, 2014
    Assignee: Nanocrystal Asia Inc.
    Inventors: Chong-Ming Lee, Andrew Eng-Jia Lee
  • Publication number: 20140264549
    Abstract: A vertical memory device includes a substrate, a column of vertical channels on the substrate and spaced apart along a direction parallel to the substrate, respective charge storage structures on sidewalls of respective ones of the vertical channels and gate electrodes vertically spaced along the charge storage structures. The vertical memory device further includes an isolation pattern disposed adjacent the column of vertical channels and including vertical extension portions extending parallel to the vertical channels and connection portions extending between adjacent ones of the vertical extension portions.
    Type: Application
    Filed: February 27, 2014
    Publication date: September 18, 2014
    Inventor: Chang-Hyun Lee
  • Publication number: 20140252363
    Abstract: A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 11, 2014
    Inventors: Haitao Liu, Chandra V. Mouli, Krishna K. Parat, Jie Sun, Guangyu Huang
  • Patent number: 8828863
    Abstract: A method for providing metal filled features in a layer is provided. A nonconformal metal seed layer is deposited on tops, sidewalls, and bottoms of the features, wherein more seed layer is deposited on tops and bottoms of features than sidewalls. The metal seed layer are etched back on tops, sidewalls, and bottoms of the features, wherein some metal seed layer remains on tops and bottoms of the features. Deposition on the seed layer on tops of the features is suppressed. An electroless “bottom up” deposition of metal is provided to fill the features.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: September 9, 2014
    Assignee: Lam Research Corporation
    Inventors: William T. Lee, Xiaomin Bin