Utilizing Epitaxial Semiconductor Layer Grown Through An Opening In An Insulating Layer Patents (Class 438/269)
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Publication number: 20040180499Abstract: A method is described for forming an element of a microelectronic circuit. A sacrificial layer is formed on an upper surface of a support layer. The sacrificial layer is extremely thin and uniform. A height-defining layer is then formed on the sacrificial layer, whereafter the sacrificial layer is etched away so that a well-defined gap is left between an upper surface of the support layer and a lower surface of the height-defining layer. A monocrystalline semiconductor material is then selectively grown from a nucleation silicon site through the gap. The monocrystalline semiconductor material forms a monocrystalline layer having a thickness corresponding to the thickness of the original sacrificial layer.Type: ApplicationFiled: March 12, 2003Publication date: September 16, 2004Inventors: Brian S. Doyle, Anand S. Murthy, Robert S. Chau
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Patent number: 6773994Abstract: An architecture and process for forming CMOS vertical replacement gate metal oxide semiconductor field-effect transistors is disclosed. The integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second source/drain dopes regions formed in the surface. An insulating trench is formed between the first and second source/drain regions. A third doped region forming a channel of a different conductivity type than the first source/drain region is positioned over the first source/drain region. A fourth doped region is formed over the second source/drain region, having an opposite conductivity type with respect to the second source/drain region, and forming a channel region. Fifth and sixth source/drain regions are formed respectively over the third and fourth doped regions.Type: GrantFiled: December 26, 2001Date of Patent: August 10, 2004Assignee: Agere Systems Inc.Inventors: Sailesh Chittipeddi, Michael James Kelly
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Patent number: 6762098Abstract: An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions.Type: GrantFiled: May 30, 2003Date of Patent: July 13, 2004Assignee: General Semiconductor, Inc.Inventors: Fwu-Iuan Hshieh, Yan Man Tsui, Koon Chong So
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Patent number: 6756273Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.Type: GrantFiled: March 12, 2001Date of Patent: June 29, 2004Assignee: Semiconductor Components Industries, L.L.C.Inventors: Peyman Hadizad, Jina Shumate, Ali Salih
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Publication number: 20040043566Abstract: A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface structures, while adequately preventing dopants in doped glass layer from diffusing out of the doped glass layer to the surface structures and the substrate. Further, heavy water can be used during the formation of the alumina so that deuterium may be accomplished near the interface of surface structures and the substrate to enhance the performance of the device.Type: ApplicationFiled: August 29, 2002Publication date: March 4, 2004Inventors: Kunal R. Parekh, Gurtej Singh Sandhu
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Patent number: 6699754Abstract: A flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, and a source/drain region. The floating gate, disposed over the substrate and insulated from the substrate, has a plurality of hut structures. The control gate is disposed over the floating gate and insulated from the floating gate. The source/drain region is formed in the substrate. This invention further includes a method of fabricating a flash memory cell. First, a polysilicon layer and a germanium layer are successively formed over a substrate and insulated from the substrate. Subsequently, the substrate is annealed to form a germanium layer having a plurality of hut structures on the polysilicon layer to serve as a floating gate with the polysilicon layer. Next, a control gate is formed over the floating gate and insulated from the floating gate. Finally, a source/drain region is formed in the substrate.Type: GrantFiled: November 22, 2002Date of Patent: March 2, 2004Assignee: Nanya Technology CorporationInventor: Yung-Meng Huang
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Patent number: 6673646Abstract: Compound semiconductor structures and devices can be grown on patterned oxide layers deposited on silicon. The deposition of Group II-VI and Group II-V compound semiconductors on patterned wafers results in an increase in the critical thickness for lattice mismatched layers and the relief of strain energy through side walls. As a result, high crystalline quality compound semiconductor material can be grown on less expensive and more accessible substrate to more cost effectively produce semiconductor components and devices having enhanced reliability.Type: GrantFiled: February 28, 2001Date of Patent: January 6, 2004Assignee: Motorola, Inc.Inventor: Ravindranath Droopad
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Patent number: 6670244Abstract: A method is provided for fabricating a body region of a first conduction type for a vertical MOS transistor configuration in a semiconductor body such that the body region has a reduced resistivity without a corresponding reduction in the breakdown voltage of the transistor. The method includes, inter alia: performing a first implantation of a doping material of a first conduction type into the semiconductor body such that an implantation maximum of the first implantation lies within the semiconductor body set back from the channel region; and performing a second implantation of a doping material of the first conduction type such that an implantation maximum of the second implantation lies within the semiconductor body below the implantation maximum of the first implantation. The dose of the second implantation is less than the dose of the first implantation.Type: GrantFiled: August 30, 2001Date of Patent: December 30, 2003Assignee: Infineon Technologies AGInventors: Helmut Gassel, Werner Kanert, Helmut Strack, Franz Hirler, Herbert Pairitsch
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Publication number: 20030230760Abstract: The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.Type: ApplicationFiled: March 17, 2003Publication date: December 18, 2003Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won-bong Choi, Jo-won Lee, Young-hee Lee
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Patent number: 6660584Abstract: A memory cell is defined along first, second, and third orthogonal dimensions and comprises an electrically conductive word line, an electrically conductive bit line, an electrical charge storage structure, a transistor structure, and a bit line contact. The charge storage structure is conductively coupled to the bit line via the transistor structure and the bit line contact. The transistor structure is conductively coupled to the word line. The first dimension is characterized by one-half of a bit line contact feature, one word line feature, one word line space feature, and one-half of a field poly line feature. The second dimension is characterized by two one-half field oxide features and one active area feature. The first and second dimensions define a 6F2 memory cell. The bit line contact feature is characterized by a contact hole bounded by insulating side walls.Type: GrantFiled: January 24, 2002Date of Patent: December 9, 2003Inventor: Luan Tran
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Patent number: 6660590Abstract: The present invention discloses a vertical transistor wherein source/drain regions are formed by using a self-alignment method without using a latest photolithography, channels are formed via a selective epitaxial growth (hereinafter, referred to as ‘SEG’) method and gate oxide films are formed at the both ends of channels to be more efficient than devices having the same channel length, and a method of manufacturing thereof, the vertical transistor comprising: a source region formed on a semiconductor substrate; a drain region formed substantially above the source region; a vertical channel, one end of the channel being contact to the source region and the other end being contact to the drain region; and a gate electrode, formed on the substrate, surrounding the sides of the channel and the drain region, said gate electrode electrically isolated with the source region by a nitride pattern disposed therebetween, isolated with the drain region by a nitride spacer formed on the sidewalls of the draiType: GrantFiled: December 27, 2002Date of Patent: December 9, 2003Assignee: Hynix Semiconductor Inc.Inventor: Kyung Dong Yoo
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Patent number: 6660582Abstract: It is proposed when forming field-effect transistor devices in a semiconductor substrate for the overlapping region of a source-drain region that is to be provided to be formed directly as a material region, in particular with outdiffusion processes being avoided to the greatest extent. This takes place in particular by forming the connection region or buried-strap region as selectively epitaxially grown-on single-crystal, possibly doped silicon.Type: GrantFiled: October 15, 2002Date of Patent: December 9, 2003Assignee: Infineon Technologies AGInventors: Albert Birner, Matthias Goldbach
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Publication number: 20030207538Abstract: An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions.Type: ApplicationFiled: May 30, 2003Publication date: November 6, 2003Inventors: Fwu-Iuan Hshieh, Yan Man Tsui, Koon Chong So
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Patent number: 6642115Abstract: It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit comprising a first gate, a second gate, and source and drain regions adjacent the first and second gates, wherein the structure has a planar upper structure and the first gate, source and drain regions are silicided in a single self-aligned process (salicide).Type: GrantFiled: October 18, 2000Date of Patent: November 4, 2003Assignee: International Business Machines CorporationInventors: Guy M. Cohen, Hon-Sum P. Wong
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Patent number: 6639275Abstract: A semiconductor device improves the gate withstand voltage of vertical MOSFETs and raises their operation speed. The gate electrode is formed in the trench of the second semiconductor layer. The interlayer dielectric layer has the contact hole that exposes the connection portion of the gate electrode, where the connection portion is located in the trench. The conductive plug is filled in the contact hole of the interlayer dielectric layer in such a way as to contact the connection portion of the gate electrode. The wiring layer is formed on the interlayer dielectric layer in such a way as to contact the plug, resulting in the wiring layer electrically connected to the connection portion by way of the plug. There is no need to form a connection portion for the gate electrode outside of the trench, which means that the gate dielectric does not include a weak or thinner portion where dielectric breakdown is likely to occur.Type: GrantFiled: June 10, 2002Date of Patent: October 28, 2003Assignee: NEC CorporaitonInventor: Hitoshi Ninomiya
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Patent number: 6632712Abstract: A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the composite insulator stack. Selective removal of specific components of the composite insulator stack, in a specific region, allows the depth of the channel openings to be varied. A subsequent epitaxial silicon growth procedure fills the variable depth channel openings, providing the variable length, channel regions for the vertical CMOS devices.Type: GrantFiled: October 3, 2002Date of Patent: October 14, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew-Hoe Ang, Eng Hua Lim, Randall Cha, Jia Zhen Zheng, Elgin Quek, Mei Sheng Zhou, Daniel Yen
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Patent number: 6624032Abstract: A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.Type: GrantFiled: March 20, 2002Date of Patent: September 23, 2003Assignee: Intel CorporationInventors: Mohsen Alavi, Ebrahim Andideh, Scott Thompson, Mark T. Bohr
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Patent number: 6613621Abstract: Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.Type: GrantFiled: March 9, 2001Date of Patent: September 2, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Soo Uh, Kyu-Hynn Lee, Tae-Young Chung, Ki-Nam Kim, Yoo-Sang Hwang
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Publication number: 20030151092Abstract: The invention disclosed a power MOSFET with reduced snap-back and being capable increasing avalanche-breakdown current endurance, which has sequentially a drain with N+ silicon substrate, an N− epitaxial layer formed on said N+ silicon substrate, a source contact region formed of N+ doped well and P+ doped well implanted after etching in a P− well formed on said N− epitaxial layer, and a gate electrode with deposition of polysilicon above a channel between said N− epitaxial layer and N+ source contact region, said device is characterized in that: Said source contact region is formed by etching into said P− well first and implanting P+ dopant to the interface between said N− epitaxial layer and P− well, and the source contact region of said N+ well and that of said P+ well are not at the same level, by which it is possible to increase the avalanche-breakdown current endurance of the power MOSFET device.Type: ApplicationFiled: February 11, 2002Publication date: August 14, 2003Inventor: Feng-Tso Chien
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Patent number: 6599801Abstract: A method of fabricating NROM memory cell, wherein the NROM device comprises a memory array and a peripheral portion. The fabricating method comprising the steps of: providing a substrate which a oxide layer is formed thereon; forming a peripheral polysilicon layer on the oxide layer; defining a patterned peripheral polysilicon; forming an ONO layer over the substrate in the memory array and the peripheral portion; forming an array polysilicon layer on the ONO layer; and defining a patterned array polysilicon. The method of fabricating NROM memory cell according to the invention can solve the problems of top oxide loss, touch between nitride and polysilicon, and BD over-diffusion.Type: GrantFiled: June 25, 2002Date of Patent: July 29, 2003Assignee: Macronix International Co., Ltd.Inventors: Kent Kuohua Chang, Erh-Kun Lai
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Publication number: 20030139012Abstract: In a method for manufacturing a semiconductor device of the present invention, a portion of a first epitaxial layer formed in a trench in a silicon substrate is removed by vapor phase etching using a halogenated compound or hydrogen. In this removing process, the portion of the first epitaxial layer is removed at a predetermined temperature higher than that during epitaxial growth of the first epitaxial layer and at a predetermined pressure higher than that during epitaxial growth of the first epitaxial layer. Therefore, stress that would otherwise be concentrated at a bottom portion of the trench is relaxed because rearrangement of the silicon atoms increases.Type: ApplicationFiled: January 21, 2003Publication date: July 24, 2003Inventors: Shoichi Yamauchi, Nobuhiro Tsuji
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Patent number: 6593620Abstract: An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions.Type: GrantFiled: October 6, 2000Date of Patent: July 15, 2003Assignee: General Semiconductor, Inc.Inventors: Fwu-Iuan Hshieh, Yan Man Tsui, Koon Chong So
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Patent number: 6589835Abstract: A process of manufacturing a flash memory device having a tunnel oxide layer with high reliability, low defect and interface trap by using semi-atmospheric pressure chemical vapor deposition (SPACVD) and tetra-ethyl-ortho-silicate (TEOS) reactant. SAPCVD is performed accompanied with a reaction temperature between about 600° C. and about 750° C. and a reaction pressure between about 340 Torr and about 500 Torr to react TEOS and oxygen.Type: GrantFiled: March 22, 2001Date of Patent: July 8, 2003Assignee: Macronix International Co., Ltd.Inventor: Kent Kuohua Chang
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Patent number: 6521497Abstract: A method of manufacturing a trenched field effect transistor that includes a heavy body structure. The method includes forming a plurality of trenches into a semiconductor substrate having dopants of a first conductivity type, wherein the gate electrode of the transistor is formed. A doped well having dopants of a second conductivity type is formed into the substrate and between the trenches. Source regions having dopants of the first conductivity type are formed inside the doped well adjacent to and on opposite sides of the trenches. A heavy body region having dopants of the second conductivity type is formed inside each doped well and at a depth that is shallower than the doped well. The heavy body is formed in a manner that makes an abrupt junction between the heavy body and the well. In one embodiment, the abrupt junction is formed by a dobule implant process.Type: GrantFiled: May 9, 2001Date of Patent: February 18, 2003Assignee: Fairchild Semiconductor CorporationInventor: Brian Sze-Ki Mo
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Patent number: 6521508Abstract: There is disclosed a method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon (SEG) process. The method includes forming a nitride film at a predetermined in a semiconductor substrate region except for the region in which a contact plug will be formed, forming an USG film on the entire surface of the substrate in which the nitride film is formed by chemical enhanced vapor deposition method or a plasma method, etching the USG film by reactive ion etch method to expose the surface of silicon in the structure, and forming a contact plug by performing in-situ process while performing selective epitaxial growth method for the silicon film exposed through the contact hole in the structure.Type: GrantFiled: November 27, 2000Date of Patent: February 18, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Woo Seock Cheong, Eui Beom Roh
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Patent number: 6503799Abstract: There is provided a method of forming an element isolation structure that can maintain its element isolation capability even with the progress of miniaturization of semiconductor elements. Through thermal processing in a nitrogen atmosphere at 900° C., a non single-crystal silicon film (80) is crystallized into single-crystal form by epitaxial growth on the main surface of a substrate, thereby to form an epitaxial silicon film (85). The epitaxial silicon film (85) is then planarized by CMP to expose the upper surface of an element isolation insulating film (50). This completes the element isolation insulating film (50) having a two-level protruding shape.Type: GrantFiled: November 26, 2001Date of Patent: January 7, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuyuki Horita, Takashi Kuroi, Shuuichi Ueno
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Patent number: 6495421Abstract: A method is described of manufacturing a semiconductor material having a zone (200) with p-conductivity type and n-conductivity type regions with dopant concentrations and dimensions such that, when the n- and p-conductivity type regions are depleted of free charge carriers the space charge per unit area of the regions balances at least to the extent that the resulting electric field is lower than that at which avalanche breakdown would occur in the area. The method starts with a semiconductor body having adjacent a first major surface (10b) a first semiconductor region (2) of one conductivity type. A mask (3, 4, 5) is provided on the first major surface, having at least one mask area masking a part (2a) of the first region. At least a part of the unmasked first region (2) is then removed to provide at least one opening (7) in the first region.Type: GrantFiled: December 14, 2000Date of Patent: December 17, 2002Assignee: Koninklijke Philips Electronics N.V.Inventor: JiKui Luo
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Patent number: 6492232Abstract: An n-channel device (10) and a p-channel device (11) are formed from a single epitaxial silicon layer (60,61). During the deposition of the single epitaxial silicon layer (60,61), dopants are added to the epitaxial reaction chamber and subsequently changed to define a drain region (24,33), a channel region (27,34), and a source region (30,35). The dopant concentration is modified during the formation of the channel region (27,34) to create a doping profile (50). The doping profile (50) has a first profile (51) that is constant and a second profile (52) that changes.Type: GrantFiled: May 2, 2000Date of Patent: December 10, 2002Assignee: Motorola, Inc.Inventors: Zhirong Tang, Heemyong Park, Jenny M. Ford
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Patent number: 6486017Abstract: A new method is provided for the creation of a horizontal spiral inductor over the surface of a silicon substrate. A first layer of dielectric is deposited over the surface of the substrate, this first layer of dielectric is patterned and etched creation islands of first dielectric material overlying the surface of the substrate, the islands of first dielectric material align with coils of a thereover to be created spiral inductor. The openings created in the layer of dielectric by the patterning and etching of the first layer of dielectric are filled by selective deposition of epitaxial silicon therein. Second and third layers of dielectric are successively deposited over the surface of the first layer of dielectric. A spiral horizontal inductor is then created over the surface of the third layer of dielectric.Type: GrantFiled: June 4, 2002Date of Patent: November 26, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Purakh Raj Verma, Sanford Chu, Johnny Chew, Sia Choon Beng
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Patent number: 6479354Abstract: A method of forming a semiconductor device with a SEG layer and isolating elements formed in the device includes forming an insulating layer for isolating elements on a silicon substrate. An open area is formed in the insulating layer to expose the surface of the silicon substrate by selectively etching the insulating layer. The open area in the insulating layer includes an inclined side wall at a positive angle of inclination. An epitaxial layer is selectively grown to have a top surface lower than the surface of the insulating layer, using the silicon exposed in the open area as a seed. A sacrificial oxide layer is formed on the surface of the silicon of the epitaxial growth, and the sacrificial oxide layer is then removed.Type: GrantFiled: March 28, 2001Date of Patent: November 12, 2002Assignee: Samsung Electronics Co., Ltd.Inventor: Hong Bae Moon
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Patent number: 6455377Abstract: A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench.Type: GrantFiled: January 19, 2001Date of Patent: September 24, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying Keung Leung, Yelehanka Ramachandramurthy Pradeep
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Patent number: 6436778Abstract: A process for fabricating a semiconductor device 20 that includes providing semiconductor substrate 28 having a core region 24 and a peripheral gate region 26. The semiconductor substrate 28 has at least one shallow trench isolation region 30 and at least one nitrogen-contaminated region 36 in the peripheral gate region 26. A tunnel oxide layer 34 overlies the semiconductor substrate 28 and a first polysilicon layer 38 overlies the tunnel oxide layer 34 in the core region 24. An ONO layer 40 overlies the first polysilicon layer 38 in the core region 24. The process further includes growing a sacrificial oxide layer 42 overlying the nitrogen-contaminated region 36 in the peripheral gate region 26, wherein oxygen from within the sacrificial oxide layer 42 diffuses into the nitrogen-contaminated region 36 and forms silicon dioxide.Type: GrantFiled: June 12, 2001Date of Patent: August 20, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Hao Fang, Yue-song He
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Patent number: 6432775Abstract: A semiconductor device includes a first region of semiconductor material, which is doped to a first concentration with a dopant of a first conductivity type. A gate trench formed within the first region has sides and a bottom. A drain access trench is also formed within the first region, which also has sides and a bottom. A second region of semiconductor material is located within the first region and adjacent to and near the bottom of the gate trench. The second region extends to a location adjacent to and near the bottom of the drain access trench. The second region is of the first conductivity type and has a higher dopant concentration than the first region. A gate electrode is formed within the gate trench. A layer of gate dielectric material insulates the gate electrode from the first and second regions. A drain region of semiconductor material is located within the drain access trench. The drain region is of a first conductivity type and has a higher dopant concentration than the first region.Type: GrantFiled: June 1, 2001Date of Patent: August 13, 2002Assignee: General Semiconductor, Inc.Inventor: Richard A. Blanchard
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Patent number: 6426259Abstract: For fabricating a vertical field effect transistor on a semiconductor substrate, a first layer of dielectric material is deposited on the semiconductor substrate. A layer of metal is then deposited on the first layer of dielectric material, and a second layer of dielectric material is deposited on the layer of metal. A channel opening is etched through the second layer of dielectric material, the layer of metal, and the first layer of dielectric material. A source and drain dopant is implanted through the channel opening and into the semiconductor substrate to form a drain region of the vertical field effect transistor in the semiconductor substrate. Metal oxide is then formed at any exposed surface of the layer of metal on sidewalls of the channel opening in a thermal oxidation process to form a gate dielectric of the vertical field effect transistor.Type: GrantFiled: November 15, 2000Date of Patent: July 30, 2002Assignee: Advanced Micro Devices, Inc.Inventor: Bin Yu
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Patent number: 6420750Abstract: A method and structure for forming an integrated circuit memory device includes forming a trench conductor in a trench, forming an isolation collar along a perimeter of an upper portion of the trench conductor, forming supporting spacers above the isolation collar, forming a sacrificial layer between the supporting spacers along an upper surface of the trench conductor, forming an insulator above the sacrificial layer, forming a gate conductor above the insulator, removing the sacrificial layer to form a gap between the insulator and the trench conductor, wherein the supporting spacers maintain a relative position of the gate conductor, the insulator and the trench conductor and forming a conductive strap in the gap.Type: GrantFiled: August 9, 2000Date of Patent: July 16, 2002Assignee: International Business Machines CorporationInventors: Ramachandra Divakaruni, Jack A. Mandelman
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Patent number: 6395597Abstract: A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.Type: GrantFiled: September 27, 1999Date of Patent: May 28, 2002Assignee: Micron Technology, Inc.Inventor: Wendell P. Noble
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Patent number: 6387758Abstract: For fabricating a vertical field effect transistor on a semiconductor substrate, a bottom layer of doped insulating material is deposited on the semiconductor substrate. A layer of dummy material is deposited on the bottom layer of doped insulating material. A top layer of doped insulating material is deposited on the layer of dummy material. An opening is etched through the top layer of doped insulating material, the layer of dummy material, and the bottom layer of doped insulating material. A semiconductor fill is contained within the opening. The semiconductor fill has at least one sidewall with a top portion of the sidewall abutting the top layer of doped insulating material, a middle portion of the sidewall abutting the layer of dummy material, and a bottom portion of the sidewall abutting the bottom layer of doped insulating material. The layer of dummy material is etched away such that the middle portion of the sidewall of the semiconductor fill is exposed.Type: GrantFiled: March 26, 2001Date of Patent: May 14, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Allen S. Yu, Chau M. Ho
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Patent number: 6372583Abstract: A method for making a semiconductor device. In that method, source and drain regions are epitaxially grown on a first part of a substrate. After a gate oxide is formed on a second part of the substrate, an etched polysilicon layer is formed on the gate oxide.Type: GrantFiled: February 9, 2000Date of Patent: April 16, 2002Assignee: Intel CorporationInventor: Sunit Tyagi
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Patent number: 6365465Abstract: A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.Type: GrantFiled: March 19, 1999Date of Patent: April 2, 2002Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Guy M. Cohen, Yuan Taur, Hon-Sum P. Wong
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Patent number: 6362048Abstract: A method for manufacturing the floating gate of a flash memory. First, a substrate is provided. A gate oxide layer, a polysilicon layer and a silicon nitride layer are sequentially formed over the substrate. Gate position is defined and then the silicon nitride layer above the gate position is removed. Th exposed polysilicon layer is oxidized to from a floating gate oxide layer. A buffer layer is formed over the silicon nitride layer and the floating gate oxide layer. A first spacer is formed on the sidewall of the buffer layer. Thereafter, a second spacer is formed. Using the second spacer as a mask, the exposed floating gate oxide layer is removed. The buffer layer, the first spacer and the second spacer above the polysilicon layer and the floating gate oxide layer are removed. Finally, the polysilicon layer not covered by the floating gate oxide layer is removed to form a complete floating gate of a flash memory.Type: GrantFiled: April 4, 2001Date of Patent: March 26, 2002Assignee: Winbond Electronics Corp.Inventor: Shui-Chin Huang
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Patent number: 6359309Abstract: A MOSFET and IGBT are described that exhibit high breakdown voltage together with low on-resistance. This is achieved by providing an N type shunt that extends from the N+ drain (for power MOSFETs) or P+ emitter (for IGBTs), through the N− region to a short distance below the gate oxide. To manufacture such a shunt, an epi wafer with N−epitaxy is first provided on top of an N+ (for power MOSFET) or P+ (for IGBT) layer. Through a suitable mask (contact or freestanding) on the top surface, the wafer is then subjected to bombardment by protons or deuterons. Because of ion transmutation doping, a region of N type material forms wherever the surface is not masked. By controlling the energies of the ions, this region is caused to extend below the wafer's surface so as to just contact the N+ or P+ layer or even to go through it.Type: GrantFiled: November 16, 2000Date of Patent: March 19, 2002Assignee: Industrial Technology Research InstituteInventors: Chungpin Liao, Dar-Chang Juang
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Patent number: 6355528Abstract: A narrow groove is formed over a substrate. To form such a narrow groove, a first material is formed over a substrate, the first material having a sidewall. A spacer is formed abutting the sidewall. Subsequently a second material is formed adjacent to the spacer. The spacer is removed leaving a groove between the first material and second material. In one embodiment, the groove is filled with material for a narrow feature, such as a gate, and the first material and second material are removed. As a result a gate or other narrow feature is formed having a length defined by the width of a spacer. In another embodiment, an implant is performed through the small groove, resulting in a small localized implant.Type: GrantFiled: October 26, 1999Date of Patent: March 12, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Emi Ishida, Scott Luning, Tim Thurgate
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Publication number: 20020015898Abstract: A method for producing identifying elements for identifying the specification of a MASK ROM, which can easily accompany the standard process of MASK ROM. Also disclosed a method for identifying a MASK ROM, which can identify the code specification of the MASK ROM produced using simple electrical tests before the product is delivered, thereby achieving high efficiency and low error rate.Type: ApplicationFiled: February 13, 2001Publication date: February 7, 2002Applicant: Mosel Vitelic Inc.Inventors: Kuan-Chou Sung, Chih-Ta Teng, Kuo-Chung Wu
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Patent number: 6303437Abstract: A non-volatile semiconductor device structure and method for low power applications comprises a trenched floating gate and corner dopings and further includes a well junction region with a source region and a drain region therein, and includes a channel region, an inter-gate dielectric layer, and a control gate. The trenched floating gate is formed in a trench etched into the semiconductor substrate and has a top surface which is substantially planar with a top surface of the semiconductor substrate. The source and drain regions are laterally separated by the trench in which the trenched floating gate is formed and have a depth which is approximately less than the depth of the trench. The channel region is formed beneath a bottom surface of the trench and is doped to form a depletion type channel region.Type: GrantFiled: August 4, 2000Date of Patent: October 16, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Yowjuang W. Liu
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Publication number: 20010026006Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method of forming an integrated circuit include forming a trench in a silicon wafer. A trench wall of the trench has a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a <110> direction. One method of the present invention provides for forming an integrated circuit.Type: ApplicationFiled: May 8, 2001Publication date: October 4, 2001Applicant: Micron Technology, Inc.Inventors: Wendell P. Noble, Leonard Forbes, Alan R. Reinberg
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Patent number: 6284600Abstract: A predetermined species such as nitrogen is placed at an interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device to minimize degradation of such an interface by minimizing formation of interface defects during program or erase operations of the flash memory device. The predetermined species such as nitrogen is implanted into a bit line junction of the flash memory device. A thermal process is performed that heats up the semiconductor wafer such that the predetermined species such as nitrogen implanted within the semiconductor wafer thermally drifts to the interface between the bit line junction and the control dielectric structure during the thermal process. The predetermined species such as nitrogen at the interface minimizes formation of interface defects and thus degradation of the interface with time during the program or erase operations of the flash memory device.Type: GrantFiled: July 3, 2000Date of Patent: September 4, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Yider Wu, Mark T. Ramsbey, Chi Chang, Yu Sun, Tuan Duc Pham, Jean Y. Yang
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Publication number: 20010017392Abstract: MOSFET comprising:Type: ApplicationFiled: March 22, 2001Publication date: August 30, 2001Applicant: International Business Machines Corporation.Inventors: James Hartfiel Comfort, Young Hoon Lee, Yaun Taur, Samuel Jonas Wind, Hom-Sum Philip Wong
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Publication number: 20010016387Abstract: A method of fabricating field emission arrays which employs a single mask to define emitter tips and their corresponding resistors. Column lines may also be defined without requiring the use of an additional mask. The method includes disposing substantially mutually parallel conductive lines onto a substrate of the field emission array. The conductive lines may be patterned from a layer of conductive material or selectively deposited onto the substrate. One or more material layers from which the emitter tips and resistors will be defined are disposed onto the conductive lines and the regions of substrate exposed between adjacent conductive lines. The exposed surface of the layer or layers of emitter tip and resistor material or materials may be planarized. A mask is disposed over the substantially planar surface.Type: ApplicationFiled: March 27, 2001Publication date: August 23, 2001Inventor: Ammar Derraa
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Publication number: 20010014504Abstract: A method of forming a semiconductor device with a SEG layer and isolating elements formed in the device includes forming an insulating layer for isolating elements on a silicon substrate. An open area is formed in the insulating layer to expose the surface of the silicon substrate by selectively etching the insulating layer. The open area in the insulating layer includes an inclined side wall at a positive angle of inclination. An epitaxial layer is selectively grown to have a top surface lower than the surface of the insulating layer, using the silicon exposed in the open area as a seed. A sacrificial oxide layer is formed on the surface of the silicon of the epitaxial growth, and the sacrificial oxide layer is then removed.Type: ApplicationFiled: March 28, 2001Publication date: August 16, 2001Inventor: Hong Bae Moon
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Patent number: 6271087Abstract: A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A first photoresist contact mask is deposited, processed, and used to etch core contact and peripheral local interconnect openings. The first photoresist contact mask is removed. A second photoresist contact mask is deposited, processed, and used to etch the multi-layer structures to form local interconnect openings. The second photoresist contact mask is removed.Type: GrantFiled: October 10, 2000Date of Patent: August 7, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Hiroyuki Kinoshita, YongZhong Hu, Yu Sun, Fei Wang