Abstract: A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate. A low voltage device is also formed in the substrate. The high voltage device includes a drift region, a gate, a source, a drain, and a mitigation region. The mitigation region has a second conductive type, and is formed in the drift region between the gate and drain. The mitigation region is formed by a process step which also forms a lightly doped drain (LDD) region in the low voltage device.

Abstract: Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

Abstract: A field effect transistor including a substrate which includes, a fin structure, the fin structure having a top surface. The field effect transistor further including an isolation in the substrate and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the fin structure and the isolation structure. The S/D recess cavity includes a lower portion, the lower portion further includes a first strained layer, a first dielectric film and a second dielectric film, wherein the first strained layer is disposed between the first dielectric film and the second dielectric film. The S/D recess cavity further includes an upper portion including a second strained layer overlying the first strained layer, wherein a ratio of a height of the upper portion to a height of the lower portion ranges from about 0.8 to about 1.2.

Abstract: A method of fabricating a corner transistor is described. An isolation structure is formed in a substrate to define an active region. A treating process is performed to make the substrate in the active region have sharp corners at top edges thereof. The substrate in the active region is covered by a gate dielectric layer. A gate conductor is formed over the gate dielectric layer. A source region and a drain region are formed in the substrate beside the gate conductor.

Abstract: Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

Abstract: One method disclosed herein includes forming first, second and third gate stacks, wherein one of the gate stacks is an isolation stack positioned above an isolation structure and each of the gate stacks is comprised of three layers of hard mask material positioned above a layer of gate electrode material. The method also involves forming sidewall spacers proximate the second gate stack while the first and isolation gate stacks are masked, forming sidewall spacers proximate the first gate stack while the second and isolation gate stacks are masked, forming a polish stop layer between the plurality of gate stacks, performing another etching process on an etch stop layer, a layer of spacer material, and the second layer of hard mask material positioned above or proximate the isolation gate stack and performing a chemical mechanical polishing process to remove material positioned above an upper surface of the polish stop layer.

Abstract: A static random access memory fabrication method includes forming a gate stack on a substrate, forming isolating spacers adjacent the gate stack, the isolating spacers and gate stack having a gate length, forming a source and drain region adjacent the gate stack, which generates an effective gate length, wherein the source and drain regions are formed from a low extension dose implant that varies a difference between the gate length and the effective gate length.

Abstract: A semiconductor device includes an isolation layer formed on a semiconductor substrate; an active region defined by the isolation layer; at least one gate line formed to overlap with the active region; at least one first active tab formed on a first interface of the active region which overlaps with the gate line; and a first gate tab formed on a second interface facing away from the first interface in such a way as to project from the gate line.

Abstract: A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors.

Abstract: A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.

Abstract: A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.

Abstract: An integrated circuit includes a substrate, a first semiconductor device, a second semiconductor device and an interlayer dielectric layer. At least one isolation structure has been formed in the he substrate so as to separate the substrate into a first active region and a second active region. The first semiconductor device disposed on the first active region of the substrate includes a first gate insulating layer and a poly-silicon gate stacked on the substrate sequentially. The second semiconductor device disposed on the second active region of the substrate includes a second gate insulating layer and a metal gate stacked on the substrate sequentially. The material of the second gate insulating layer is different from that of the first gate insulating layer. The thickness of the metal gate is greater than that of the poly-silicon gate. The interlayer dielectric layer is disposed on the substrate and covering the first semiconductor device.

Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

Abstract: An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The integrated circuit can further include a doped structure having an opposite conductivity type as compared to the buried conductive region, lying closer to an opposing surface than to a primary surface of the semiconductor layer, and being electrically connected to the buried conductive region. The integrated circuit can also include a well region that includes a portion of the semiconductor layer, wherein the portion overlies the doped structure and has a lower dopant concentration as compared to the doped structure. In other embodiment, the doped structure can be spaced apart from the buried conductive region.

Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor pillar extending from the semiconductor substrate, the semiconductor pillar comprising a first region, a second region, and a third region, the second region positioned between the first region and the third region, the third region positioned between the second region and the semiconductor substrate, immediately adjacent regions having different conductivity types, a first gate pattern disposed on the second region with a first insulating layer therebetween, and a second gate pattern disposed on the third region, wherein the second region is ohmically connected to the substrate by the second gate pattern.

Abstract: In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench.

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Abstract: An electrostatic discharge protection device is disclosed. The electrostatic discharge protection device preferably includes a first transistor, a second transistor, and an electrostatic discharge clamping circuit. The first transistor includes a first drain electrically connected to an input/output pin of a chip, a first source electrically connected to a first voltage input pin of the chip, and a first gate. The first drain is preferably an internally shrunk drain. The second transistor includes a second drain electrically connected to the input/output pin of the chip, a second source electrically connected to a second voltage input pin and a second gate. The electrostatic discharge clamping circuit is electrically connected to the first voltage input pin and the second voltage input pin.

Abstract: A semiconductor device including a first insulation film including a first opening reaching a diffusion region of a transistor; a first barrier metal over the diffused region in the first opening; a first conduction layer formed over the first barrier metal in the first opening and formed of a first conductor; a second barrier metal formed over the first conduction layer in the first opening; a second conduction layer formed over the second barrier metal in the first opening and formed of a second conductor; a third barrier metal formed over the first gate electrode in the second opening; a fourth barrier metal formed in the second opening and contacting with the third barrier metal; and a third conduction layer formed of the second conductor contacting with the fourth barrier metal in the second opening.

Abstract: A semiconductor device comprises an active region having an upper portion and a sidewall portion which are protruded from the top surface of a device isolation region, and a silicide film disposed in the upper portion and the sidewall portion of the active region, thereby effectively reducing resistance in a source/drain region of the semiconductor device. As a result, the entire resistance of the semiconductor device comprising a fin-type gate can be reduced to improve characteristics of the semiconductor device.

Abstract: A Schottky barrier field effect transistor with a carbon-containing insulation layer and a method for fabricating the same are provided. The Schottky barrier field effect transistor comprises: a substrate; a gate stack formed on the substrate; a metal source and a metal drain formed in the substrate on both sides of the gate stack respectively; and the carbon-containing insulation layer formed between the substrate and the metal source and between the substrate and the metal drain respectively, in which a material of the carbon-containing insulation layer is organic molecular chains containing an alkyl group.

Abstract: A method for fabricating a recessed channel access transistor device is provided. A semiconductor substrate having thereon a recess is provided. A gate dielectric layer is formed in the recess. A gate material layer is then deposited into the recess. A dielectric cap layer is formed on the gate material layer. The dielectric cap layer and the gate material layer are etched to form a gate pattern. A liner layer is then formed on the gate pattern. A spacer is formed on the liner layer on each sidewall of the gate pattern. The liner layer not masked by the spacer is etched to form an undercut recess that exposes a portion of the gate material layer. The spacer is then removed. The exposed portion of the gate material layer in the undercut recess is oxidized to form an insulation block therein.

Abstract: Semiconductor devices and methods of making semiconductor devices are provided. Boron diffusion into source/drain regions is restricted by a vertical and lateral confinement area formed on the surfaces of the source/drain regions. In an aspect, a silicon-carbon layer formed on the surface of the channel region suppresses boron diffusion toward a first source/drain region and toward at least a second source/drain region.

Abstract: A method for manufacturing a semiconductor includes: forming an isolation region defining first, second and third active regions; implanting first impurity ions of a first conductivity type to form first, second and third wells; implanting second impurity ions of the first conductivity type to form first and second channel regions; implanting second impurity ions of a second conductivity to form a first drain region, such that a portion of the first channel region is overlapped with the first drain region; forming first, second and third gate electrodes, the first gate electrode superposing a portion of the first drain region and covering one lateral end of the first channel region; forming first insulating side wall spacers and a second insulating side wall spacer on a side wall of the first gate electrode; and implanting fourth impurity ions of the second conductivity type to form second drain/source regions.

Abstract: A method of forming a device is presented. The method includes providing a substrate having a device region which includes a source region, a gate and a drain region defined thereon. The method also includes implanting the gate. The gate comprises one or more doped portions with different dopant concentrations. A source and a drain are formed in the source region and drain region. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate.

Abstract: Technology is described herein for manufacturing a three-dimensional 3D stacked memory structure having multiple layers of single crystal silicon or other semiconductor. The multiple layers of single crystal semiconductor are suitable for implementing multiple levels of high performance memory cells.

Abstract: A method includes forming a gate stack including a gate electrode on a first semiconductor fin. The gate electrode includes a portion over and aligned to a middle portion of the first semiconductor fin. A second semiconductor fin is on a side of the gate electrode, and does not extend to under the gate electrode. The first and the second semiconductor fins are spaced apart from, and parallel to, each other. An end portion of the first semiconductor fin and the second semiconductor fin are etched. An epitaxy is performed to form an epitaxy region, which includes a first portion extending into a first space left by the etched first end portion of the first semiconductor fin, and a second portion extending into a second space left by the etched second semiconductor fin. A first source/drain region is formed in the epitaxy region.

Abstract: A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming spacers adjoining sidewalls of the gate stacks, wherein at least one of the spacers extends beyond an edge the isolation feature. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.

Abstract: A lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) with a high drain-to-body breakdown voltage (Vb) incorporates gate structure extensions on opposing sides of a drain drift region. The extensions are tapered such that a distance between each extension and the drift region increases linearly from one end adjacent to the channel region to another end adjacent to the drain region. In one embodiment, these extensions can extend vertically through the isolation region that surrounds the LEDMOSFET. In another embodiment, the extensions can sit atop the isolation region. In either case, the extensions create a strong essentially uniform horizontal electric field profile within the drain drift. Also disclosed are a method for forming the LEDMOSFET with a specific Vb by defining the dimensions of the extensions and a program storage device for designing the LEDMOSFET to have a specific Vb.

Abstract: A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.

Abstract: A method of forming a semiconductor device may include forming a metal layer on a silicon portion of a substrate, and reacting the metal layer with the silicon portion to form a metal silicide. After reacting the metal layer, unreacted residue of the metal layer may be removed using an electrolyzed sulfuric acid solution. More particularly, a volume of sulfuric acid in the electrolyzed sulfuric acid solution may be in the range of about 70% to about 95% of the total volume of the electrolyzed sulfuric acid solution, a concentration of oxidant in the electrolyzed acid solution may be in the range of about 7 g/L to about 25 g/L, and a temperature of the electrolyzed sulfuric acid solution may be in the range of about 130 degrees C. to about 180 degrees C.

Abstract: Disclosed is a solid-state imaging device which includes a plurality of pixels in an arrangement, each of the pixels including a photoelectric conversion element, pixel transistors including a transfer transistor, and a floating diffusion region, in which the channel width of transfer gate of the transfer transistor is formed to be larger on a side of the floating diffusion region than on a side of the photoelectric conversion element.

Abstract: In an embodiment of the invention, a method of forming an NMOS (n-type metal-oxide semiconductor) transistor is disclosed. A dual mask pattern is used to ion-implant source/drain regions of the NMOS transistor. The first mask allows first doses of As (arsenic), P (phosphorous) and N (Nitrogen) to be ion-implanted. After these doses are ion-implanted, a high temperature (900-1050 C) spike anneal is performed to activate the formed source/drains. A second mask allows a second dose of phosphorus to be implanted in the source/drain regions. The second dose of the phosphorus is typically higher than the first dose of phosphorus. The second dose of phosphorus lowers the Rsd (resistance of the source and drain regions) and dopes n-type poly-silicon blocks.

Abstract: Disclosed herein is a nitride based semiconductor device, including: a substrate; a nitride based semiconductor layer having a lower nitride based semiconductor layer and an upper nitride based semiconductor layer on the substrate; an isolation area including an interface between the lower nitride based semiconductor layer and the upper nitride based semiconductor layer; and drain electrodes, source electrode, and gate electrodes formed on the upper nitride based semiconductor layer. According to preferred embodiments of the present invention, in the nitride based semiconductor device, by using the isolation area including the interface between the lower nitride based semiconductor layer and the upper nitride based semiconductor layer, problems of parasitic capacitance and leakage current are solved, and as a result, a switching speed can be improved through a gate pad.

Abstract: A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.

Abstract: A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.

Abstract: There is provided a method for manufacturing a semiconductor wafer, comprising: performing heating so that metals dissolve into semiconductors of the wafer to form a semiconductor-metal compound; and performing cooling so that the formed semiconductor-metal compound retrogradely melt to form a mixture of the metals and the semiconductors. According to embodiments of the present invention, it is possible to achieve wafers of a high purity applicable to the semiconductor manufacture.

Abstract: A MOS transistor (60, 62) is provided. The structure of the transistor (60, 62) includes: a semiconductor substrate (10), a channel area (20, 24), source/drain regions (22, 26), a gate (30, 32), a gate insulating layer (11), a shallow trench isolation region (12), a passive layer (50, 52), and holes (40, 42) formed with a certain distance to the gate insulating layer (11). Wherein both the shapes of the holes (40, 42) and the Young's modulus' difference between the material in the holes (40, 42) and that around the holes (40, 42) contribute to the stress concentration effect, thus the stress in the channel area (20, 24) is enhanced. The structure of the transistor (60, 62) can greatly reduce the stress attenuation during the transmission from stress resource to the sensitive region, and concentrate the stress in the sensitive region. The structure can be involved in large size device, especially.

Abstract: A MOS P-N junction diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. The method for manufacturing such diode device includes several ion-implanting steps. After the gate structure is formed by isotropic etching using a patterned photo-resist layer as a mask, an ion-implanting step is performed using the patterned photo-resist layer as a mask to form a deeper doped sub-region. Then, another ion-implanting step is performed using the gate structure as a mask to form a shallower doped sub-region between the gate structure and the deeper doped sub-region. The formed MOS P-N junction diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.

Abstract: In one embodiment, a method of providing a semiconductor device is provided, in which instead of forming isolation regions before the formation of the semiconductor devices, the isolation regions are formed after the semiconductor devices. In one embodiment, the method includes forming a semiconductor device on a semiconductor substrate. A placeholder dielectric is formed on a portion of a first surface of the substrate adjacent to the semiconductor device. A trench is etched into the substrate from a second surface of the substrate that is opposite the first surface of the substrate, wherein the trench terminates on the placeholder dielectric. The trench is filled with a dielectric material.

Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

Abstract: A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.

Abstract: An LDMOS device includes a second conduction type buried layer, a first conduction type drain extension region configured to be formed on and/or over a region of the second conduction type buried layer, a second conduction type drain extension region configured to be formed in a partial region of the first conduction type drain extension region, a first conduction type body, a first guard ring configured to be formed around the second conduction type drain extension region and configured to include a second conduction type impurity layer, and a second guard ring configured to be formed around the first guard ring and configured to include a high-voltage second conduction type well and a second conduction type impurity layer. Further, the second conduction type impurity layer of the first guard ring and the second conduction type impurity layer of the second guard ring operate as an isolation.

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming an epitaxial layer by growing a crystalline layer using a semiconductor source gas in a reaction chamber, and by etching the crystalline layer using an etching gas in the reaction chamber.

Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.

Abstract: A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of a substrate to enhance carrier mobility and upgrade the device performance. In an embodiment, the improved formation method is achieved using an etching process to redistribute the strained material by removing at least a portion of the corner to be located in the cavity.

Abstract: A semiconductor device includes a first device isolation insulating film defining a first region, a first conductive layer of a first conductivity type formed in the first region, a semiconductor layer formed above the semiconductor substrate and including a second conductive layer of the first conductivity type connected to the first conductive layer and a third conductive layer of the first conductivity type connected to the first conductive layer, a second device isolation insulating film formed in the semiconductor layer and isolating the second conductive layer and the third conductive layer from each other, a gate insulating film formed above the second conductive layer, and a gate electrode formed above the gate insulating film and electrically connected to the first conductive layer via the third conductive layer.

Abstract: A semiconductor device includes a substrate (e.g., a P-type semiconductor substrate), and an isolation region formed in the substrate to isolate an element formation region from the other region. The semiconductor device also includes a gate electrode formed over the element formation region. The gate electrode extends over each of first and second regions of the isolation region opposing each other with the element formation region interposed therebetween. The semiconductor device further includes a pair of diffusion regions (e.g., N-type diffusion regions) formed in the element formation region so as to be spaced apart from each other in a channel length direction with reference to the gate electrode. At least a portion of each of upper surfaces of the first and second regions is depressed to a depth of not less than 5% of a channel width to be located under an upper surface of the element formation region. In each of resultant depressions also, a portion of the gate electrode is present.

Abstract: Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.