Utilizing Gate Sidewall Structure Patents (Class 438/303)
  • Patent number: 11594603
    Abstract: An exemplary device includes a channel layer, a first epitaxial source/drain feature, and a second epitaxial source/drain feature disposed over a substrate. The channel layer is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. A metal gate is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The metal gate is disposed over and physically contacts at least two sides of the channel layer. A source/drain contact is disposed over the first epitaxial source/drain feature. A doped crystalline semiconductor layer, such as a gallium-doped crystalline germanium layer, is disposed between the first epitaxial source/drain feature and the source/drain contact. The doped crystalline semiconductor layer is disposed over and physically contacts at least two sides of the first epitaxial source/drain feature.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Georgios Vellianitis, Blandine Duriez
  • Patent number: 11527613
    Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: December 13, 2022
    Assignee: INTEL CORPORATION
    Inventors: Aaron Lilak, Patrick Keys, Sean Ma, Stephen Cea, Rishabh Mehandru
  • Patent number: 11495609
    Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: November 8, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
  • Patent number: 11482596
    Abstract: A semiconductor device includes a channel, a first source/drain structure on a first side surface of the channel, a second source/drain structure on a second side surface of the channel, a gate structure surrounding the channel, an inner spacer layer on a side surface of the gate structure, and an outer spacer layer on an outer surface of the inner spacer layer. The first source/drain structure includes a first source/drain layer on the channel and a second source/drain layer on the first source/drain layer, and on a plane of the semiconductor device that passes through the channel, at least one of a first boundary line of the first source/drain layer in contact with the second source/drain layer and a second boundary line of the first source/drain layer in contact with the channel may be convex, extending toward the channel.
    Type: Grant
    Filed: March 21, 2021
    Date of Patent: October 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinbum Kim, Seokhoon Kim, Kwanheum Lee, Choeun Lee, Sujin Jung
  • Patent number: 11476344
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: October 18, 2022
    Assignee: Daedalus Prime LLC
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
  • Patent number: 11466406
    Abstract: A cellulose-silicon oxide composite superhydrophobic material and a preparation method thereof are disclosed. In the method, cellulose substrates with different surface topographies are pretreated by a low-temperature plasma, and then a first silicon oxide layer is deposited on the cellulose substrate by a low-temperature plasma-enhanced chemical vapor deposition method, then modified by a low-temperature plasma, and finally a second silicon oxide layer is deposited thereon, thereby preparing a micro-nano structured superhydrophobic surface on the cellulose substrate, to obtain a cellulose-silicon oxide composite superhydrophobic material, which is an environmentally friendly bio-based hydrophobic material.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: October 11, 2022
    Assignee: GUANGXI UNIVERSITY
    Inventors: Chongxing Huang, Yuan Zhao, Hui Zhao, Lijie Huang, Yangfan Xu, Qingshan Duan, Cuicui Li, Hongxia Su, Jian Wang, Linyun Zhang
  • Patent number: 11462679
    Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hoon Bak, Myoung-Su Son, Jae-Chul Shim, Gwan-Hyeob Koh, Yoon-Jong Song
  • Patent number: 11462407
    Abstract: An etching method includes: forming a second film on a workpiece target including a processing target film, a layer including a plurality of convex portions formed on the processing target film, and a first film that covers the plurality of convex portions and the processing target film exposed between the plurality of convex portions; etching the second film in a state where the second film remains on a portion of the first film that covers a side surface of each of the plurality of convex portions; and etching the first film in a state where the second film remains on the portion of the first film that covers the side surface of each of the plurality of convex portions, thereby exposing a top portion of each of the plurality of convex portions and the processing target film between the plurality of convex portions.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: October 4, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusuke Yanagisawa, Yusuke Takino
  • Patent number: 11444175
    Abstract: Semiconductor devices and methods of forming the same are provided. An example method includes providing a workpiece including a first dummy gate stack and a second dummy gate stack in a first area of the workpiece, a third dummy gate stack and a fourth dummy gate stack in a second area of the workpiece, a hard mask layer over each of the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack. The method further includes depositing a photoresist (PR) layer over the workpiece to form a first PR layer portion over the first area and a second PR layer portion over the second area; and selectively forming a first opening through the second PR layer portion over the third dummy gate stack and a second opening through the second PR layer portion over the fourth dummy gate stack.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Hsin Yang, Jung-Chi Jeng, Ru-Shang Hsiao
  • Patent number: 11431340
    Abstract: This disclosure relates to a dual power supply detection circuit including first and second input stage field effect transistors, an inverter stage, a feedback stage field effect transistor, and first and second compensation circuits. The inverter stage includes a complimentary pair of transistors, and the complementary pair of transistors includes an NMOS transistor and a PMOS transistor configured and arranged so that gate lengths of the PMOS and NMOS transistors are different. The disclosure also relates to an integrated circuit including a dual power supply detection circuit.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: August 30, 2022
    Assignee: Nexperia B.V.
    Inventors: Geethanadh Asam, Robert Mossel, Walter Luis Tercariol
  • Patent number: 11423987
    Abstract: A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a fine programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: August 23, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Hongtao Liu, Ying Huang, Wenzhe Wei, Song Min Jiang, Dejia Huang, Wen Qiang Chen
  • Patent number: 11417740
    Abstract: Embodiments disclosed herein relate generally to methods for forming recesses in epitaxial source/drain regions for forming conductive features. In some embodiments, the recesses are formed in a two-step etching process including an anisotropic etch to form a vertical opening and an isotropic etch to expand an end portion of the vertical opening laterally and vertically. The recesses can have increased contact area between the source/drain region and the conductive feature, and can enable reduced resistance therebetween.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yu-Lien Huang
  • Patent number: 11404537
    Abstract: A semiconductor device includes a substrate, a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, and a spacer formed adjacent the gate and over the substrate. The spacer includes a void filled with air to prevent leakage of charge to and from the gate, thereby reducing data loss and providing better memory retention. The reduction in charge leakage results from reduced parasitic capacitances, fringing capacitances, and overlap capacitances due to the low dielectric constant of air relative to other spacer materials. The spacer can include multiple layers such as oxide and nitride layers. In some embodiments, the semiconductor device is a multiple-time programmable (MTP) memory device.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Gulbagh Singh, Kun-Tsang Chuang, Hsin-Chi Chen
  • Patent number: 11393754
    Abstract: Contact over active gate (COAG) structures with etch stop layers, and methods of fabricating contact over active gate (COAG) structures using etch stop layers, are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A first dielectric etch stop layer is directly on and continuous over the trench insulating layers and the gate insulating layers. A second dielectric etch stop layer is directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer. An interlayer dielectric material is on the second dielectric etch stop layer.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Atul Madhavan, Nicholas J. Kybert, Mohit K. Haran, Hiten Kothari
  • Patent number: 11387361
    Abstract: A method for forming a semiconductor structure includes: forming a first gate structure in a predetermined low-potential region of a substrate and a second gate structure in a predetermined high-potential region of the substrate; sequentially forming a first dielectric layer and a second dielectric layer covering the first gate structure and the second gate structure; forming a portion of a third dielectric layer along sidewalls of the second gate structure and on the second dielectric layer; and etching the first dielectric layer and the second dielectric layer with the portion of the third dielectric layer as an etching hard mask to form a first composite spacer covering sidewalls of the first gate structure, and a second composite spacer covering the sidewalls of the second gate structure, wherein a width of the first composite spacer is less than a width of the second composite spacer.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: July 12, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chin-Hsiu Huang, Tse-Hsiao Liu, Pao-Hao Chiu, Chih-Cherng Liao, Ching-Yi Hsu
  • Patent number: 11329137
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: May 10, 2022
    Inventors: Naoto Umezawa, Satoru Yamada, Junsoo Kim, Honglae Park, Chunhyung Chung
  • Patent number: 11309185
    Abstract: A method includes forming a gate trench over a semiconductor fin. The gate trench includes an upper portion surrounded by first gate spacers and a lower portion surrounded by second gate spacers and the first gate spacers. The method includes forming a metal gate in the lower portion of the gate trench. The metal gate is disposed over a first portion of a gate dielectric layer. The method includes depositing a metal material in the gate trench to form a gate electrode overlaying the metal gate in the lower portion of the gate trench, while keeping sidewalls of the first gate spacers and upper surfaces of the second gate spacer overlaid by a second portion of the gate dielectric layer. The method includes removing the second portion of the gate dielectric layer, while remaining the gate electrode substantially intact.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Jian-Jou Lian, Po-Yuan Wang, Chieh-Wei Chen
  • Patent number: 11264396
    Abstract: Various embodiments of the present application are directed to an IC device and associated forming methods. In some embodiments, a memory region and a logic region are integrated in a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices disposed on a plurality of logic sub-regions of the logic region. A first logic device is disposed on a first upper surface of a first logic sub-region. A second logic device is disposed on a second upper surface of a second logic sub-region. A third logic device is disposed on a third upper surface of a third logic sub-region. Heights of the first, second, and third upper surfaces of the logic sub-regions monotonically decrease. By arranging logic devices on multiple recessed positions of the substrate, design flexibility is improved and devices with multiple operation voltages are better suited.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Cheng Wu, Li-Feng Teng
  • Patent number: 11227828
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a capacitor structure, and a conductive contact. The semiconductor substrate has at least one semiconductor fin thereon. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer and a first metal layer disposed on the ferroelectric layer. The capacitor structure is sandwiched between the conductive contact and the gate structure.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Ho, Chun-Chieh Lu, Chih-Sheng Chang
  • Patent number: 11037833
    Abstract: A method for forming a semiconductor device is provided. A dielectric layer is formed on a substrate. First and second gate trenches are formed in the dielectric layer. First and second spacers are disposed in the first and the second gate trenches, respectively. A patterned photoresist is formed on the dielectric layer. The patterned photoresist masks the first region and exposes the second region. Multiple cycles of spacer trimming process are performed to trim a sidewall profile of the second spacer. Each cycle comprises a step of oxygen stripping and a successive step of chemical oxide removal. The patterned photoresist is then removed to reveal the first region.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 15, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yao-Hsien Chung, Hao-Hsuan Chang, Ting-An Chien, Bin-Siang Tsai
  • Patent number: 11031484
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to differential silicide structures and methods of manufacture. The structure includes: a substrate; a gate structure comprising a silicided gate region; and source and drain regions adjacent to the gate structure and comprising S/D silicided regions having a differential thickness compared to the silicided gate region.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 8, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: George R. Mulfinger, Judson R. Holt, Mark Raymond
  • Patent number: 10944002
    Abstract: Some embodiments include an integrated assembly with a semiconductor base having a horizontally-extending upper surface, and having a recessed region. A transistor gate is supported by the semiconductor base. The transistor gate has a first segment over the horizontally-extending upper surface, and has a second segment over the recessed region. The first segment has a first vertically-extending surface along an outer edge. The second segment has a ledge along an edge of the recessed region. The ledge has an upper surface which is lower than the horizontally-extending upper surface. The second segment has a second vertically-extending surface extending upwardly from an inner portion of the ledge. A first spacer is along the first vertically-extending surface. A second spacer is along the second vertically-extending surface. The second spacer has a bottom edge beneath the horizontally-extending upper surface of the base.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Masahiro Yokomichi
  • Patent number: 10930764
    Abstract: A semiconductor device herein includes doped extension regions for silicon and silicon germanium nanowires. The nanowires can be selectively grown and recessed into a gate spacer. The semiconductor device can include a gate structure including the gate spacer; the nanowire or channel extending through the gate structure such that an end of the channel is recessed within a recess in said gate spacer; an extension region in contact with the end of the channel within the recess, the extension region being formed of an extension material having a different composition than a channel material of the channel such that a strain is provided in the channel; and a source-drain contact in contact with the extension region and adjacent to the gate structure.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: February 23, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara Tapily, Jeffrey Smith, Nihar Mohanty, Anton J. deVilliers
  • Patent number: 10825867
    Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Stephen H. Tang, Stephen W. Russell
  • Patent number: 10770354
    Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10714578
    Abstract: Embodiments disclosed herein relate generally to methods for forming recesses in epitaxial source/drain regions for forming conductive features. In some embodiments, the recesses are formed in a two-step etching process including an anisotropic etch to form a vertical opening and an isotropic etch to expand an end portion of the vertical opening laterally and vertically. The recesses can have increased contact area between the source/drain region and the conductive feature, and can enable reduced resistance therebetween.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 10700170
    Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei
  • Patent number: 10699955
    Abstract: In one aspect, a method of forming a local interconnect structure includes the steps of: forming a BOX SOI wafer having a fully depleted seed layer between a first BOX layer and a second BOX layer, and an active layer over the second BOX layer; forming at least one STI region in the active layer having an STI oxide; forming at least one trench that extends through the STI oxide and the second BOX layer down to the seed layer, wherein the trench has a footprint and a location such that a portion of the STI oxide remains lining sidewalls of the trench; and growing an epitaxial material in the trench using the seed layer as a template for the growth, wherein the epitaxial material is doped and serves as the local interconnect structure which is buried in the double BOX SOI wafer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 30, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 10644130
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain. An inner spacer is disposed at least partially over the gate electrode. An outer spacer is disposed adjacent to a sidewall of the gate electrode.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yuan Yang, Jen-Pan Wang
  • Patent number: 10636904
    Abstract: The present disclosure, in some embodiments, relates to a transistor device having a field plate. The transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers are arranged over the gate electrode, and a field plate is arranged over the one or more dielectric layers. The field plate extends from a first outermost sidewall that is directly over an upper surface of the gate electrode to a second outermost sidewall that is between the gate electrode and the drain region and that extends to below the upper surface of the gate electrode.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Liang Chou, Dah-Chuen Ho, Hui-Ting Lu, Po-Chih Su, Pei-Lun Wang, Yu-Chang Jong
  • Patent number: 10559468
    Abstract: Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon carbonitride material, silicon oxycarbide material, silicon carbon-oxynitride, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: February 11, 2020
    Assignee: Lam Research Corporation
    Inventors: Reza Arghavani, Samantha Tan, Bhadri N. Varadarajan, Adrien LaVoie, Ananda K. Banerji, Jun Qian, Shankar Swaminathan
  • Patent number: 10559500
    Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: February 11, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Maekawa, Tatsuyoshi Mihara
  • Patent number: 10490663
    Abstract: The present disclosure provides N-type fin field-effect transistors. An N-type fin field-effect transistor includes a semiconductor substrate; at least one fin having a first side surface and a second side surface formed over the semiconductor substrate; a gate structure crossing over the fin and formed over the semiconductor substrate; and a source region and a drain region respectively formed on top of the fin at two sides of the gate structure by an ion implantation process on one of the first side surface and the second side surface of the fin at two sides of the gate structure and a thermal annealing process to diffuse doping ions into the other of the first side surface and the second side surface of the fin.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 26, 2019
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Yong Li
  • Patent number: 10468325
    Abstract: A radio frequency integrated circuit (RFIC) device and methods for fabricating same are disclosed. The RFIC device includes: a first semiconductor layer having a first surface, a second surface parallel to the first surface and a thickness of smaller than 3 ?m; a first dielectric layer on the first surface of the first semiconductor layer; a semiconductor component within the first semiconductor layer and the first dielectric layer; a second dielectric layer on the second surface of the first semiconductor layer, the second dielectric layer having a thickness of smaller than 1 ?m; and a sheet-like heat sink formed on a surface of the first dielectric layer opposite to the first semiconductor layer for dissipating heat from the semiconductor component. Efficient dissipation of heat from an RF transistor to a certain extent can be achieved by the RFIC device.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: November 5, 2019
    Assignee: SHANGHAI JADIC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaochuan Wang
  • Patent number: 10431495
    Abstract: A technique relates to a semiconductor device. A first trench silicide (TS) is coupled to a first source or drain (S/D). A second TS is coupled to a second S/D, and a gate metal is separated from the first and second TS. A trench is formed above and on sides of the gate metal. A local connection metal is formed in the trench such that the gate metal is coupled to the first TS and the second TS. A local connection cap is formed on top of the local connection metal.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: October 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, Junli Wang, John H. Zhang
  • Patent number: 10332746
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chih-Tang Peng, Jei Ming Chen, Shu-Yi Wang
  • Patent number: 10269711
    Abstract: A semiconductor device includes a substrate, a group of devices, a plurality of sidewall spacers and a contact structure. The group of the devices is arranged over the substrate. The plurality of sidewall spacers are over lateral surfaces of the group of the devices. The sidewall spacers abut one another and cooperatively define an enclosure between the devices. The contact structure is arranged between the devices in the enclosure. The contact structure is electrically connected to one device of the group of the devices.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Chyi Liu, Chia-Shiung Tsai
  • Patent number: 10199232
    Abstract: Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Shin-Chi Chen, Jiunn-Hsiung Liao, Yu-Tsung Lai
  • Patent number: 10176997
    Abstract: Forming a semiconductor structure, including epitaxially growing a first source drain region between a first fin in an N-FET region and a second fin in a P-FET region, forming a shallow trench isolation region separating the N-FET region and the P-FET region, conformally forming an insulator on exposed surfaces of the semiconductor structure, conformally forming a work function metal layer on exposed surfaces, conformally forming a liner, conformally forming an organic planarization layer, forming a titanium nitride layer, patterning a photo resist mask, forming an first opening between the N-FET region and the P-FET region, wherein a top surface of a portion of the liner is exposed at a bottom of the first opening, removing the portion of the liner between the N-FET region and the P-FET region and removing a portion of the work function metal layer between the N-FET region and the P-FET region.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ekmini A. De Silva, Indira Seshadri, Stuart A. Sieg, Wenyu Xu
  • Patent number: 10157990
    Abstract: A semiconductor device is provided, which includes a substrate, a shallow trench isolation (STI), a gate dielectric structure, a capping structure and a gate structure. The STI is in the substrate and defines an active area of the substrate. The gate dielectric structure is on the active area. The capping structure is adjacent to the gate dielectric structure and at edges of the active area. The gate structure is on the gate dielectric structure and the capping structure. An equivalent oxide thickness of the capping structure is substantially greater than an equivalent oxide thickness of the gate dielectric structure.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ming Wang, Fang-Ting Kuo
  • Patent number: 10158000
    Abstract: Systems and methods are provided for fabricating a semiconductor structure including sidewall spacers. An example semiconductor structure includes: a gate structure, a first sidewall spacer, and a second sidewall spacer. The gate structure is formed over a substrate. The first sidewall spacer is adjacent to the gate structure, a top part of the first sidewall spacer including a first dielectric material, a bottom part of the first sidewall spacer including a second dielectric material. The second sidewall spacer is adjacent to the first sidewall spacer, the second sidewall spacer including a third dielectric material.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-Yang Lee, Chia-Chun Lan
  • Patent number: 10079305
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The device may include an active pattern protruding from a substrate, gate structures crossing the active pattern, and a source/drain region provided between adjacent ones of the gate structures. The source/drain region may include a source/drain epitaxial layer in a recessed region, which is formed in the active pattern between the adjacent ones of the gate structures. Further, an impurity diffusion region may be provided in the active pattern to enclose the source/drain epitaxial layer along inner surfaces of the recessed region.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 18, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byeongchan Lee, Nam-Kyu Kim, JinBum Kim, Kwan Heum Lee, Choeun Lee, Sujin Jung
  • Patent number: 9960084
    Abstract: The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: May 1, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Wen-Jiun Shen, Yu-Ren Wang
  • Patent number: 9944692
    Abstract: The present invention a method for producing a human immunoglobulin G (IgG) antibody using a prime-boost regime in a Bone Marrow Liver Thymic (BLT) mouse.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: April 17, 2018
    Assignee: Trustees of Dartmouth College
    Inventors: William G. North, Steven N. Fiering
  • Patent number: 9859386
    Abstract: An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer, forming a first dielectric layer adjacent and over the first gate, etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsai-Jung Ho, Kuang-Yuan Hsu, Pei-Ren Jeng
  • Patent number: 9711612
    Abstract: A semiconductor device structure and a method for fabricating the same. A method for fabricating semiconductor device structure includes forming gate lines on a semiconductor substrate; forming gate sidewall spacers surrounding the gate lines; forming respective source/drain regions in the semiconductor substrate and on either side of the respective gate lines; forming conductive sidewall spacers surrounding the gate sidewall spacers; and cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions, in which the cut gate lines are electrically isolated gates, and the cut conductive sidewall spacers are electrically isolated lower contacts. The method is applicable to the manufacture of contacts in integrated circuits.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: July 18, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang, Haizhou Yin
  • Patent number: 9659981
    Abstract: A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-Fann Ting, Chih-Yu Lai, Cheng-Ta Wu, Yeur-Luen Tu, Ching-Chun Wang
  • Patent number: 9595478
    Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: March 14, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wenhui Wang, Ryan Ryoung-han Kim, Linus Jang, Jason Cantone, Lei Sun, Seowoo Nam
  • Patent number: 9449834
    Abstract: A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into ? form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a ?-shaped recess with a cuspate bottom.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: September 20, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Qingsong Wei, Wei Lu, Wuping Liu, Yonggen He
  • Patent number: 9419103
    Abstract: Field-effect transistor and method of fabrication are provided for, for instance, providing a gate structure disposed over a substrate. The fabricating method further includes forming a source and drain region within the substrate separated by a channel region, the channel region underlying, at least partially, the gate structure. Forming further includes implanting at least one dopant at a pre-selected temperature into the source and drain region to facilitate increasing a concentration of the at least one dopant within the source and drain region, where the implanting of the at least one dopant at the pre-selected temperature facilitates reducing contact resistance of the source and drain region and increasing charge carrier mobility through the channel region.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: August 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Mitsuhiro Togo