Utilizing Gate Sidewall Structure Patents (Class 438/303)
  • Patent number: 10714578
    Abstract: Embodiments disclosed herein relate generally to methods for forming recesses in epitaxial source/drain regions for forming conductive features. In some embodiments, the recesses are formed in a two-step etching process including an anisotropic etch to form a vertical opening and an isotropic etch to expand an end portion of the vertical opening laterally and vertically. The recesses can have increased contact area between the source/drain region and the conductive feature, and can enable reduced resistance therebetween.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 10699955
    Abstract: In one aspect, a method of forming a local interconnect structure includes the steps of: forming a BOX SOI wafer having a fully depleted seed layer between a first BOX layer and a second BOX layer, and an active layer over the second BOX layer; forming at least one STI region in the active layer having an STI oxide; forming at least one trench that extends through the STI oxide and the second BOX layer down to the seed layer, wherein the trench has a footprint and a location such that a portion of the STI oxide remains lining sidewalls of the trench; and growing an epitaxial material in the trench using the seed layer as a template for the growth, wherein the epitaxial material is doped and serves as the local interconnect structure which is buried in the double BOX SOI wafer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 30, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 10700170
    Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei
  • Patent number: 10644130
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain. An inner spacer is disposed at least partially over the gate electrode. An outer spacer is disposed adjacent to a sidewall of the gate electrode.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yuan Yang, Jen-Pan Wang
  • Patent number: 10636904
    Abstract: The present disclosure, in some embodiments, relates to a transistor device having a field plate. The transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers are arranged over the gate electrode, and a field plate is arranged over the one or more dielectric layers. The field plate extends from a first outermost sidewall that is directly over an upper surface of the gate electrode to a second outermost sidewall that is between the gate electrode and the drain region and that extends to below the upper surface of the gate electrode.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Liang Chou, Dah-Chuen Ho, Hui-Ting Lu, Po-Chih Su, Pei-Lun Wang, Yu-Chang Jong
  • Patent number: 10559500
    Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: February 11, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Maekawa, Tatsuyoshi Mihara
  • Patent number: 10559468
    Abstract: Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon carbonitride material, silicon oxycarbide material, silicon carbon-oxynitride, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: February 11, 2020
    Assignee: Lam Research Corporation
    Inventors: Reza Arghavani, Samantha Tan, Bhadri N. Varadarajan, Adrien LaVoie, Ananda K. Banerji, Jun Qian, Shankar Swaminathan
  • Patent number: 10490663
    Abstract: The present disclosure provides N-type fin field-effect transistors. An N-type fin field-effect transistor includes a semiconductor substrate; at least one fin having a first side surface and a second side surface formed over the semiconductor substrate; a gate structure crossing over the fin and formed over the semiconductor substrate; and a source region and a drain region respectively formed on top of the fin at two sides of the gate structure by an ion implantation process on one of the first side surface and the second side surface of the fin at two sides of the gate structure and a thermal annealing process to diffuse doping ions into the other of the first side surface and the second side surface of the fin.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 26, 2019
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Yong Li
  • Patent number: 10468325
    Abstract: A radio frequency integrated circuit (RFIC) device and methods for fabricating same are disclosed. The RFIC device includes: a first semiconductor layer having a first surface, a second surface parallel to the first surface and a thickness of smaller than 3 ?m; a first dielectric layer on the first surface of the first semiconductor layer; a semiconductor component within the first semiconductor layer and the first dielectric layer; a second dielectric layer on the second surface of the first semiconductor layer, the second dielectric layer having a thickness of smaller than 1 ?m; and a sheet-like heat sink formed on a surface of the first dielectric layer opposite to the first semiconductor layer for dissipating heat from the semiconductor component. Efficient dissipation of heat from an RF transistor to a certain extent can be achieved by the RFIC device.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: November 5, 2019
    Assignee: SHANGHAI JADIC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaochuan Wang
  • Patent number: 10431495
    Abstract: A technique relates to a semiconductor device. A first trench silicide (TS) is coupled to a first source or drain (S/D). A second TS is coupled to a second S/D, and a gate metal is separated from the first and second TS. A trench is formed above and on sides of the gate metal. A local connection metal is formed in the trench such that the gate metal is coupled to the first TS and the second TS. A local connection cap is formed on top of the local connection metal.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: October 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, Junli Wang, John H. Zhang
  • Patent number: 10332746
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chih-Tang Peng, Jei Ming Chen, Shu-Yi Wang
  • Patent number: 10269711
    Abstract: A semiconductor device includes a substrate, a group of devices, a plurality of sidewall spacers and a contact structure. The group of the devices is arranged over the substrate. The plurality of sidewall spacers are over lateral surfaces of the group of the devices. The sidewall spacers abut one another and cooperatively define an enclosure between the devices. The contact structure is arranged between the devices in the enclosure. The contact structure is electrically connected to one device of the group of the devices.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Chyi Liu, Chia-Shiung Tsai
  • Patent number: 10199232
    Abstract: Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Shin-Chi Chen, Jiunn-Hsiung Liao, Yu-Tsung Lai
  • Patent number: 10176997
    Abstract: Forming a semiconductor structure, including epitaxially growing a first source drain region between a first fin in an N-FET region and a second fin in a P-FET region, forming a shallow trench isolation region separating the N-FET region and the P-FET region, conformally forming an insulator on exposed surfaces of the semiconductor structure, conformally forming a work function metal layer on exposed surfaces, conformally forming a liner, conformally forming an organic planarization layer, forming a titanium nitride layer, patterning a photo resist mask, forming an first opening between the N-FET region and the P-FET region, wherein a top surface of a portion of the liner is exposed at a bottom of the first opening, removing the portion of the liner between the N-FET region and the P-FET region and removing a portion of the work function metal layer between the N-FET region and the P-FET region.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ekmini A. De Silva, Indira Seshadri, Stuart A. Sieg, Wenyu Xu
  • Patent number: 10158000
    Abstract: Systems and methods are provided for fabricating a semiconductor structure including sidewall spacers. An example semiconductor structure includes: a gate structure, a first sidewall spacer, and a second sidewall spacer. The gate structure is formed over a substrate. The first sidewall spacer is adjacent to the gate structure, a top part of the first sidewall spacer including a first dielectric material, a bottom part of the first sidewall spacer including a second dielectric material. The second sidewall spacer is adjacent to the first sidewall spacer, the second sidewall spacer including a third dielectric material.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-Yang Lee, Chia-Chun Lan
  • Patent number: 10157990
    Abstract: A semiconductor device is provided, which includes a substrate, a shallow trench isolation (STI), a gate dielectric structure, a capping structure and a gate structure. The STI is in the substrate and defines an active area of the substrate. The gate dielectric structure is on the active area. The capping structure is adjacent to the gate dielectric structure and at edges of the active area. The gate structure is on the gate dielectric structure and the capping structure. An equivalent oxide thickness of the capping structure is substantially greater than an equivalent oxide thickness of the gate dielectric structure.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ming Wang, Fang-Ting Kuo
  • Patent number: 10079305
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The device may include an active pattern protruding from a substrate, gate structures crossing the active pattern, and a source/drain region provided between adjacent ones of the gate structures. The source/drain region may include a source/drain epitaxial layer in a recessed region, which is formed in the active pattern between the adjacent ones of the gate structures. Further, an impurity diffusion region may be provided in the active pattern to enclose the source/drain epitaxial layer along inner surfaces of the recessed region.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 18, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byeongchan Lee, Nam-Kyu Kim, JinBum Kim, Kwan Heum Lee, Choeun Lee, Sujin Jung
  • Patent number: 9960084
    Abstract: The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: May 1, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Wen-Jiun Shen, Yu-Ren Wang
  • Patent number: 9944692
    Abstract: The present invention a method for producing a human immunoglobulin G (IgG) antibody using a prime-boost regime in a Bone Marrow Liver Thymic (BLT) mouse.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: April 17, 2018
    Assignee: Trustees of Dartmouth College
    Inventors: William G. North, Steven N. Fiering
  • Patent number: 9859386
    Abstract: An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer, forming a first dielectric layer adjacent and over the first gate, etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsai-Jung Ho, Kuang-Yuan Hsu, Pei-Ren Jeng
  • Patent number: 9711612
    Abstract: A semiconductor device structure and a method for fabricating the same. A method for fabricating semiconductor device structure includes forming gate lines on a semiconductor substrate; forming gate sidewall spacers surrounding the gate lines; forming respective source/drain regions in the semiconductor substrate and on either side of the respective gate lines; forming conductive sidewall spacers surrounding the gate sidewall spacers; and cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions, in which the cut gate lines are electrically isolated gates, and the cut conductive sidewall spacers are electrically isolated lower contacts. The method is applicable to the manufacture of contacts in integrated circuits.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: July 18, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang, Haizhou Yin
  • Patent number: 9659981
    Abstract: A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-Fann Ting, Chih-Yu Lai, Cheng-Ta Wu, Yeur-Luen Tu, Ching-Chun Wang
  • Patent number: 9595478
    Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: March 14, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wenhui Wang, Ryan Ryoung-han Kim, Linus Jang, Jason Cantone, Lei Sun, Seowoo Nam
  • Patent number: 9449834
    Abstract: A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into ? form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a ?-shaped recess with a cuspate bottom.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: September 20, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Qingsong Wei, Wei Lu, Wuping Liu, Yonggen He
  • Patent number: 9419103
    Abstract: Field-effect transistor and method of fabrication are provided for, for instance, providing a gate structure disposed over a substrate. The fabricating method further includes forming a source and drain region within the substrate separated by a channel region, the channel region underlying, at least partially, the gate structure. Forming further includes implanting at least one dopant at a pre-selected temperature into the source and drain region to facilitate increasing a concentration of the at least one dopant within the source and drain region, where the implanting of the at least one dopant at the pre-selected temperature facilitates reducing contact resistance of the source and drain region and increasing charge carrier mobility through the channel region.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: August 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Mitsuhiro Togo
  • Patent number: 9287262
    Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
  • Patent number: 9287277
    Abstract: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: March 15, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Tatsuya Sugimachi, Satoshi Torii
  • Patent number: 9287397
    Abstract: A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers, selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes remains after the selective etch, and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: March 15, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: GuoHao Cao, Guangli Yang, Yang Zhou, GangNing Wang
  • Patent number: 9263275
    Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a semiconductor substrate and a interlayer dielectric (ILD) over the semiconductor substrate. A gate structure is formed within the ILD and disposed on the semiconductor substrate, wherein the gate structure includes a high-k dielectric material layer and a metal gate stack. One or more portions of a protection layer are formed over the gate stack, and a contact etch stop layer is formed over the ILD and over the one or more portions of the protection layer. The metal gate stack includes aluminum and the protection layer includes aluminum oxide.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jinn-Kwei Liang, Chung-Ren Sun, Shiu-Ko Jang Jiang, Hsiang-Hsiang Ko
  • Patent number: 9263345
    Abstract: A transistor structure with improved device performance, and a method for forming the same is provided. The transistor structure is an SOI (silicon-on-insulator) transistor. In one embodiment, a silicon layer over the oxide layer is a relatively uniform film and in another embodiment, the silicon layer over the oxide layer is a silicon fin. The transistor devices include source/drain structures formed of a strain material that extends through the silicon layer, through the oxide layer and into the underlying substrate which may be silicon. The source/drain structures also include portions that extend above the upper surface of the silicon layer thereby providing an increased volume of the strain layer to provide added carrier mobility and higher performance.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ken-Ichi Goto, Dhanyakumar Mahaveer Sathaiya, Ching-Chang Wu, Tzer-Min Shen
  • Patent number: 9218976
    Abstract: When forming field-effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art, which may overcome this problem. However, formation of a fully silicided gate is hindered by the fact that silicidation of the source and drain regions and of the gate electrode are normally performed simultaneously. The claimed method proposes two consecutive silicidation processes which are decoupled with respect to each other. During the first silicidation process, a metal silicide is formed forming an interface with the source and drain regions and without affecting the gate electrode. During the second silicidation, a metal silicide layer having an interface with the gate electrode is formed, without affecting the transistor source and drain regions.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: December 22, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Gerd Zschaetzsch, Jan Hoentschel
  • Patent number: 9214557
    Abstract: Devices and methods for forming a device are presented. A substrate prepared with a device region is provided. A fin is formed in the device region. The fin includes top and bottom portions. An amorphous isolation buffer is formed at least in the bottom fin portion, leaving the top fin portion crystalline. The top fin portion serves as a body of a fin type transistor.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: December 15, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Dexter Xueming Tan, Eng Huat Toh
  • Patent number: 9209033
    Abstract: A gas cluster ion beam (GCIB) etching method for adjusting a fin height in finFET devices is described. The method includes providing a substrate having a fin structure and a gap-fill material layer completely overlying the fin structure and filling the regions between each fin of the fin structure, wherein each fin includes a cap layer formed on a top surface thereof, and planarizing the gap-fill material layer until the cap layer is exposed on at least one fin of the fin structure. Additionally, the method includes setting a target fin height for the fin structure, wherein the fin height measured from an interface between the cap layer and the fin structure, and exposing the substrate to a GCIB and recessing the gap-fill material layer relative to the cap layer until the target fin height is substantially achieved.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: December 8, 2015
    Assignee: TEL Epion Inc.
    Inventors: Luis Fernandez, Edmund Burke
  • Patent number: 9209344
    Abstract: The present invention provides a method of forming a doping region. A substrate is provided, and a poly-silicon layer is formed on the substrate. A silicon oxide layer is formed on the poly-silicon layer. An implant process is performed to form a doping region in the poly-silicon layer. The present invention further provides a method for forming a MOS.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: December 8, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao Su, Hang Hu, Hong Liao
  • Patent number: 9202891
    Abstract: The semiconductor device includes a semiconductor substrate, a plurality of source regions formed in a stripe shape on the semiconductor substrate, a plurality of gate electrodes formed in a stripe shape between a plurality of the stripe shaped source regions on the semiconductor substrate, an insulating film for covering the source regions and the gate electrodes, the insulating film including a contact hole for partly exposing the source regions in a part of a predetermined region with respect to a longitudinal direction of the source regions; and a source electrode formed on the insulating film and electrically connected to the source region via the contact hole.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: December 1, 2015
    Assignee: ROHM CO., LTD.
    Inventor: Kenichi Yoshimochi
  • Patent number: 9178037
    Abstract: An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: November 3, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chet Vernon Lenox, Seung-Chul Song, Brian K. Kirkpatrick
  • Patent number: 9177803
    Abstract: The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Javorka, Juergen Faul, Ralf Richter, Jan Hoentschel
  • Patent number: 9171928
    Abstract: Provided is a semiconductor device with improved performance and production yield. Insulating films IL2 and IL3 are formed over a semiconductor substrate in that order to cover a gate electrode. Then, the insulating films IL3 and IL2 are etched back to form sidewall spacers including the insulating films IL2 and IL3 over sidewalls of the gate electrode. The source/drain region is formed in the semiconductor substrate by ion implantation using the gate electrode and the sidewall spacer as a mask. Then, the sidewall spacers are isotropically etched on conditions where the insulating film IL2 is less likely to be etched than the third insulating film IL3 to thereby decrease the thickness of the sidewall spacer. Thereafter, a reaction layer between the metal and the source/drain region is formed over the source/drain region.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 27, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tamotsu Ogata, Toshifumi Iwasaki
  • Patent number: 9171952
    Abstract: A low gate-to-drain capacitance merged finFET and methods of manufacture are disclosed. The method includes forming a plurality of fins on a substrate. The method further includes forming at least one dummy gate structure intersecting the plurality of fins. The method further includes forming a gap between sidewalls of the fins and an insulator material, which exposes portions of the substrate. The method further includes merging the fins together with semiconductor material formed within the gaps and over the insulator material.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Terence B. Hook, Edward J. Nowak
  • Patent number: 9142402
    Abstract: A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material. The first, the second, and the third materials may include a hard mask, a semiconductor material, and an oxide, respectively.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: September 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ling Liou, Chih-Tang Peng, Pei-Ren Jeng, Hao-Ming Lien, Tze-Liang Lee
  • Patent number: 9142649
    Abstract: A metal gate process comprises the steps of providing a substrate, forming a dummy gate on said substrate, forming dummy spacers on at least one of the surrounding sidewalls of said dummy gate, forming a source and a drain respectively in said substrate at both sides of said dummy gate, performing a replacement metal gate process to replace said dummy gate with a metal gate, removing said dummy spacers, and forming low-K spacers to replace said dummy spacers.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: September 22, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Patent number: 9136181
    Abstract: A method for manufacturing a semiconductor device, comprising: defining an active region on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric on the interfacial oxide layer; forming a first metal gate layer on the high-K gate dielectric; forming a dummy gate layer on the first metal gate layer; patterning the dummy gate layer, the first metal gate layer, the high-K gate dielectric and the interfacial oxide layer to form a gate stack structure; forming a gate spacer surrounding the gate stack structure; forming S/D regions for NMOS and PMOS respectively; depositing interlayer dielectric and planarization by CMP to expose the surface of dummy gate layer; removing the dummy gate layer so as to form a gate opening; implanting dopant ions into the first metal gate layer; forming a second metal gate layer on the first metal gate layer so as to fill the gate opening; and performing annealing, so that the dopant ions diffuse a
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: September 15, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Huilong Zhu, Gaobo Xu, Huajie Zhou, Dapeng Chen
  • Patent number: 9129796
    Abstract: A process of forming an integrated circuit including an MOS transistor, in which a pre-metal deposition cleanup prior to depositing metal for silicide formation includes an HF etch, a first SC1 etch, a piranha etch and a second SC1 etch, so that a native oxide on the source/drain regions is less the 2 nanometers thick before deposition of the silicide metal. A process of forming a metal silicide layer on an integrated circuit containing an MOS transistor, in which a pre-metal deposition cleanup prior to depositing metal for silicide formation includes an HF etch, a first SC1 etch, a piranha etch and a second SC1 etch, so that a native oxide on the source/drain regions and the MOS gate is less the 2 nanometers thick before deposition of the silicide metal.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: September 8, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Scott Cuong Nguyen, Phuong-Lan Thi Tran, Michelle Marie Eastlack
  • Patent number: 9105651
    Abstract: Provided is a method of fabricating a MOS device including the following steps. A gate structure is formed on a substrate and a first spacer is formed at a sidewall of the gate structure. A first implant process is performed to form source and drain extension regions in the substrate. A spacer material layer is formed on the gate structure, the first spacer and the substrate. A treatment process is performed so that stress from the spacer material layer is applied onto and memorized in a channel between two source and drain extension regions. An anisotropic process is performed to remove a portion of the spacer material so that a second spacer is formed. A second implant process is performed to form source and drain regions in the substrate.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: August 11, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tsung-Hung Chang, Yi-Wei Chen, I-Fang Huang
  • Patent number: 9076817
    Abstract: A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: July 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chengwen Pei, Geng Wang, Yanli Zhang
  • Patent number: 9059270
    Abstract: A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Chih-Chao Yang
  • Patent number: 9059218
    Abstract: A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide layer and a top nitride layer are provided over the dummy gate structure and active region to protect the dummy gate during source and drain implantation. The active region is implanted using dopants such as, a n-type dopant or a p-type dopant to create a source region and a drain region in the active region, after which the sacrificial conformal layer is removed.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: June 16, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bharat Krishnan, Jinping Liu, Zhao Lun, Hui Zhan, Bongki Lee
  • Patent number: 9041057
    Abstract: A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin
  • Patent number: 9034749
    Abstract: A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer. In some embodiments, carbon and/or nitrogen can be present within the semiconductor-containing layer, the metal semiconductor alloy layer or both the semiconductor-containing layer and the metal semiconductor alloy layer. The presence of carbon and/or nitrogen within the semiconductor-containing layer and/or the metal semiconductor alloy layer provides stability to the gate structure. In another embodiment, a layer of carbon and/or nitrogen can be formed between the semiconductor-containing layer and the metal semiconductor alloy layer.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas L. Breil, Cyril Cabral, Jr., Martin M. Frank, Claude Ortolland
  • Patent number: 9034705
    Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: May 19, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Chin-Cheng Chien, Tien-Wei Yu, Hsin-Kuo Hsu, Yu-Shu Lin, Szu-Hao Lai, Ming-Hua Chang