Plural Doping Steps Patents (Class 438/305)
  • Patent number: 10685840
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a plurality of gate structures comprising a gate cap, sidewall spacers and source and drain regions; source and drain metallization features extending to the source and drain regions; and a liner extending along an upper portion of the sidewall spacers of at least one of the plurality of gate structures.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Hui Zang
  • Patent number: 10672907
    Abstract: A dummy gate structure straddling at least one semiconductor fin is formed on a substrate. Active semiconductor regions and raised active semiconductor regions may be formed. A planarization dielectric layer is formed over the at least one semiconductor fin, and the dummy gate structure is removed to provide a gate cavity. Electrical dopants in the channel region can be removed by outgassing during an anneal, thereby lowering the concentration of the electrical dopants in the channel region. Alternately or additionally, carbon can be implanted into the channel region to deactivate remaining electrical dopants in the channel region. The threshold voltage of the field effect transistor can be effectively controlled by the reduction of active electrical dopants in the channel region. A replacement gate electrode can be subsequently formed in the gate cavity.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Murshed M. Chowdhury, Brian J. Greene, Arvind Kumar
  • Patent number: 10600641
    Abstract: Implementations described herein relate to selective oxidation processes for semiconductor device manufacturing. In one implementation, the process includes delivering a substrate having a semiconductor device comprising at least a silicon material and a silicon germanium material formed thereon to a process chamber. Process variables are determined based upon the germanium concentration of the silicon germanium material and a desired oxide thickness and a selective oxidation process is performed utilizing the determined process variables.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: March 24, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Agus Sofian Tjandra
  • Patent number: 10573740
    Abstract: A method of producing a semiconductor device includes the following steps (A), (B), and (C). In the step (A), a semiconductor epitaxial wafer is prepared. The semiconductor epitaxial wafer includes a body region. In the step (B), a channel layer is formed by epitaxial growth. In the step (C), a gate insulation film is formed on the channel layer. The channel layer contains impurity at a concentration ranging from 1×1018 cm?3 to 1×1019 cm?3, inclusive, and has a thickness ranging from 10 nm to 100 nm, inclusive. In the steps of (B) and (C), a condition for the epitaxial growth and a condition for forming the gate insulation film are controlled so that a thickness distribution in the channel layer and a thickness distribution in the gate insulation film are positively correlated to each other.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 25, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Tsutomu Kiyosawa
  • Patent number: 10529832
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shallow, abrupt and highly activated tin (Sn) extension implant junction. The method includes forming a semiconductor fin on a substrate. A gate is formed over a channel region of the semiconductor fin. A Sn extension implant junction is formed on a surface of the semiconductor fin in the channel region.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Bruley, Marinus J. P. Hopstaken, Kam-Leung Lee
  • Patent number: 10522642
    Abstract: A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
    Inventors: Wei-Yang Lee, Feng-Cheng Yang, Chung-Te Lin, Yen-Ming Chen
  • Patent number: 10516044
    Abstract: A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: December 24, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
  • Patent number: 10411120
    Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the cha
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: September 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robin Hsin-Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Shogo Mochizuki, Chun W. Yeung
  • Patent number: 10396176
    Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Scott B. Clendenning, Szuya S. Liao, Florian Gstrein, Rami Hourani, Patricio E. Romero, Grant M. Kloster, Martin M. Mitan
  • Patent number: 10319855
    Abstract: A method for reducing series resistance for transistors includes forming a conductive gate over and insulated from a semiconductor substrate, forming source and/or drain extension regions within the substrate and adjacent to respective source and/or drain regions, and forming source and/or drain regions within the substrate. The source and/or drain extension regions are formed from a material alloyed with a first dopant and a second dopant, the first dopant configured to increase a lattice structure of the material forming the source and/or drain extension regions.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mona A. Ebrish, Oleg Gluschenkov
  • Patent number: 10312145
    Abstract: A method includes forming a plurality of fins on a substrate and a dummy gate structure over the fins. A spacer layer is formed over the dummy gate structure and the fins. The spacer layer is recessed to form asymmetrically recessed spacers along sidewalls of each of the fins, thereby exposing a portion of each of the fins. A source/drain epitaxy is grown on the exposed portions of the plurality of fins, a first source/drain epitaxy on a first fin being asymmetrical to a second source/drain epitaxy on a second fin. A device includes a first and second fin on a substrate with a gate structure formed over the first and second fins. An epitaxy if formed over the first fin and the second fin on the same side of the gate structure, where the height of the first epitaxy is greater than the height of the second epitaxy.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 10297608
    Abstract: The present disclosure relates to an integrated chip having an inter-digitated capacitor, and an associated method of formation. In some embodiments, the integrated chip has a plurality of upper electrodes separated from a substrate by a first dielectric layer. A plurality of lower electrodes vertically extend from between the plurality of upper electrodes to locations embedded within the substrate. A charge trapping dielectric layer is arranged between the substrate and the plurality of lower electrodes and between the plurality of upper electrodes and the plurality of lower electrodes. The charge trapping dielectric layer has a plurality of discrete segments respectively lining opposing sidewalls and a lower surface of one of the plurality of lower electrodes.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Chen Chen, Yu-Hsiung Wang, Han-Yu Chen
  • Patent number: 10256237
    Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: April 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-han Lee, Sun-ghil Lee, Myung-il Kang, Jeong-yun Lee, Seung-hun Lee, Hyun-jung Lee, Sun-wook Kim
  • Patent number: 10205011
    Abstract: Some embodiments relate to a method for forming a semiconductor device. The method includes forming a source region of a field effect transistor structure in a semiconductor substrate. The method further includes forming an oxide layer. The method also includes incorporating atoms of at least one atom type of a group of atom types into at least a part of the source region of the field effect transistor structure after forming the oxide layer. The group of atom types includes chalcogen atoms, silicon atoms and argon atoms.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Philip Christoph Brandt, Andre Rainer Stegner
  • Patent number: 10181397
    Abstract: Semiconductor devices and a method for forming the same are provided. In various embodiments, a method for forming a semiconductor device includes receiving a semiconductor substrate including a channel. An atmosphere-modulation layer is formed over the channel. An annealing process is performed to form an interfacial layer between the channel and the atmosphere-modulation layer.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Heng Chen, Hui-Cheng Chang, Hong-Fa Luan, Xiong-Fei Yu, Chia-Wei Hsu
  • Patent number: 10170364
    Abstract: A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Chun-Chen Yeh
  • Patent number: 10121665
    Abstract: A semiconductor device has an active region that includes a semiconductor layer. A transistor is formed in and above the active region, wherein the transistor has an implanted halo region that includes a halo dopant species and defines a halo dopant profile in the semiconductor layer. An implanted carbon species is positioned in the semiconductor layer, wherein the implanted carbon species defines a carbon species profile in the semiconductor layer that is substantially the same as the halo dopant profile of the implanted halo region in the semiconductor layer.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chi Dong Nguyen, Klaus Hempel
  • Patent number: 10020186
    Abstract: Implementations described herein relate to selective oxidation processes for semiconductor device manufacturing. In one implementation, the process includes delivering a substrate having a semiconductor device comprising at least a silicon material and a silicon germanium material formed thereon to a process chamber. Process variables are determined based upon the germanium concentration of the silicon germanium material and a desired oxide thickness and a selective oxidation process is performed utilizing the determined process variables.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: July 10, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Agus Sofian Tjandra
  • Patent number: 9923083
    Abstract: A method for fabricating a semiconductor structure includes forming a cut mask over a set of fin hard masks formed on a substrate. At least one gap defined at least in part by the cut mask is formed, and a first dielectric layer is formed within the at least one gap. A plurality of fins is formed, and the first dielectric layer is recessed to form an isolation region. A liner is deposited along exposed surfaces of the recessed first dielectric layer and the plurality of fins. A second dielectric layer is formed within a region defined by the liner and the plurality of fins. At least a portion of the second dielectric layer is removed to reveal the plurality of fins, wherein the portion of the second dielectric layer that is removed is based on the liner serving as an endpoint layer.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 9837534
    Abstract: A semiconductor device includes: a first substrate on which a first field effect transistor is provided; and a second substrate on which a second field effect transistor of a second conductive type is provided; the first and second substrates being bonded to each other at the substrate faces thereof on which the first and second field transistors are provided, respectively; the first field effect transistor and the second field effect transistor being electrically connected to each other.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: December 5, 2017
    Assignee: Sony Corporation
    Inventor: Takashi Yokoyama
  • Patent number: 9837514
    Abstract: Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joseph R. Greco, Qizhi Liu, Aaron L. Vallett, Robert F. Vatter
  • Patent number: 9818761
    Abstract: Methods and devices are provided to fabricate semiconductor devices with, e.g., SiGe-on-insulator structures. For example, a method for fabricating a semiconductor device includes forming a crystalline buffer layer on a substrate, forming an epitaxial semiconductor layer on the crystalline buffer layer, patterning the epitaxial semiconductor layer to form a patterned epitaxial semiconductor layer, and oxidizing a surface region of the crystalline buffer layer selective to the patterned epitaxial semiconductor layer to convert the surface region of the crystalline buffer layer to an insulating layer. The insulating layer insulates the patterned epitaxial semiconductor layer from the crystalline buffer layer. In one example structure, the substrate is a silicon substrate, the crystalline buffer layer is formed of germanium, the epitaxial semiconductor layer is formed of silicon-germanium, and the insulating layer is formed of amorphous germanium-oxide.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Effendi Leobandung, Devendra K. Sadana, Min Yang
  • Patent number: 9768058
    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a layer of insulating material, performing at least one damage-causing process operation to selectively damage portions of the insulating material adjacent the trenches, forming a conductive line in each of the trenches, after forming the conductive lines, performing a selective etching process to selectively remove at least portions of the damaged portions of the insulating material and thereby define an air gap positioned laterally adjacent each of the conductive lines, and forming a capping layer of material above the conductive lines, the air gap and the undamaged portion of the layer of insulating material.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: September 19, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Zhiguo Sun, Qiang Fang, Christian Witt
  • Patent number: 9735012
    Abstract: A method of forming a semiconductor device is provided including co-implanting a halo species and carbon in a semiconductor layer with a finite tilt angle with respect to a direction perpendicular to the surface of the semiconductor layer. Furthermore, a semiconductor device is provided including an N-channel transistor comprising a halo region made of a halo species with a dopant profile formed in a semiconductor layer and a carbon species implanted in the semiconductor layer with substantially the same dopant profile as the dopant profile of the halo region.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: August 15, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chi Dong Nguyen, Klaus Hempel
  • Patent number: 9735259
    Abstract: Various particular embodiments include an integrated circuit (IC) structure including: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joseph R. Greco, Qizhi Liu, Aaron L. Vallett, Robert F. Vatter
  • Patent number: 9680027
    Abstract: A nickelide material with reduced resistivity is provided as source/drain contact surfaces in both NMOS and PMOS technology. The nickelide material layer may be a ternary material such as NiInAs, and may be formed from a binary material previously formed in the source/drain regions. The binary material may be the channel material or it may be an epitaxial layer formed over the channel material. The same ternary nickelide material may be used as the source/drain contact surface in both NMOS and PMOS transistors. Various binary or ternary channel materials may be used for the NMOS transistors and for the PMOS transistors.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Richard Kenneth Oxland, Mark van Dal
  • Patent number: 9644523
    Abstract: A device is provided for protecting at least one metallic surface against discolorations under the action of heat. The device includes a metallic surface with a lacquer applied a lacquer applied thereto to the metallic surfaces and then stoving the metallic surface while sealing the metallic surface against oxygen contact to form a permanently effective oxygen barrier.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: May 9, 2017
    Assignee: DR. ING. H.C.F. PORSCHE AKTIENGESELLSCHAFT
    Inventor: Frank Haunstetter
  • Patent number: 9637662
    Abstract: The present invention relates to a method for applying a weldable anti-scale coat to steel, comprising producing a thin silicatic layer free from metal pigments on the metallic steel surface, and subsequently applying and curing a wet film of a curable, pigment-containing paint; wherein said paint comprises, in solution in a liquid phase, a binder, comprising hydrolysates and/or condensates of at least one silane/siloxane and/or at least one silicone resin; at least one particulate metallic pigment of AI and at least one particulate metallic pigment of Bi. The present invention also relates to application of an organic paint film system obtainable in the method of the invention, a paint formula useful in the method of the invention, a hot forming operation on steel coated in the method of the invention; and a hot-formed steel component suitable for electrical spot welding processes.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: May 2, 2017
    Assignee: Henkel AG & Co. KGaA
    Inventors: Marcel Roth, Reiner Wark, Thomas Moeller, Eva Wilke, Uta Sundermeier, Manuela Goeske-Krajnc
  • Patent number: 9614090
    Abstract: A semiconductor device includes at least one first gate structure and at least one second gate structure on a semiconductor substrate. The at least one first gate structure has a flat upper surface extending in a first direction and a first width in a second direction perpendicular to the first direction. The at least one second gate structure has a convex upper surface extending in the first direction and a second width in the second direction, the second width being greater than the first width.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-youn Kim, Sang-jung Kang, Ji-hwan An
  • Patent number: 9583380
    Abstract: In one example, a method includes forming a mask layer above or in a dielectric material. The dielectric material is exposed to photon radiation in an ambient atmosphere comprising a carbon gettering agent to generate damaged portions of the dielectric material. The mask layer blocks the photon radiation. The damaged portions of the dielectric material are removed.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: February 28, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Errol Todd Ryan
  • Patent number: 9583594
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: February 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Duan Quan Liao, Yikun Chen, Ching Hwa Tey
  • Patent number: 9548379
    Abstract: An asymmetrical finFET device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The fin extends along a length of the semiconductor substrate to define a fin length. A plurality of gate structures wrap around the sidewalls and upper fin surface of the fin. The plurality of gate structures includes at least one desired gate structure surrounded by at least one sacrificial gate structure. A first source/drain region is formed adjacent a first sidewall of the at least one desired gate structure, and a second source/drain region is formed adjacent a second sidewall of the at least one desired gate structure opposite the first sidewall. The dimensions of the first and second source/drain regions are asymmetrical with respect to one another.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Andres Bryant, Huiming Bu, Sivananda K. Kanakasabapathy, Tenko Yamashita
  • Patent number: 9537004
    Abstract: A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Ming Wu, Chien-Chang Su, Hsien-Hsin Lin, Yi-Fang Pai
  • Patent number: 9525019
    Abstract: A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: December 20, 2016
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Mickael Gros-Jean
  • Patent number: 9472423
    Abstract: A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: October 18, 2016
    Assignee: SYNOPSYS, INC.
    Inventors: Victor Moroz, Dipankar Pramanik
  • Patent number: 9443956
    Abstract: A method includes forming a line feature above a substrate. Carbon-containing spacers are formed on sidewalls of the line feature. A first dielectric layer is formed above the carbon spacers and the line feature. The first dielectric layer is planarized to expose upper ends of the carbon-containing spacers. An ashing process is performed to remove the carbon-containing spacers and define air gaps adjacent the line feature. A cap layer is formed to seal the upper ends of the air gaps.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: September 13, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hong Yu, Biao Zuo, Jin Ping Liu, Huang Liu
  • Patent number: 9443954
    Abstract: The present invention provides a method for forming a semiconductor device having a metal gate. The method includes firstly, a substrate is provided, and a first semiconductor device and a second semiconductor device are formed on the substrate, having a first gate trench and a second trench respectively. Next, a bottom barrier layer is formed in the first gate trench and a second trench. Afterwards, a first pull back step is performed, to remove parts of the bottom barrier layer, and a first work function metal layer is then formed in the first gate trench. Next, a second pull back step is performed, to remove parts of the first work function metal layer, wherein the topmost portion of the first work function metal layer is lower than the openings of the first gate trench and the second gate trench.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: September 13, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 9401352
    Abstract: Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. The body region physically contacts the pocket implant region.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: July 26, 2016
    Assignee: Infineon Technologies AG
    Inventors: Mayank Shrivastava, Harald Gossner, Ramgopal Rao, Maryam Shojaei Baghini
  • Patent number: 9396986
    Abstract: Forming a shallow trench isolation (STI) structure filled with a flowable dielectric layer involves performing an implant to generate passages in the upper portion of the flowable dielectric layer. The passages enable oxygen source in a thermal anneal to reach the flowable dielectric layer near the bottom of the STI structure during the thermal anneal to convert a SIONH network of the reflowable dielectric layer to a network of SiOH and SiO. The passages also help to provide escape paths for by-products produced during another thermal anneal to convert the network of SiOH and SiO to SiO2.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Sen-Hong Syue, Ziwei Fang
  • Patent number: 9391202
    Abstract: The semiconductor device including: a semiconductor layer extending in a first direction, the semiconductor layer including a pair of source/drain regions and a channel region, a gate extending on the semiconductor layer to cover the channel region, and a gate dielectric layer interposed between the channel region and the gate, a corner insulating spacer having a first surface and a second surface, the first surface extending in the second direction along a side wall of the gate, the first surface covering from a side portion of the gate dielectric layer to at least a portion of the side wall of the gate, and the second surface covering a portion of the semiconductor layer, and an outer portion insulating spacer covering the side wall of the gate above the corner insulating spacer, the outer portion insulating spacer having a smaller dielectric constant than the corner insulating spacer, may be provided.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: July 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Je-min Park
  • Patent number: 9349817
    Abstract: Embodiments of the disclosure provide semiconductor device structures and methods of forming the same. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: May 24, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chen-Liang Liao, Chih-Hsiao Chen, Yi-Lii Huang, Yao-Yu Li
  • Patent number: 9337282
    Abstract: A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a n? type drift layer deposited on an n+ type semiconductor substrate. The oxide film is patterned to have tapered ends. Two proton irradiations are carried out on the n? type drift layer with the oxide film as a mask to form a point defect region in the vicinity of the surface of the n? type drift layer. Silica paste containing 1% by weight platinum is applied to an exposed region of the n? type drift layer surface not covered with the oxide film. Heat treatment inverts the vicinity of the surface of the n? type drift layer to p-type by platinum atoms which are acceptors. A p-type inversion enhancement region forms a p-type anode region.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: May 10, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shoji Kitamura
  • Patent number: 9324603
    Abstract: A method is disclosed that includes the operations outlined below. An insulating material is disposed within a plurality of trenches on a semiconductor substrate and over the semiconductor substrate. The first layer is formed over the insulating material. The first layer and the insulating material are removed.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: April 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Yeu Tsai, Chia-Hui Lin, Ching-Yu Chen, Chui-Ya Peng
  • Patent number: 9312189
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack by performing a laser anneal process. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: April 12, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Alban Zaka, Ran Yan, El Mehdi Bazizi, Jan Hoentschel
  • Patent number: 9305921
    Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: April 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Chan Lee, Seung-Jae Lee, Sang-Bom Kang, Dae-Young Kwak, Myeong-Cheol Kim, Yong-Ho Jeon
  • Patent number: 9252233
    Abstract: The present disclosure relates to a method of forming a FinFET device having sidewalls spacers comprising an air gap that provides for a low dielectric constant, and an associated apparatus. In some embodiments, the method is performed by forming a fin of semiconductor material on a semiconductor substrate. A gate structure, having a gate dielectric layer and an overlying gate material layer, is formed at a position overlying the fin of semiconductor material. Sidewall spacers are formed at positions abutting opposing sides of the gate structure. Respective sidewall spacers have a first layer of insulating material abutting the gate structure and a second layer of insulating material separated from the first layer of insulating material by an air gap. By forming the FinFET device to have sidewall spacers with air gaps, the parasitic capacitance of the FinFET device and a corresponding RC time delay are decreased.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Rou-Han Kuo, Ting-Fu Lin, Sheng-Fu Yu, Tzung-Da Liu, Li-Yi Chen
  • Patent number: 9252018
    Abstract: A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Renee T. Mo, Wesley C. Natzle, Vijay Narayanan, Jeffrey W. Sleight
  • Patent number: 9240408
    Abstract: Integrated circuit device with transistors having different threshold voltages and methods of forming the device are provided. The device may include the first, second and third transistors having threshold voltages different from each other. The first transistor may be free of a stacking fault and the second transistor may include a stacking fault. The concentration of the channel implant region of the third transistor may be different from the concentration of the channel implant region of the first transistor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Hyun Song, Seung-Chul Lee, In-Kook Jang
  • Patent number: 9236448
    Abstract: In the present method of fabricating a semiconductor device, initially, a semiconductor substrate is provided. An oxide layer is provided on and in contact with the substrate, and a polysilicon layer is provided on and in contact with the oxide layer. A layer of photoresist is provided on the polysilicon layer, and the photoresist is patterned to provide a photoresist body, which is used as a mask to etch away polysilicon and oxide, forming a polysilicon element thereunder. The photoresist body is then removed. A nickel layer is provided on the resulting structure, and a reaction step is undertaken to provide that nickel diffuses into the exposed top and side portions of the polysilicon body, forming nickel silicide. After the reaction step, the remaining nickel is removed, and a chemical-mechanical polishing step is undertaken to remove nickel silicide so that a pair of nickel silicide bodies remain, separated by polysilicon.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: January 12, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Eunha Kim, Minh-Van Ngo
  • Patent number: 9230835
    Abstract: Embodiments of an integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices are provided herein. In some embodiments, an integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices may include a first deposition chamber configured to deposit a first layer atop the substrate, the first layer comprising titanium oxide (TiO2) or selenium (Se); a second deposition chamber configured to deposit a second layer atop the first layer, the second layer comprising titanium; a third deposition chamber configured to deposit a third layer atop the second layer, the third layer comprising one of titanium nitride (TiN) or tungsten nitride (WN).
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 5, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Avgerinos V. Gelatos, Srinivas Gandikota, Seshadri Ganguli, Xinyu Fu, Bo Zheng, Yu Lei