Utilizing Gate Sidewall Structure Patents (Class 438/303)
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Publication number: 20150115374Abstract: The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure.Type: ApplicationFiled: April 26, 2012Publication date: April 30, 2015Applicant: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huaxiang Yin, Xiaolong Ma, Changliang Qi, Qiuxia Xu, Dapeng Chen
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Patent number: 9006072Abstract: A method of forming a metal silicide layer includes the following steps. At first, at least a gate structure, at least a source/drain region and a first dielectric layer are formed on a substrate, and the gate structure is aligned with the first dielectric layer. Subsequently, a cap layer covering the gate structure is formed, and the cap layer does not overlap the first dielectric layer and the source/drain region. Afterwards, the first dielectric layer is removed to expose the source/drain region, and a metal silicide layer totally covering the source/drain region is formed.Type: GrantFiled: March 14, 2013Date of Patent: April 14, 2015Assignee: United Microelectronics Corp.Inventors: Po-Chao Tsao, Chien-Ting Lin
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Patent number: 9006064Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.Type: GrantFiled: March 11, 2013Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Barry P. Linder, Shahab Siddiqui
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Patent number: 8999795Abstract: An asymmetrical field effect transistor (FET) device includes a semiconductor substrate, a buried oxide layer disposed on the semiconductor substrate, an extended source region disposed on the buried oxide layer and a drain region disposed on the buried oxide layer. The asymmetrical FET device also includes a silicon on insulator region disposed between the extended source region and the drain region and a gate region disposed above the extended source region and the silicon on insulator region.Type: GrantFiled: August 12, 2013Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh
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Publication number: 20150093871Abstract: A method of manufacturing a semiconductor device includes forming a dummy gate structure on a semiconductor substrate, forming sidewall spacers, and forming heavily doped source/drain regions. After removing the spacers, a stress material layer is formed over the dummy gate structure. An annealing process is performed to transfer the stress to the device channel region. After the annealing process, the stress material layer is removed. The dummy gate structure is replaced by a high-k dielectric layer and a metal gate structure. Subsequently, contact holes are formed to expose at least part of the heavily doped source/drain regions, and self-aligned silicide is formed over exposed portions of the heavily doped source/drain regions.Type: ApplicationFiled: March 27, 2014Publication date: April 2, 2015Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Yong Li
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Publication number: 20150087128Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.Type: ApplicationFiled: December 4, 2014Publication date: March 26, 2015Inventors: Koji MAEKAWA, Tatsuyoshi MIHARA
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Patent number: 8987103Abstract: In advanced semiconductor devices, spacer elements may be formed on the basis of a multi-station deposition technique, wherein a certain degree of variability of the various sub-layers of the spacer materials, such as a different thickness, may be applied in order to enhance etch conditions during the subsequent anisotropic etch process. Consequently, spacer elements of improved shape may result in superior deposition conditions when using a stress-inducing dielectric material. Consequently, yield losses due to contact failures in densely packed device areas, such as static RAM areas, may be reduced.Type: GrantFiled: May 10, 2010Date of Patent: March 24, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Markus Lenski, Kerstin Ruttloff, Volker Jaschke, Frank Seliger, Ralf Otterbach
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Patent number: 8987104Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate and forming a plurality of spacers proximate the gate electrode structures, wherein the plurality of spacers comprises a first silicon nitride spacer positioned adjacent a sidewall of the gate electrode structure, a generally L-shaped silicon nitride spacer positioned adjacent the first silicon nitride spacer, and a silicon dioxide spacer positioned adjacent the generally L-shaped silicon nitride spacer.Type: GrantFiled: May 16, 2011Date of Patent: March 24, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Peter Baars, Sven Beyer, Jan Hoentschel, Thilo Scheiper
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Patent number: 8987105Abstract: A method of manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) by using a single mask, etching regions of an SiC semiconductor layer which serve as an impurities implantation region and a mark region, to form recesses, (b) by using the same mask as in the step (a), performing ion-implantation in the recesses of the regions which serve as the impurities implantation region and the mark region, at least from an oblique direction relative to a surface of the SiC semiconductor layer and (c) positioning another mask based on the recess of the region which serves as the impurities implantation region or the mark region, and performing well implantation in a region containing the impurities implantation region.Type: GrantFiled: April 17, 2013Date of Patent: March 24, 2015Assignee: Mitsubishi Electric CorporationInventors: Noriaki Tsuchiya, Yoichiro Tarui
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Patent number: 8980701Abstract: A method of forming a semiconductor device includes the following steps. At least a fin structure is provided on a substrate and a gate structure partially overlapping the fin structure is formed. Then, a dielectric layer is formed on the substrate. Subsequently, a first etching process is performed to remove apart of the dielectric layer to form a first spacer surrounding the gate structure and a second spacer surrounding a sidewall of the fin structure, and a protective layer is formed in-situ to cover the gate structure and the first spacer. Finally, a second etching process is performed to remove a part of the protective layer and totally remove the second spacer.Type: GrantFiled: November 5, 2013Date of Patent: March 17, 2015Assignee: United Microelectronics Corp.Inventors: Shui-Yen Lu, Chih-Ho Wang, Jhen-Cyuan Li
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Publication number: 20150069466Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.Type: ApplicationFiled: September 10, 2013Publication date: March 12, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Che-Cheng CHANG, Tung-Wen CHENG, Yi-Jen CHEN, Yung-Jung CHANG
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Patent number: 8956943Abstract: A method for manufacturing a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby forming a nitride layer on a sidewall of the gate conductive layer and extending into the opening.Type: GrantFiled: May 27, 2013Date of Patent: February 17, 2015Assignee: United Microelectronics CorporationInventors: Chien-Hung Chen, Tzu-Ping Chen, Yu-Jen Chang
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Patent number: 8951876Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least a gate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.Type: GrantFiled: June 20, 2012Date of Patent: February 10, 2015Assignee: United Microelectronics Corp.Inventors: Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung
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Patent number: 8951877Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.Type: GrantFiled: March 13, 2013Date of Patent: February 10, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Nicolas Sassiat, Carsten Grass, Jan Hoentschel, Ran Yan, Ralf Richter
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Patent number: 8951875Abstract: A semiconductor structure includes a substrate, a gate structure, and two silicon-containing structures. The substrate includes two recesses defined therein and two doping regions of a first dopant type. Each of the two doping regions extends along a bottom surface and at least portion of a sidewall of a corresponding one of the two recesses. The gate structure is over the substrate and between the two recesses. The two silicon-containing structures are of a second dopant type different from the first dopant type. Each of the two silicon-containing structures fills a corresponding one of the two recesses, and an upper portion of each of the two silicon-containing structures has a dopant concentration higher than that of a lower portion of each of the two silicon-containing structures.Type: GrantFiled: December 10, 2012Date of Patent: February 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: King-Yuen Wong, Ming-Lung Cheng, Chien-Tai Chan, Da-Wen Lin, Chung-Cheng Wu
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Patent number: 8946007Abstract: After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. The removal of the bottom semiconductor layer exposes a horizontal surface of the buried insulator layer present between source and drain regions on which a conductive material layer is formed as a back gate electrode.Type: GrantFiled: February 7, 2013Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Douglas C. La Tulipe, Jr.
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Patent number: 8946036Abstract: A method for forming a dielectric film is disclosed. The method includes (a) exposing a substrate to a first gas pulse having a first oxygen-containing gas in a chamber; (b) exposing the substrate to multiple consecutive second gas pulses having a second oxygen-containing gas in the chamber, wherein the first oxygen-containing gas is different from the second oxygen-containing gas; and (c) sequentially after (a) and (b), exposing the substrate to a third gas pulse having a metal-containing gas in the chamber. Steps (a), (b), and (c) may be repeated any number of times to form the dielectric film with a predetermined thickness.Type: GrantFiled: December 7, 2012Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Liang-Chen Chi, Chia-Ming Tsai, Yu-Min Chang, Chin-Kun Wang, Miin-Jang Cheng, Keng-Ham Lin
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Patent number: 8946003Abstract: A semiconductor transistor is formed as follows. A gate electrode is formed over but is insulated from a semiconductor body region. A first layer of insulating material is formed over the gate electrode and the semiconductor body region. A second layer of insulating material different from the first layer of insulating material is formed over the first layer of insulating material. Only the second layer of insulating material is etched to form spacers along the side-walls of the gate electrode. Impurities are implanted through the first layer of insulating material to form a source region and a drain region in the body region. A substantial portion of those portions of the first layer of insulting material extending over the source and drain regions is removed.Type: GrantFiled: February 20, 2007Date of Patent: February 3, 2015Assignee: SK hynix Inc.Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
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Publication number: 20150024569Abstract: A method of forming an integrated circuit includes forming a gate electrode over a substrate, forming a recess in the substrate and adjacent to the gate electrode, forming a diffusion barrier structure in the recess, forming an N-type doped silicon-containing structure over the diffusion barrier structure and thermally annealing the N-type doped silicon-containing structure. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode and the second portion is distant from the gate electrode. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate and the second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.Type: ApplicationFiled: October 9, 2014Publication date: January 22, 2015Inventors: Chun Hsiung TSAI, Su-Hao LIU, Chien-Tai CHAN, King-Yuen WONG, Chien-Chang SU
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Patent number: 8932930Abstract: Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided.Type: GrantFiled: November 9, 2012Date of Patent: January 13, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Sven Beyer, Frank Seliger, Gunter Grasshoff
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Publication number: 20150008528Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.Type: ApplicationFiled: September 25, 2014Publication date: January 8, 2015Inventors: Shyue Seng TAN, Lee Wee TEO, Yung Fu CHONG, Elgin QUEK, Sanford CHU
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Patent number: 8928040Abstract: A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics).Type: GrantFiled: December 27, 2013Date of Patent: January 6, 2015Assignee: SK Hynix Inc.Inventor: Kyung Do Kim
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Patent number: 8927378Abstract: An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer. An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.Type: GrantFiled: February 21, 2013Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Chengwen Pei, Jeffrey B. Johnson, Zhengwen Li, Jian Yu
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Publication number: 20150004769Abstract: A method of fabricating a semiconductor device is disclosed. A substrate with protrusion structures is provided. A patterned photoresist layer is formed over the substrate, including the protrusion structures. An ion-implantation is applied to the substrate, including to the patterned photoresist layer and an outer portion of the patterned photoresist layer is formed a hardened portion. A two-stage-striping process is performed to remove the patterned photoresist layer. The first stage is performing a low-temperature-dry-etch to substantially remove the hardened portion of the patterned photoresist layer. The second stage is performing a wet etch to remove the remaining patterned photoresist layer.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Yi-Wei Chiu, Tzu Chan Weng, Li Te Hsu, Hsu-Yu Huang
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Patent number: 8916430Abstract: A method for fabricating an integrated circuit includes forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region, forming a sacrificial spacer on sidewalls of the first and second gate electrode structures, and forming deep drain and source regions selectively in the first and second active regions by using the sacrificial spacer as an implantation mask. The method further includes forming drain and source extension and halo regions in the first and second active regions after removal of the sacrificial spacer and forming a nitrogen implant region in the halo region of the first active region after formation of the drain and source extension and halo regions.Type: GrantFiled: May 17, 2013Date of Patent: December 23, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Ran Yan, Jan Hoentschel, Shiang Yang Ong
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Patent number: 8916428Abstract: A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming spacers adjoining sidewalls of the gate stacks, wherein at least one of the spacers extends beyond an edge the isolation feature. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.Type: GrantFiled: January 5, 2012Date of Patent: December 23, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsan-Chun Wang, Chun Hsiung Tsai
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Publication number: 20140370681Abstract: A field-effect transistor (FET) and methods for fabricating such. The FET includes a substrate having a crystalline orientation, a source region in the substrate, and a drain region in the substrate. Gate spacers are positioned over the source region and the drain region. The gate spacers include a gate spacer height. A source contact physically and electrically contacts the source region and extends beyond the gate spacer height. A drain contact physically and electrically contacts the drain region and extends beyond the gate spacer height. The source and drain contacts have the same crystalline orientation as the substrate.Type: ApplicationFiled: June 17, 2013Publication date: December 18, 2014Inventors: Kevin K. Chan, Wilfried E. Haensch, Effendi Leobandung, Min Yang
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Publication number: 20140361339Abstract: A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate; and forming gate structures on a surface of the semiconductor substrate. The method also includes forming sidewall spacers around the gate structures; and forming a protection layer on the sidewall spacers. Further, the method includes forming sigma shape trenches in the semiconductor substrate at sides of the gate structures; and forming SiGe structures with a surface protruding from the surface of the semiconductor substrate in the sigma shape trenches. Further, the method also includes removing the sidewall spacers and a portion of the protection layer; and forming lightly doped drain regions in the semiconductor substrate at both sides of the gate structures.Type: ApplicationFiled: January 23, 2014Publication date: December 11, 2014Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventor: JIALEI LIU
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Publication number: 20140357042Abstract: A known problem when manufacturing transistors is the stress undesirably introduced by the spacers into the transistor channel region. In order to solve this problem, the present invention proposes an ion implantation aimed at relaxing the stress of the spacer materials. The relax implantation is performed after the spacer has been completely formed. The relax implantation may be performed after a silicidation process or after an implantation step in the source and drain regions followed by an activation annealing and before performing the silicidation process.Type: ApplicationFiled: May 31, 2013Publication date: December 4, 2014Inventors: Ralf Richter, Stefan Flachowsky, Jan Hoentschel
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Patent number: 8901665Abstract: The present disclosure provides a method of semiconductor fabrication including forming an inter-layer dielectric (ILD) layer on a semiconductor substrate. The ILD layer has an opening defined by sidewalls of the ILD layer. A spacer element is formed on the sidewalls of the ILD layer. A gate structure is formed in the opening adjacent the spacer element. In an embodiment, the sidewall spacer also for a decrease in the dimensions (e.g., length) of the gate structure formed in the opening.Type: GrantFiled: December 22, 2011Date of Patent: December 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andrew Joseph Kelly, Pei-Shan Chien, Yung-Ta Li, Chan Syun Yang
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Patent number: 8901537Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.Type: GrantFiled: December 21, 2010Date of Patent: December 2, 2014Assignee: Intel CorporationInventors: Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Ravi Pillarisetty, Niloy Mukherjee, Jack T. Kavalieros, Roza Kotlyar, Willy Rachmady, Mark Y. Liu
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Patent number: 8900952Abstract: A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.Type: GrantFiled: March 11, 2013Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 8900959Abstract: A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.Type: GrantFiled: March 12, 2013Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Isaac Lauer, Jeffrey W. Sleight
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Publication number: 20140349460Abstract: The substrate is provided with a first semiconducting area partially covered by a first masking pattern to define a protected surface and an open surface. A continuous layer of silicon-germanium is deposited in non-selective manner on the first semiconducting area and on the first gate pattern. The continuous silicon-germanium layer forms an interface with the first semiconducting area. A diffusion/condensation annealing is performed to make the germanium atoms diffuse from the silicon-germanium layer to the open surface of the first semiconducting area. The masking pattern is a gate stack of the transistor or is used to define the shape of the gate stack in an electrically insulating layer so as to form a self-aligned gate stack with the source and drain areas.Type: ApplicationFiled: May 6, 2014Publication date: November 27, 2014Inventors: Maud VINET, Laurent GRENOUILLET, Yves MORAND
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Publication number: 20140346577Abstract: The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode.Type: ApplicationFiled: August 11, 2014Publication date: November 27, 2014Inventors: Gurtej S. Sandhu, Kunal R. Parekh
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Patent number: 8896048Abstract: The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.Type: GrantFiled: June 4, 2004Date of Patent: November 25, 2014Assignee: Spansion LLCInventors: Richard Fastow, Zhigang Wang, Yue-Song He, Kazuhiro Mizutani, Pavel Fastenko
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Patent number: 8889554Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure.Type: GrantFiled: April 18, 2011Date of Patent: November 18, 2014Assignee: The Institue of Microelectronics Chinese Academy of ScienceInventors: Haizhou Yin, Wei Jiang, Zhijiong Luo, Huilong Zhu
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Patent number: 8883651Abstract: A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.Type: GrantFiled: July 31, 2012Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Seokhoon Kim, Sangsu Kim, Chung Geun Koh, Byeongchan Lee, Sunghil Lee, Jinyeong Joe
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Patent number: 8884346Abstract: A semiconductor structure includes a gate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided.Type: GrantFiled: January 15, 2014Date of Patent: November 11, 2014Assignee: United Microelectronics Corp.Inventors: Chin-I Liao, Chin-Cheng Chien
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Patent number: 8883600Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.Type: GrantFiled: December 21, 2012Date of Patent: November 11, 2014Assignee: SuVolta, Inc.Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane
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Patent number: 8877598Abstract: A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process.Type: GrantFiled: June 1, 2012Date of Patent: November 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Wang, Yu Lun Liu, Chia-Chu Liu, Ya Hui Chang, Kuei-Shun Chen
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Patent number: 8877597Abstract: When forming metal silicide regions, such as nickel silicide regions, in sophisticated transistors requiring a shallow drain and source dopant profile, superior controllability may be achieved by incorporating a silicide stop layer. To this end, in some illustrative embodiments, a carbon species may be incorporated on the basis of an implantation process in order to significantly modify the metal diffusion during the silicidation process. Consequently, an increased thickness of the metal silicide may be provided, while not unduly increasing the probability of creating contact failures.Type: GrantFiled: August 12, 2011Date of Patent: November 4, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Jens Heinrich, Frank Feustel, Kai Frohberg
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Patent number: 8872244Abstract: After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion.Type: GrantFiled: April 18, 2013Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Hong He, Chiahsun Tseng, Chun-chen Yeh, Yunpeng Yin
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Patent number: 8871585Abstract: A manufacturing method of a semiconductor device includes: forming a first gate insulating film on a semiconductor substrate in first and second regions in an active area; forming first gate electrodes on the first gate insulating film in the first and second regions; forming source/drain regions by introducing impurities at both sides of the first gate electrode in the first and second regions; performing heat treatment of activating the impurities; forming a stress liner film so as to cover the whole surface of first gate electrodes in the first and second regions; removing the stress liner film at an upper portion of the first gate electrode in the second region while allowing the stress liner film at least at a portion in the first region to remain to expose the upper portion of the first gate electrode in the second region; forming a groove by removing the first gate electrode in the second region; and forming a second gate electrode in the groove.Type: GrantFiled: May 26, 2011Date of Patent: October 28, 2014Assignee: Sony CorporationInventor: Masanori Tsukamoto
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Patent number: 8871625Abstract: A method of fabricating a spacer structure which includes forming a dummy gate structure comprising a top surface and sidewall surfaces over a substrate and forming a spacer structure over the sidewall surfaces. Forming the spacer structure includes depositing a first oxygen-sealing layer on the dummy gate structure and removing a portion of the first oxygen-sealing layer on the top surface of the dummy gate structure, whereby the first oxygen-sealing layer remains on the sidewall surfaces. Forming the spacer structure further includes depositing an oxygen-containing layer on the first oxygen-sealing layer and the top surface of the dummy gate structure. Forming the spacer structure further includes depositing a second oxygen-sealing layer on the oxygen-containing layer and removing a portion of the second oxygen-sealing layer over the top surface of the dummy gate structure. Forming the spacer structure further includes thinning the second oxygen-sealing layer.Type: GrantFiled: May 2, 2013Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Ryan Chia-Jen Chen
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Patent number: 8859381Abstract: A field-effect transistor (FET) and methods for fabricating such. The FET includes a substrate having a crystalline orientation, a source region in the substrate, and a drain region in the substrate. Gate spacers are positioned over the source region and the drain region. The gate spacers include a gate spacer height. A source contact physically and electrically contacts the source region and extends beyond the gate spacer height. A drain contact physically and electrically contacts the drain region and extends beyond the gate spacer height. The source and drain contacts have the same crystalline orientation as the substrate.Type: GrantFiled: June 29, 2013Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Wilfried E. Haensch, Effendi Leobandung, Min Yang
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Patent number: 8847353Abstract: Capacitance blocks (first block and second block) respectively formed on two different adjacent common pad electrodes are electrically connected in series through an upper electrode. A distance between two adjacent capacitance blocks connected in series through an upper electrode film for the upper electrode corresponds to a distance between opposing lower electrodes disposed in an outermost perimeter of each capacitance block, and is two or less times than a total film thickness of the upper electrode film embedded between the two adjacent capacitance blocks.Type: GrantFiled: December 19, 2011Date of Patent: September 30, 2014Assignee: PS4 Luxco S.A.R.L.Inventor: Eiji Hasunuma
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Publication number: 20140284716Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a second well region adjacent the first well region, having the second conductivity type, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region.Type: ApplicationFiled: June 11, 2014Publication date: September 25, 2014Applicant: Freescale Semiconductor, Inc.Inventors: Xiaowei Ren, David C. Burdeaux, Robert P. Davidson, Michele L. Miera
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Patent number: 8841193Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.Type: GrantFiled: June 26, 2013Date of Patent: September 23, 2014Assignee: United Microelectronics Corp.Inventors: Ted Ming-Lang Guo, Chin-Cheng Chien, Shu-Yen Chan, Ling-Chun Chou, Tsung-Hung Chang, Chun-Yuan Wu
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Publication number: 20140264557Abstract: A method for doping terminals of a field-effect transistor (FET), the FET including a drain region, a source region, and a surround gate surrounding a channel region, the method including depositing a dopant-containing layer, such that the surround gate prevents the dopant-containing layer from contacting the channel region of the FET, the dopant-containing layer including a dopant. The dopant then diffuses the dopant from the dopant-containing layer into at least one of the drain region and source region of the FET.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Chung H. Lam, Jing Li