Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and an integrated circuit including the same. The semiconductor device (300), without limitation, may include a gate electrode (320) having a gate length (l) and a gate width (w) located over a substrate (310) and a gate electrode material feature (330) located adjacent a gate width (w) side of the gate electrode (320). The semiconductor device (300) may further include a silicide region (350) located over the substrate (310) proximate a side of the gate electrode (320), the gate electrode material feature (330) breaking the silicided region (350) into multiple silicide portions (353, 355, 358).

Abstract: Split gate memory cell formation includes forming a sacrificial layer over a substrate. The sacrificial layer is patterned to form a sacrificial structure with a first sidewall and a second sidewall. A layer of nanocrystals is formed over the substrate. A first layer of polysilicon is deposited over the substrate. An anisotropic etch on the first polysilicon layer forms a first polysilicon sidewall spacer adjacent the first sidewall and a second polysilicon sidewall spacer adjacent the second sidewall. Removal of the sacrificial structure leaves the first sidewall spacer and the second sidewall spacer. A second layer of polysilicon is deposited over the first and second sidewall spacers and the substrate. An anisotropic etch on the second layer of polysilicon forms a third sidewall spacer adjacent to a first side of the first sidewall spacer and a fourth sidewall spacer adjacent to a first side of the second sidewall spacer.

Abstract: The present invention makes it is possible to provide a manufacturing method of a semiconductor device by which damage by plasma process or doping process during a LDD formation process can be reduced as much as possible. Charge density to be stored in a gate electrode and the damage of an element due to plasma are reduced as much as possible during anisotropic etching of an LDD formation process, by forming an LDD region in the state that a conductive protecting film is formed to cover a whole area of a substrate. Further, damage by charged particles during a process of doping a high concentration of impurity is also reduced.

Abstract: A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the layer tunnel junction barrier. The device further includes a second gate insulator layer on a sidewall of the tunnel junction barrier, a third gate insulator on a second portion of the substrate adjacent the tunnel junction barrier and a gate electrode on the second gate insulator and the third gate insulator. First and second impurity-doped regions are disposed in the substrate and are coupled by a channel through the first and second portions of the substrate. Fabrication of such a device is also describes.

Abstract: A method of manufacturing a semiconductor integrated circuit device is provided including providing a substrate with projecting island regions formed in stripes, with first regions of the substrate adjacent the projecting island regions and with a conductive film covering the projecting island regions and first regions. An insulating film is formed between the projecting island regions and conductive film, wherein the projecting island regions extend in a first direction in stripes. The conductive film is anisotropically etched using a mask covering contact regions to form conductive lines on sides of the projecting island regions and the contact regions integrated with the conductive lines, which conductive lines serve as common gate electrodes for MISFETs.

Abstract: A method for manufacturing a capacitor electrode structure, according to which the following steps are executed: A substrate is provided, which comprises contact pads arranged in lines and rows on a surface of the substrate. The lines are non-parallel to the rows. A first mold is applied on the substrate. At least one first trench is formed into the first mold above the contact pads. The first trench spans over at least two contact pads arranged in one row. A first dielectric layer is applied on side walls of the at least one first trench for forming first supporting walls. A second mold is applied on the substrate. At least one second trench is formed into the second mold above the contact pads. The second trench spans over at least two contact pads arranged in one line. A second dielectric layer is applied on side walls of the at least one second trench for forming second supporting walls.

Abstract: A memory cell structure comprises a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers and a gate structure positioned at least on the gate oxide layer. Particularly, each of two stack structures includes a first oxide block, a conductive block and a second oxide block, and the two conductive spacers are positioned at on the sidewall of the two conductive blocks of the two stack structures. The two conductive spacers are preferably made of polysilicon, and have a top end lower than the bottom surface of the second oxide block. In addition, a dielectric spacer is positioned on each of the two conductive spacers.

Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted.

Abstract: A method for forming a semiconductor device includes forming a liner over a semiconductor material including a control electrode. The method further includes forming a first spacer adjacent to the control electrode, wherein the first spacer has a first width. The method further includes implanting current electrode dopants. The method further includes removing the first spacer. The method further includes forming a second spacer adjacent the control electrode, wherein the second spacer has a second width and wherein the second width is less than the first width. The method further includes using the second spacer as a protective mask to selectively remove the liner. The method further includes forming a stressor layer overlying the control electrode and current electrode regions.

Abstract: A non-volatile memory device including a control gate pattern having a tunnel insulation pattern, a trap-insulation pattern, a blocking insulation pattern and a control gate electrode, which are stacked on a semiconductor substrate. A selection gate pattern is disposed on the semiconductor substrate at one side of the control gate pattern. A gate insulation pattern is interposed between the selection gate electrode and the semiconductor substrate, and between the selection gate electrode and the control gate pattern. A cell channel region includes a first channel region defined in the semiconductor substrate under the selection gate electrode and a second channel region defined in the semiconductor substrate under the control gate electrode.

Abstract: The invention improves the performance of a semiconductor device. A metal silicide film is formed by a silicide process on a gate electrode and an n+-type source region of an LDMOSFET, and no such metal silicide film is formed on an n?-type offset drain region, an n-type offset drain region, and an n+-type drain region. A side wall spacer comprising a silicon film is formed via an insulating film on the side wall of the gate electrode over the drain side thereof, and a field plate electrode is formed by this side wall spacer. The field plate electrode does not extend above the gate electrode, and a metal silicide film is formed over the entire upper surface of the gate electrode in the silicide process.

Abstract: A method for fabricating a transistor. A substrate having a gate electrode thereon and insulated therefrom is provided. A first gate spacer with a first dielectric material is formed on the sidewalls of the gate electrode. A liner with a second dielectric material is formed on the upper surfaces of the substrate, the first gate spacer and the gate electrode, wherein the first dielectric material has an etching selectivity relative to the second dielectric material. Ion implantation is performed on the substrate to form source/drain regions in the substrate and substantially self-aligned with the liner on the first gate spacer. The liner is removed from the upper surfaces of the gate electrode and the source/drain regions. A method for fabricating a semiconductor device is also disclosed.

Abstract: A method of manufacturing self-aligned contact openings is provided. A substrate having a number of device structures is provided and the top of the device structures is higher than the surface of the substrate. A first dielectric layer and a conductive layer are sequentially formed on the surfaces of the substrate and the device structures. Next, a part of the conductive layers on the top and the sidewalls of the device structures is removed and a number of first spacers is formed on the exposed sidewalls of the device structures. The exposed conductive layer and the first dielectric layer are removed by using the first spacer as the mask to expose the substrate. Then, a number of conductive spacers is formed. A number of second spacers is formed on the sidewalls of the conductive spacers.

Abstract: Provided is a method of manufacturing a flash memory device. In the method, after forming a cell string and source/drain selection transistors, it forms a first oxide film in which a sidewall oxide film and a buffering oxide film are stacked, a nitride film, and a second oxide film for spacer on the overall structure. Then, source/drain contact holes are formed. Thus, the source/drain selection transistors are prevented from being exposed while etching the source/drain contact holes, which enhances the reliability of the flash memory device.

Abstract: A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.

Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

Abstract: A method of manufacturing a high-voltage device DDD (Double Doped Drain) ion implantation process is performed at a tilt angle in order to form a smooth junction profile. Accordingly, the intensity of an electric field can be reduced and breakdown voltage margin can be secured.

Abstract: A method of manufacturing a semiconductor device including at least one step of: forming a transistor on and/or over a semiconductor substrate; forming silicide on and/or over a gate electrode and a source/drain region of the transistor; removing an uppermost oxide film from a spacer of the transistor; and forming a contact stop layer on and/or over the entire surface of the substrate including the gate electrode.

Abstract: Methods of recovering damage on a semiconductor device by performing a hydrogen annealing process are disclosed. An example disclosed method includes forming an STI structure on a semiconductor substrate; forming a gate electrode and spacers on the sidewalls of the gate electrode; implanting ions into source and drain regions and performing a hydrogen annealing process; and performing a thermal treatment for the resulting structure to diffuse and align the ions in the source/drain region.

Abstract: Gate electrodes of semiconductor devices and methods of manufacturing the same are disclosed. An example method comprises: sequentially forming a gate oxide layer and a sacrificial buffer layer on a semiconductor substrate; patterning the sacrificial buffer layer to form an auxiliary pattern; depositing a polysilicon layer; dry etching the polysilicon layer to form a side wall of the polysilicon layer to adjacent the auxiliary pattern; removing the auxiliary pattern; depositing an insulating layer; chemical mechanical polishing to remove a predetermined thickness of the side wall and the insulating layer to thereby complete the gate electrode from the side wall; and removing the insulating layer.

Abstract: A semiconductor process and apparatus use a predetermined sequence of patterning and etching steps to etch a gate stack (62) formed over a substrate (11) and a first spacer structure (42), thereby forming etched gate structures (72, 74) that are physically separated from one another but that control a substrate channel (71) subsequently defined in the substrate (11) by source/drain regions (82, 102, 84, 104) that are implanted around the etched gate structures (72, 74). Depending on how the first spacer structure (42) is positioned and configured, the channel (71) may be controlled to provide either a logical AND gate (100) or logical OR gate (200) functionality.

Abstract: The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled with an electrically conductive trench filling layer. The isolation trench connects to the first doping regions adjoining the second contact for the purpose of realizing a buried contact bypass line.

Abstract: A method of making a magnetic tunnel junction device is disclosed. The magnetic tunnel junction device includes a magnetic tunnel junction stack and an electrically non-conductive spacer in contact with a portion of the magnetic tunnel junction stack. The spacer electrically insulates a portion of the magnetic tunnel junction stack from an electrically conductive material used for a via that is in contact with the magnetic tunnel junction stack and a top conductor. The spacer can also prevent an electrical short between a bottom conductor and the top conductor. The spacer can prevent electrical shorts when the magnetic tunnel junction stack and a self-aligned via are not aligned with each other.

Abstract: The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate insulation film is removed to form an opening that exposes an outside area of the active area, which is outside of the central area where a gate electrode will be formed. A shallow grade layer is formed by implanting impurities into an opening with an energy that does not permit penetration of impurity ions through the gate insulation film.

Abstract: The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.

Abstract: A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. Preferably, the central region is substantially undoped with fluorine and chlorine. The chlorine and/or fluorine can be provided by forming sidewall spacers proximate the opposing lateral edges of the gate, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time effective to diffuse the fluorine or chlorine into the gate oxide layer to beneath the gate.

Abstract: The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating layer pattern is protruded from the edge of the second insulating layer pattern to be covered with the silicon epitaxial layer whose predetermined region is silicided.

Abstract: A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.

Abstract: Semiconductor devices and methods for fabricating a silicide of a semiconductor device are disclosed. An illustrated method comprises: forming a gate electrode; depositing an insulating layer; removing a predetermined portion of the insulating layer in order to expose a portion of the gate electrode; forming silicide on the exposed portion of the gate electrode; and etching the insulating layer while using the silicide as an etching mask.

Abstract: According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a gate stack on an outer surface of a semiconductor body. First and second sidewall bodies are formed on opposing sides of the gate stack. A first recess is formed in an outer surface of the gate stack, and a first dopant is implanted into the gate stack after the first recess is formed. The first dopant diffuses inwardly from the outer surface of the gate stack that defines the first recess. The first dopant diffuses toward an interface between the gate stack and the semiconductor body. The first recess increases the concentration of the first dopant at the interface.

Abstract: Methods of forming silicide layers of a semiconductor device are disclosed. A disclosed method comprises depositing a polysilicon layer, a buffer oxide layer, and a buffer nitride layer on a semiconductor substrate; forming a gate on the semiconductor substrate by removing some portion of the polysilicon layer, the buffer oxide layer, and the buffer nitride layer; forming sidewall spacers on the sidewalls of the gate; forming source and drain regions in the semiconductor substrate by performing an ion implantation process; forming a first silicide layer on the source and drain regions; depositing a first ILD layer over the semiconductor substrate including the gate and the first silicide layer; removing some portion of the first ILD layer to expose the top surface of the gate; and forming a second silicide layer on the gate.

Abstract: There are provided methods of fabricating a semiconductor device having a T-shaped gate and an L-shaped spacer. In the method, an insulating layer and a sacrificial layer are formed in sequence on a semiconductor substrate having a vertical gate pattern. By etching the sacrificial layer, a sacrificial spacer is formed. By etching the insulating layer until an upper surface of at least the vertical gate pattern is exposed, there is formed an L-shaped spacer, which includes a vertical portion located between sidewalls of the vertical gate pattern and the sacrificial spacer, and a horizontal portion extended from the vertical portion and located between the semiconductor substrate and the sacrificial spacer. By selectively etching a part of the vertical portion of the L-shaped spacer, an empty space is formed between upper sidewalls of the vertical gate pattern and the sacrificial spacer.

Abstract: A method of forming contact holes is provided. A substrate having a plurality of device structures is provided. A first dielectric layer and a conductive layer sequentially cover the device structures and the surface of the substrate. A recess is formed in the conductive layer between every two neighboring device structures. A pair of composite spacers is formed in the recess. By using the composite spacers as a mask, a portion of the exposed conductive layer is removed to form a plurality of openings between every two neighboring device structures. A second dielectric layer is then formed on the sidewalls of the openings. A third dielectric layer is formed over the substrate. Portions of the third dielectric layer and the first dielectric layer above the openings are removed to form a plurality of self-aligned contact holes.

Abstract: A method of manufacturing an electronic device including a thin film transistor comprises forming a semiconductor film over an insulating substrate; depositing a first masking layer over the semiconductor film and removing portions of it to form a plurality of holes through it that extend substantially perpendicularly from its upper to its lower surface; patterning the first masking layer in a first pattern; depositing a second masking layer over the first masking layer; patterning the second masking layer to define a second pattern that lies within the area of the first pattern; and implanting the semiconductor film using at least the first masking layer as an implantation mask.

Abstract: A process and structure for forming electrical devices. The process and structure provide for forming an insulating layer on a substrate. A conductive region is then formed in the insulating layer by implanting silicon atoms into the insulating layer. Further, a plurality of different conductive regions can be formed in the insulating layer. An electrical device such as a transistor or a diode can then be formed in each of the conductive regions. Because the conductive regions are formed in a conductive region which is largely electrically isolated from other conductive regions there is little possibility for adjacent devices to cause interference.

Abstract: A method of fabricating a non-volatile memory is described. A substrate is provided and a first dielectric layer, an electron trapping layer and a second dielectric layer are sequentially formed thereon. Each of the stacked gate structures includes a first gate and a cap layer having a gap between every two stacked gate structures. An oxide layer is formed on the sidewalls of the first gate. A portion of the second dielectric layer not covered by the stacked gate structures is removed. A third dielectric layer is further formed on the substrate. A second conductive layer is formed over the substrate, and a portion thereof to form second gates. The second gates and the stacked gate structures form a column of memory cells. A source region and a drain region are formed in the substrate adjacent to two sides of the column of memory cells.

Abstract: A method of manufacturing a MOS transistor, comprising the steps of providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, performing an implantation to form two implanted regions in the semiconductor substrate respectively adjacent to the gate structure, performing an etching process to remove each implanted region and form a trench, and performing a selective epitaxial growth to fill epitaxial crystal into the trenches, thereby forming a source/drain of the MOS transistor.

Abstract: A method forms a semiconductor device from a device that includes a first source region, a first drain region, and a first fin structure that are separated from a second source region, a second drain region, and a second fin structure by an insulating layer. The method may include forming a dielectric layer over the device and removing portions of the dielectric layer to create covered portions and bare portions. The method may also include depositing a gate material over the covered portions and bare portions, doping the first fin structure, the first source region, and the first drain region with a first material, and doping the second fin structure, the second source region, and the second drain region with a second material. The method may further include removing a portion of the gate material over at least one covered portion to form the semiconductor device.

Abstract: A method of manufacturing a semiconductor device includes forming a gate, source/drain extensions, buffer regions, and source/drain regions. The gate is formed over a semiconductor layer, and the source/drain extensions are formed within the semiconductor layer and adjacent the gate. The buffer regions are formed within first amorphous implant regions, and the source/drain regions are formed within second amorphous implant regions. The buffer regions and the source/drain regions are activated using solid-phase epitaxy whereby sidewalls of the activated buffer regions and the activated source/drain regions are substantially vertical.

Abstract: The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: The present invention makes it is possible to provide a manufacturing method of a semiconductor device by which damage by plasma process or doping process during a LDD formation process can be reduced as much as possible. Charge density to be stored in a gate electrode and the damage of an element due to plasma are reduced as much as possible during anisotropic etching of an LDD formation process, by forming an LDD region in the state that a conductive protecting film is formed to cover a whole area of a substrate. Further, damage by charged particles during a process of doping a high concentration of impurity is also reduced.

Abstract: A method for fabricating a transistor in a semiconductor device is disclosed. An example method forms an isolation region in a semiconductor substrate and sequentially deposits a pad oxide layer, a pad nitride layer and a first oxide layer on the substrate and the isolation region. The example method also patterns the first oxide layer and pad nitride layer to form a gate electrode, deposits a doped poly silicon layer, forms a doped polysilicon sidewall on the pad nitride layer and the first oxide layer, etches the pad oxide layer, sequentially deposits and planarizing a gate isolation layer, a gate nitride layer and a metal layer on the substrate to form the gate electrode. In addition, the example method forms a source, a drain, a gate plug, a source plug and a drain plug, respectively.

Abstract: A method of manufacturing a thin film transistor for solving the drawbacks of the prior arts is disclosed. The method includes steps of providing an insulating substrate, sequentially forming a source/drain layer, a primary gate insulating layer, and a first conducting layer on the insulating substrate, etching the first conducting layer to form a primary gate; sequentially forming a secondary gate insulating layer and a second conducting layer on the primary gate; and etching the second conducting layer to form a first secondary gate and a second secondary gate.

Abstract: A new structure is disclosed for semiconductor devices in which contact regions are self-aligned to conductive lines. Openings to a gate oxide layer, in partially fabricated devices on a silicon substrate, have insulating sidewalls. First polysilicon lines disposed against the insulating sidewalls extend from below the top of the openings to the gate oxide layer. Oxide layers are grown over the top and exposed sides of the first polysilicon lines serving to insulate the first polysilicon lines. Polysilicon contact regions are disposed directly over and connect to silicon substrate regions through openings in the gate oxide layer and fill the available volume of the openings. Second polysilicon lines connect to the contact regions and are disposed over the oxide layers grown on the first polysilicon lines.

Abstract: A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.

Abstract: A method, for manufacturing a nonvolatile memory device, includes: forming a gate layer above which a stopper layer is disposed on a semiconductor layer; forming control gates on both side surfaces of the gate layer with an ONO film interposed therebetween; forming an insulating layer over the entire surface; polishing the insulating layer so that the stopper layer is exposed; removing the stopper layer and thereby exposing the top surface of the gate layer; forming a conductive layer above the gate layer and the insulating layer; etching the conductive layer and the gate layer and thereby forming a word line and a word gate and removing the gate layer remained under the etching.

Abstract: An insulating layer (24, 66, 82) is formed over a stack (14) of materials and a semiconductor substrate (12) and an implant is performed through the insulating layer into the semiconductor substrate. In one embodiment, spacers (26) are formed over the insulating layer (24), the insulating layer (24) is etched, and heavily doped regions (36) are formed adjacent the spacers. The spacers (26) are then removed and extension regions (50) and optional halo regions (46) are formed by implanting through the insulating layer (24). In one embodiment, the insulating layer (24) is in contact with the semiconductor substrate (12). In one embodiment, the stack (14) is a gate stack including a gate dielectric (18), a gate electrode (16), and an optional capping layer (22). The insulating layer (24, 66, 82) may include nitrogen, such as silicon nitride and aluminum nitride. In another embodiment, the insulating layer (24, 66, 82) may be hafnium oxide.

Abstract: A process and structure for forming electrical devices. The process and structure provide for forming an insulating layer on a substrate. A conductive region is then formed in the insulating layer by implanting silicon atoms into the insulating layer. Further, a plurality of different conductive regions can be formed in the insulating layer. An electrical device such as a transistor or a diode can then be formed in each of the conductive regions. Because the conductive regions are formed in a conductive region which is largely electrically isolated from other conductive regions there is little possibility for adjacent devices to cause interference.

Abstract: Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device are provided. The method and structure include the following steps. A gate oxide layer, a first semiconductor layer, and an insulating layer are formed sequentially over a provided semiconductor substrate. An etching process is used to etch the insulating layer. A semiconductor spacer is then deposited and used as a self-aligned etching mask. After the self-aligned etching, the insulating layer is removed and an insulating stacked structure is deposited. Finally, a second semiconductor layer is deposited and etched to form the control gate region.

Abstract: A method to form transistors having improved ESD performance in the manufacture of an integrated circuit device is achieved. The method includes providing a SOI substrate with a doped silicon layer and a buried oxide layer. The doped silicon layer has a first conductivity type and overlies the buried oxide layer. Ions are implanted into the SOI substrate to form higher concentration regions in the doped silicon layer. The higher concentration regions have the first conductivity type and are formed substantially below the top surface of the doped silicon layer. MOS gates are formed. These MOS gates include an electrode layer overlying the doped silicon layer with a gate oxide layer therebetween. Source and drain regions are formed in the doped silicon layer to complete the transistors in the manufacture of the integrated circuit device. The source and drain regions contact the higher concentration regions and have a second conductivity type.