Abstract: A semiconductor device may include a first insulating layer disposed on a substrate, a gate electrode disposed on the first insulating layer, and a second insulating layer disposed on the gate electrode and the first insulating layer. The second insulating layer includes a first discharge site.

Abstract: The present disclosure discloses a method of forming a semiconductor layer on a substrate. The method includes patterning the semiconductor layer into a fin structure. The method includes forming a gate dielectric layer and a gate electrode layer over the fin structure. The method includes patterning the gate dielectric layer and the gate electrode layer to form a gate structure in a manner so that the gate structure wraps around a portion of the fin structure. The method includes performing a plurality of implantation processes to form source/drain regions in the fin structure. The plurality of implantation processes are carried out in a manner so that a doping profile across the fin structure is non-uniform, and a first region of the portion of the fin structure that is wrapped around by the gate structure has a lower doping concentration level than other regions of the fin structure.

Abstract: Extension regions 7 are formed through implantation using offset sidewalls 6a of a footing profile as a mask, and sidewalls 9 are formed on the offset sidewalls 6a so that source and drain regions 10 are formed into the sidewall through implantation, so that the extension regions 7 are made separated away from both edges of the gate, contributing to enlargement in an effective gate length, and dealing with the narrowed gate pitch, without increasing the number of processes.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stack structure on a substrate; forming a drain region in the substrate on one side of the gate stack structure; and forming a source region made of GeSn in the substrate on the other side of the gate stack structure; wherein the forming the source region made of GeSn comprises: implanting precursors in the substrate on the other side of the gate stack structure; and performing a laser rapid annealing such that the precursors react to produce GeSn alloy, thereby to constitute a source region; and wherein the step of implanting precursors further comprises: performing a pre-amorphization ion implantation, so as to form an amorphized region in the substrate; and implanting Sn in the amorphized region.

Abstract: The present application discloses a method for manufacturing a semiconductor device, comprising: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; filling successively a gate insulation layer and a metal layer in the T-shape gate trench, wherein the metal layer forms the T-shape metal gate structure. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.

Abstract: First sidewalls are provided on side surfaces of a gate electrode and on regions of a semiconductor substrate which are located on lateral sides of the gate electrode, second sidewalls are provided on the first sidewalls and each second sidewall has a height and a width respectively smaller than a height and a width of the first sidewall, outer sidewalls are provided outside the second sidewalls to cover the second sidewalls, and source and drain regions are provided in regions located on lateral sides of the outer sidewalls. The second sidewalls have a composition containing an atom causing a defect level due to a collision ion being implanted, and the first sidewalls and the third sidewalls have compositions containing no atom causing the defect level.

Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure.

Abstract: One illustrative method disclosed herein includes forming a structure above a semiconductor substrate, performing a conformal deposition process to form a layer of undoped spacer material above the structure, performing an angled ion implant process to form a region of doped spacer material in the layer of undoped spacer material while leaving other portions of the layer of undoped spacer material undoped, and, after performing the angled ion implant process, performing at least one etching process that removes the undoped portions of the layer of undoped spacer material and thereby results in a sidewall spacer comprised of the doped spacer material positioned adjacent at least one side, but not all sides, of the structure.

Abstract: A semiconductor structure includes a gate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided.

Abstract: A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process.

Abstract: When forming metal silicide regions, such as nickel silicide regions, in sophisticated transistors requiring a shallow drain and source dopant profile, superior controllability may be achieved by incorporating a silicide stop layer. To this end, in some illustrative embodiments, a carbon species may be incorporated on the basis of an implantation process in order to significantly modify the metal diffusion during the silicidation process. Consequently, an increased thickness of the metal silicide may be provided, while not unduly increasing the probability of creating contact failures.

Abstract: A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 ? of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.

Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.

Abstract: In aspects of the present invention, a method of forming a semiconductor device is disclosed, wherein amorphous regions are formed at an early stage during fabrication and the amorphous regions are conserved during subsequent processing sequences, and an intermediate semiconductor device structure with amorphous regions are provided at an early stage during fabrication. Herein a gate structure is provided over a semiconductor substrate and amorphous regions are formed adjacent the gate structure. Source/drain extension regions or source/drain regions are formed in the amorphous regions. In some illustrative embodiments, fluorine may be implanted into the amorphous regions. After the source/drain extension regions and/or the source/drain regions are formed, a rapid thermal anneal process is performed.

Abstract: A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a JFET region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench. The second conduction type second source region are formed in the first conduction type first source region. The trench-type source electrode is in contact with the first source region, the second source region, and the first conduction type semiconductor deposition layer to configure a Schottky junction.

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain, and a gate dielectric layer disposed between the substrate and the gate electrode. At least a portion of the gate dielectric layer is extended beyond the gate electrode toward at least one of the source or the drain.

Abstract: Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure.

Abstract: A method comprises providing a semiconductor structure comprising a gate structure provided over a semiconductor region. An ion implantation process is performed. In the ion implantation process, a first portion of the semiconductor region adjacent the gate structure and a second portion of the semiconductor region adjacent the gate structure are amorphized so that a first amorphized region and a second amorphized region are formed adjacent the gate structure. An atomic layer deposition process is performed. The atomic layer deposition process deposits a layer of a material having an intrinsic stress over the semiconductor structure. A temperature at which at least a part of the atomic layer deposition process is performed and a duration of the at least a part of the atomic layer deposition process are selected such that the first amorphized region and the second amorphized region are re-crystallized during the atomic layer deposition process.

Abstract: Sophisticated transistors for semiconductor devices may be formed on the basis of a superior process sequence in which an increased space between closely spaced gate electrode structures may be obtained in combination with a reduced material loss in the active regions. To this end, an offset spacer conventionally used for laterally profiling the drain and source extension regions is omitted and the spacer for the deep drain and source areas may be completely removed.

Abstract: A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer.

Abstract: One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An N-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e18-5e21 ions/cm3.

Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

Abstract: A method for fabricating an ESD protection device . Agate electrode of a core device is formed in a non I/O region and a gate electrode of an ESD protection device is formed in a I/O region. A first photoresist film masks the I/O region and reveals the non I/O region. The first photoresist film includes at least an opening adjacent to the gate electrode of the ESD protection device in the I/O region. A core pocket implantation process using the first photoresist film as an implant mask is performed to implant dopants of a second conductivity type into the I/O region through the opening and into the non I/O region, thereby forming a core pocket doping region in the I/O region and core pocket doping regions in the non I/O region.

Abstract: A method includes forming a first and a second gate stack to cover a first and a second middle portion of a first and a second semiconductor fin, respectively, and performing implantations to implant exposed portions of the first and the second semiconductor fins to form a first and a second n-type doped region, respectively. A portion of each of the first and the second middle portions is protected from the implantations. The first n-type doped region and the second n-type doped region have different gate proximities from edges of the first gate stack and the second stack, respectively. The first and the second n-type doped regions are etched using chlorine radicals to form a first and a second recess, respectively. An epitaxy is performed to re-grow a first semiconductor region and a second semiconductor region in the first recess and the second recess, respectively.

Abstract: A doping method that forms a doped region at a desired location of a three-dimensional (3D) conductive structure, controls the doping depth and doping dose of the doped region relatively easily, has a shallow doping depth, and prevents a floating body effect. A semiconductor device is fabricated using the same doping method. The method includes, forming a conductive structure having a sidewall, exposing a portion of the sidewall of the conductive structure, and forming a doped region in the exposed portion of the sidewall by performing a plasma doping process.

Abstract: An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain.

Abstract: A method of manufacturing a semiconductor device comprises placing a semiconductor substrate in an ashing chamber, the semiconductor substrate having a gate, a silicon nitride gate sidewall offset spacer or a silicon nitride gate sidewall pacer formed thereon, and a photo resist residue remaining on the semiconductor substrate, introducing a gas mixture including D2 or T2 into the ashing chamber, and ashing the photo resist residue using a plasma that is formed from the gas mixture. The gas mixture can include a deuterium gas or a tritium gas having a volume ratio ranging between about 1% and about 20%. Embodiments can reduce Si recess and the loss of silicon nitride thin film during ashing.

Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract: In complex semiconductor devices, the profiling of the deep drain and source regions may be accomplished individually for N-channel transistors and P-channel transistors without requiring any additional process steps by using a sacrificial spacer element as an etch mask and as an implantation mask for incorporating the drain and source dopant species for deep drain and source areas for one type of transistor. On the other hand, the usual main spacer may be used for the incorporation of the deep drain and source regions of the other type of transistor.

Abstract: A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode.

Abstract: Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.

Abstract: A semiconductor device includes a silicon substrate having a protrusion, a gate insulating film formed over an upper surface of the protrusion of the silicon substrate, a gate electrode formed over the gate insulating film, a source/drain region formed in the silicon substrate on the side of the gate electrode, a first side wall formed over the side surface of the protrusion of the silicon substrate, the first side wall containing an insulating material, a second side wall formed over the first side wall, the second side wall having a bottom portion formed below the upper surface of the protrusion of the silicon substrate, the second side wall containing a material having a Young's modulus greater than that of the silicon substrate, and a stress film formed over the gate electrode and the second side wall.

Abstract: By modifying the dielectric liner for a spacer structure so as to exhibit an enhanced diffusion blocking characteristic, for instance by incorporating nitrogen, the out-diffusion of P-dopants, such as boron, into the dielectric material may be significantly reduced. Consequently, transistor performance, especially of P-type transistors, may be significantly enhanced while nevertheless a high degree of compatibility with conventional techniques may be maintained.

Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

Abstract: A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.

Abstract: A transistor and method of making same include a substrate, a conductive gate over the substrate and a channel region in the substrate under the conductive gate. First and second insulating spacers are laterally adjacent to first and second sides of the conductive gate. A source region in the substrate is adjacent to but laterally spaced from the first side of the conductive gate and the first spacer, and a drain region in the substrate is adjacent to but laterally spaced apart from the second side of the conductive gate and the second spacer. First and second LD regions are in the substrate and laterally extend between the channel region and the source or drain regions respectively, each with a portion thereof not disposed under the first and second spacers nor under the conductive gate, and each with a dopant concentration less than that of the source or drain regions.

Abstract: An anneal recipe is provided to tighten the distribution of resistance values in the manufacture of semiconductor integrated circuits. An adjusted amount of dopant is implanted to compensate for a shift in the distribution of resistance values associated with the anneal recipe. The distribution tightening can be effectuated by including an ammonia gas flow in the anneal recipe.

Abstract: Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary well and a counter implant region implanted in the primary well and between the drift drain and the buried layer. The primary well may comprise a first and second implant region with the second implant region at a depth less than the first. The counter implant may be at a depth between the first and second implant regions. The primary well and counter implant region may comprise dopants of the same conductivity type, or both p+-type dopants. A gate may be formed over a portion of a drift drain.

Abstract: A method of forming a semiconductor device including providing a functional gate structure on a channel portion of a semiconductor substrate. A gate sidewall spacer is adjacent to the functional gate structure and an interlevel dielectric layer is present adjacent to the gate sidewall spacer. The upper surface of the gate conductor is recessed relative to the interlevel dielectric layer. A multi-layered cap is formed a recessed surface of the gate structure, wherein at least one layer of the multi-layered cap includes a high-k dielectric material and is present on a sidewall of the gate sidewall spacer at an upper surface of the functional gate structure. Via openings are etched through the interlevel dielectric layer selectively to at least the high-k dielectric material of the multi-layered cap, wherein at least the high-k dielectric material protects a sidewall of the gate conductor.

Abstract: A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device.

Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.

Abstract: A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode.

Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.

Abstract: Methods and apparatus for selectively improving integrated circuit performance are provided. In an example, a method is provided that includes defining a critical portion of an integrated circuit layout that determines the speed of an integrated circuit, identifying at least a part of the critical portion that includes at least one of a halo, lightly doped drain (LDD), and source drain extension (SDE) implant region, and performing a speed push flow process to increase performance of the part of the critical portion that includes the at least one of the halo, the LDD, and the SDE implant region. The resultant integrated circuit can be integrated with a mobile device.

Abstract: LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches.

Abstract: The present disclosure discloses a method of forming a semiconductor layer on a substrate. The method includes patterning the semiconductor layer into a fin structure. The method includes forming a gate dielectric layer and a gate electrode layer over the fin structure. The method includes patterning the gate dielectric layer and the gate electrode layer to form a gate structure in a manner so that the gate structure wraps around a portion of the fin structure. The method includes performing a plurality of implantation processes to form source/drain regions in the fin structure. The plurality of implantation processes are carried out in a manner so that a doping profile across the fin structure is non-uniform, and a first region of the portion of the fin structure that is wrapped around by the gate structure has a lower doping concentration level than other regions of the fin structure.

Abstract: Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary well and a counter implant region implanted in the primary well and between the drift drain and the buried layer. The primary well may comprise a first and second implant region with the second implant region at a depth less than the first. The counter implant may be at a depth between the first and second implant regions. The primary well and counter implant region may comprise dopants of the same conductivity type, or both p+-type dopants. A gate may be formed over a portion of a drift drain.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region.