Plural Doping Steps Patents (Class 438/306)
  • Patent number: 10535768
    Abstract: A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Tsai, Kuo-Feng Yu, Kei-Wei Chen
  • Patent number: 10431666
    Abstract: A semiconductor switch device and a method of making the same. The method includes providing a semiconductor substrate having a major surface and a first semiconductor region having a first conductivity type. The method further includes implanting ions into the first semiconductor region through an opening in a mask positioned over the first semiconductor region, thereby to form a well region located in the first semiconductor region, the well region having a second conductivity type different to the first conductivity type. The method also includes depositing and patterning a gate electrode material on a gate dielectric to form a gate electrode located directly above the well region. The method further includes performing ion implantation to form a source region located in the well region on a first side of the gate, and to form a drain region located outside the well region on a second side of the gate.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: October 1, 2019
    Assignee: NXP B.V.
    Inventors: Mahmoud Shehab Mohammad Al-Sa'di, Petrus Hubertus Cornelis Magnee
  • Patent number: 10249537
    Abstract: A method of making a semiconductor device includes forming a first fin of a first transistor in a substrate; forming a second fin of a second transistor in the substrate; disposing a first doped oxide layer including a first dopant onto the first fin and the second fin, the first dopant being an n-type dopant or a p-type dopant; disposing a mask over the first fin and removing the first doped oxide layer from the second fin; removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first doped oxide layer covering the first fin and directly onto the second fin, the second doped oxide layer including an n-type dopant or a p-type dopant that is different than the first dopant; and annealing to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10157932
    Abstract: A semiconductor device includes: a memory transistor including a first silicon oxide film, a first silicon nitride film, a second silicon oxide film, and a first gate electrode that are disposed in sequence on a substrate; and a MOS transistor including a third silicon oxide film and a second gate electrode that are disposed in sequence on the substrate. The memory transistor has a side wall including an extending portion of the first silicon oxide film, a second silicon nitride film that is in contact with the first silicon nitride film, and a fourth silicon oxide film that are disposed in sequence on the substrate, and the MOS transistor has a side wall including a fifth silicon oxide film that is disposed on the substrate.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: December 18, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kunio Watanabe, Masaki Okuyama
  • Patent number: 9748392
    Abstract: An angled gas cluster ion beam is used for each sidewall and top of a fin (two applications) to form work-function metal layer(s) only on the sidewalls and top of each fin.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanzhen Wang, Jidong Huang, Hui Zang
  • Patent number: 9704970
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: July 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen
  • Patent number: 9679892
    Abstract: A reverse blocking semiconductor device is manufactured by introducing impurities of a first conductivity type into a semiconductor substrate of the first conductivity type through a process surface to obtain a process layer extending into the semiconductor substrate up to a first depth, and introducing impurities of a second, complementary conductivity type into the semiconductor substrate through openings of an impurity mask provided on the process surface to obtain emitter zones of the second conductivity type extending up to a second depth deeper than the first depth and channels of the first conductivity type between the emitter zones. Exposed portions of the process layer are removed above the emitter zones.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: June 13, 2017
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Roman Baburske, Christian Jaeger, Hans-Joachim Schulze
  • Patent number: 9680015
    Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device structure includes forming a spacer layer material over a substrate and over gate structures defined in a first polarity type region and a second polarity type region; selectively etching the spacer layer material in the first polarity type region to form first gate sidewall spacers; forming first epitaxially grown source/drain (SD) regions in the first polarity type region; selectively forming a protection layer only on exposed surfaces of the first SD regions, so as not to increase a thickness of the spacer layer material in the second polarity type region; forming a masking layer over the first polarity type region, and etching the spacer layer material in the second polarity type region to form second gate sidewall spacers; and removing the masking layer and forming second epitaxially grown SD regions in the second polarity type region.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: June 13, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ali Khakifirooz, Richard S. Wise
  • Patent number: 9647131
    Abstract: The semiconductor device includes a first conductive layer over a substrate; an oxide semiconductor layer which covers the first conductive layer; a second conductive layer in a region which is not overlapped with the first conductive layer over the oxide semiconductor layer; an insulating layer which covers the oxide semiconductor layer and the second conductive layer; and a third conductive layer in a region including at least a region which is not overlapped with the first conductive layer or the second conductive layer over the insulating layer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: May 9, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kei Takahashi, Yoshiaki Ito
  • Patent number: 9564437
    Abstract: A method of making a semiconductor device includes forming a first fin of a first transistor in a substrate; forming a second fin of a second transistor in the substrate; disposing a first doped oxide layer including a first dopant onto the first fin and the second fin, the first dopant being an n-type dopant or a p-type dopant; disposing a mask over the first fin and removing the first doped oxide layer from the second fin; removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first doped oxide layer covering the first fin and directly onto the second fin, the second doped oxide layer including an n-type dopant or a p-type dopant that is different than the first dopant; and annealing to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: February 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 9425285
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen
  • Patent number: 9379211
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen
  • Patent number: 9330978
    Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, a dummy gate electrode, and a first impurity diffusion region. The semiconductor substrate has first and second grooves. The gate electrode is in the first groove. The dummy gate electrode is in the second groove. The dummy gate electrode has a first top surface. The first impurity diffusion region in the semiconductor substrate is positioned between the first and second grooves. The first top surface is positioned at a lower level than a bottom of the first impurity diffusion region.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: May 3, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Koji Taniguchi
  • Patent number: 9312181
    Abstract: The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed on the substrate to form a trench, forming a preliminary device isolation pattern filling the trench and including first and second regions having first thicknesses, forming a second mask pattern on the first region, etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form a second region having a second thickness smaller than the first thickness, removing the first and second mask patterns, and etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns. An electronic device including a semiconductor device and a manufacturing method thereof are also disclosed.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: April 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Joon Choi, Myeongcheol Kim, Cheol Kim, GeumJung Seong, Hak-Sun Lee, Haegeon Jung, Ji-Eun Han
  • Patent number: 9263580
    Abstract: One method disclosed includes, among other things, forming a fin structure comprised of a semiconductor material, a first epi semiconductor material and a second epi semiconductor material, forming a sacrificial gate structure above the fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one etching process to remove the portions of the fin structure positioned laterally outside of the sidewall spacer so as to thereby define a fin cavity in the source/drain regions of the device and to expose edges of the fin structure positioned under the sidewall spacer, and performing an epitaxial deposition process to form an epi etch stop layer on the exposed edges of the fin structure positioned under the sidewall spacer and within the fin cavity.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: February 16, 2016
    Assignees: GLOBALFOUNDRIES Inc., STMICROELECTRONICS, Inc.
    Inventors: Ajey Poovannummoottil Jacob, Nicolas Loubet
  • Patent number: 9257520
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: February 9, 2016
    Assignee: Samsung Electronics Co, Ltd.
    Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
  • Patent number: 9196544
    Abstract: Integrated circuits with selectively stressed semiconductor-on-insulator (SOI) body contacts and methods for fabricating integrated circuits with selectively stressed SOI body contacts are provided. An exemplary method for fabricating an integrated circuit includes forming a channel region and a body contact overlying and/or in an SOI substrate. Further, the method includes selectively applying a first stress to the source/drain region in a longitudinal direction. Also, the method includes selectively applying a second stress to the body contact in a lateral direction perpendicular to the longitudinal direction.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: November 24, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Kheng Chok Tee, Meijun Lu, Kam Chew Leong
  • Patent number: 9099434
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: August 4, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Guowei Zhang, Purakh Raj Verma, Baofu Zhu
  • Patent number: 9059202
    Abstract: A Metal-Oxide-Semiconductor (MOS) device is disclosed. The MOS device includes a substrate, a well region formed in the substrate, and a gate located on the substrate. The MOS device also includes a first lightly-doped region arranged in the well region at a first side of the gate and overlapping with the gate, and a second lightly-doped region arranged in the well region at a second side of the gate and overlapping with the gate. Further, the MOS device includes a first heavily-doped region formed in the first lightly-doped region, and a second heavily-doped region formed in the second lightly-doped region. The MOS device also includes a first high-low-voltage gate oxide boundary arranged between the first heavily-doped region and the gate, and a second high-low-voltage gate oxide boundary arranged between the second heavily-doped region and the gate.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: June 16, 2015
    Assignees: CSMC TECHNOLOGIES FAB1 CO., LTD., CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Yan Jin
  • Publication number: 20150129938
    Abstract: A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mao-Lin Huang, Chien-Hsun Wang, Chun-Hsiung Lin, Meng-Ku Chen, Li-Ting Wang, Hung-Ta Lin
  • Patent number: 9006802
    Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gin-Chen Huang, Tsai-Fu Hsiao, Ching-Hong Jiang, Neng-Kuo Chen, Hongfa Luan, Sey-Ping Sun, Clement Hsingjen Wann
  • Publication number: 20150097238
    Abstract: A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region. A pocket may be disposed in a drain extension region and configured to establish a depletion region along an edge of a gate structure.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 9, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zhihong Zhang, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 9000540
    Abstract: The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Sunamura, Naoya Inoue, Kishou Kaneko
  • Patent number: 8999795
    Abstract: An asymmetrical field effect transistor (FET) device includes a semiconductor substrate, a buried oxide layer disposed on the semiconductor substrate, an extended source region disposed on the buried oxide layer and a drain region disposed on the buried oxide layer. The asymmetrical FET device also includes a silicon on insulator region disposed between the extended source region and the drain region and a gate region disposed above the extended source region and the silicon on insulator region.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8993401
    Abstract: An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: March 31, 2015
    Inventors: Walid M. Hafez, Chia-Hong Jan, Anisur Rahman
  • Patent number: 8987106
    Abstract: A semiconductor device manufacturing method includes forming a channel dope layer having a first electric conductive-type inside of a semiconductor substrate, the channel dope layer being formed in a region except for a drain impurity region where dopant impurities for forming a low-concentration drain region are introduced, and the channel dope layer being separated from the drain impurity region; forming a gate electrode on the semiconductor substrate via a gate insulating film; and forming a low-concentration source region inside of the semiconductor substrate on a first side of the gate electrode, and forming a low-concentration drain region in the drain impurity region of the semiconductor substrate on a second side of the gate electrode, by introducing second electric conductive dopant impurities inside of the semiconductor substrate with the gate electrode as a mask.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: March 24, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masashi Shima
  • Patent number: 8981475
    Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) comprises a semiconductor substrate having an STI structure in a top surface of the substrate, a drift region below the STI structure, and a source region and a drain region on opposite sides of the STI structure. A gate conductor is on the substrate over a gap between the STI structure and the source region and partially overlaps the drift region. A conformal dielectric layer is on the top surface and forms a mesa above the gate conductor. The conformal dielectric layer has a conformal etch-stop layer embedded therein. Contact studs extend through the dielectric layer and the etch-stop layer, and are connected to the source region, drain region, and gate conductor. A source electrode contacts the source contact stud, a gate electrode contacts the gate contact stud, and a drain electrode contacts the drain contact stud. A drift electrode is over the drift region.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Santosh Sharma, Yun Shi, Anthony K. Stamper
  • Patent number: 8980719
    Abstract: An embodiment of the disclosure includes doping a FinFET. A dopant-rich layer comprising an dopant is formed on a top surface and sidewalls of a semiconductor fin of a substrate. A cap layer is formed to cover the dopant-rich layer. The substrate is annealed to drives the dopant from the dopant-rich layer into the semiconductor fin.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Yu-Lien Huang, De-Wei Yu
  • Patent number: 8969160
    Abstract: The present invention is related to microelectronic device technologies. A method for making an asymmetric source-drain field-effect transistor is disclosed. A unique asymmetric source-drain field-effect transistor structure is formed by changing ion implantation tilt angles to control the locations of doped regions formed by two ion implantation processes. The asymmetric source-drain field-effect transistor has structurally asymmetric source/drain regions, one of which is formed of a P-N junction while the other one being formed of a mixed junction, the mixed junction being a mixture of a Schottky junction and a P-N junction.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: March 3, 2015
    Assignee: Fudan University
    Inventors: Yinghua Piao, Dongping Wu, Shili Zhang
  • Patent number: 8963243
    Abstract: The p-channel LDMOS transistor comprises a semiconductor substrate (1), an n well (2) of n-type conductivity in the substrate, and a p well (3) of p-type conductivity in the n well. A portion of the n well is located under the p well. A drain region (4) of p-type conductivity is arranged in the p well, and a source region (9) of p-type conductivity is arranged in the n well. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) is arranged on the gate dielectric. A body contact region (14) of n-type conductivity is arranged in the n well. A p implant region (17) is arranged in the n well under the p well in the vicinity of the p well. The p implant region locally compensates n-type dopants of the n well.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: February 24, 2015
    Assignee: AMS AG
    Inventors: Jong Mun Park, Martin Knaipp
  • Patent number: 8941121
    Abstract: A first region of a silicon carbide layer constitutes a first surface, and is of a first conductivity type. A second region is provided on the first region, and is of a second conductivity type. A third region is provided on the second region, and is of the first conductivity type. A fourth region is provided in the first region, located away from each of the first surface and the second region, and is of the second conductivity type. A gate insulation film is provided on the second region so as to connect the first region with the third region. A gate electrode is provided on the gate insulation film. A first electrode is provided beneath the first region. A second electrode is provided on the third region.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: January 27, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideki Hayashi, Takeyoshi Masuda
  • Patent number: 8936980
    Abstract: Method and apparatus for providing a lateral double-diffused MOSFET (LDMOS) transistor having a dual gate. The dual gate includes a first gate and a second gate. The first gate includes a first oxide layer formed over a substrate, and the second gate includes a second oxide layer formed over the substrate. The first gate is located a pre-determined distance from the second gate. A digitally implemented voltage regulator is also provided that includes a switching circuit having a dual gate LDMOS transistor.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: January 20, 2015
    Assignee: Volterra Semiconductor LLC
    Inventors: Marco A. Zuniga, Budong You
  • Publication number: 20150001594
    Abstract: Methods for forming stacking faults in sources, or sources and drains, of TFETs to improve tunneling efficiency and the resulting devices are disclosed. Embodiments may include designating areas within a substrate that will subsequently correspond to a source region and a drain region, selectively forming a stacking fault within the substrate corresponding to the source region, and forming a tunneling field-effect transistor incorporating the source region and the drain region.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Yanxiang LIU, Min-hwa CHI
  • Patent number: 8900961
    Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ashima B. Chakravarti, Anthony I. Chou, Toshiharu Furukawa, Steven J. Holmes, Wesley C. Natzle
  • Patent number: 8901665
    Abstract: The present disclosure provides a method of semiconductor fabrication including forming an inter-layer dielectric (ILD) layer on a semiconductor substrate. The ILD layer has an opening defined by sidewalls of the ILD layer. A spacer element is formed on the sidewalls of the ILD layer. A gate structure is formed in the opening adjacent the spacer element. In an embodiment, the sidewall spacer also for a decrease in the dimensions (e.g., length) of the gate structure formed in the opening.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Pei-Shan Chien, Yung-Ta Li, Chan Syun Yang
  • Patent number: 8889518
    Abstract: The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on a p-type substrate, and an asymmetric conductive spacer which acts as its gate. The LDMOS transistor also includes a source and a drain region on either side of the asymmetric conductive spacer, and a channel region formed by ion-implantation on the asymmetric conductive spacer. The height of the asymmetric conductive spacer increases from the source region to the drain region. The channel region is essentially completely under the asymmetric conductive spacer and has smaller length than that of the channel region of the prior art LDMOS transistors. The LDMOS transistor of the present invention also includes a field oxide layer surrounding the active region of the transistor, and a thin dielectric layer isolating the asymmetric conductive spacer from the n-type epitaxial layer.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: November 18, 2014
    Assignee: Micrel, Inc.
    Inventors: Martin Alter, Paul McKay Moore
  • Patent number: 8877599
    Abstract: A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ziwei Fang, Tsan-Chun Wang, De-Wei Yu
  • Patent number: 8865557
    Abstract: In an embodiment of the invention, a method of forming an NMOS (n-type metal-oxide semiconductor) transistor is disclosed. A dual mask pattern is used to ion-implant source/drain regions of the NMOS transistor. The first mask allows first doses of As (arsenic), P (phosphorous) and N (Nitrogen) to be ion-implanted. After these doses are ion-implanted, a high temperature (900-1050 C) spike anneal is performed to activate the formed source/drains. A second mask allows a second dose of phosphorus to be implanted in the source/drain regions. The second dose of the phosphorus is typically higher than the first dose of phosphorus. The second dose of phosphorus lowers the Rsd (resistance of the source and drain regions) and dopes n-type poly-silicon blocks.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: October 21, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Mahalingam Nandakumar
  • Patent number: 8859408
    Abstract: Generally, the present disclosure is directed to methods of stabilizing metal silicide contact regions formed in a silicon-germanium active area of a semiconductor device, and devices comprising stabilized metal silicides. One illustrative method disclosed herein includes performing an activation anneal to activate dopants implanted in an active area of a semiconductor device, wherein the active area comprises germanium. Additionally, the method includes, among other things, performing an ion implantation process to implant ions into the active area after performing the activation anneal, forming a metal silicide contact region in the active area, and forming a conductive contact element to the metal silicide contact region.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: October 14, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Clemens Fitz, Tom Herrmann
  • Patent number: 8859377
    Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: October 14, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Mahalingam Nandakumar, Wayne Bather, Narendra Singh Mehta
  • Patent number: 8853674
    Abstract: A tunneling field effect transistor structure and a method for forming the same are provided. The tunneling field effect transistor structure comprises: a substrate; a plurality of convex structures formed on the substrate, every two adjacent convex structures being separated by a predetermined cavity less than 30 nm in width, the convex structures comprising a plurality of sets, and each set comprising more than two convex structures; a plurality of floated films formed on tops of the convex structures, each floated film corresponding to one set of convex structures, a region of each floated film corresponding to a top of an intermediate convex structure in each set being formed as a channel region, and regions of the each floated film at both sides of the channel region are formed as a source region and a drain region with opposite conductivity types respectively; and a gate stack formed on each channel region.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: October 7, 2014
    Assignee: Tsinghua University
    Inventors: Ning Cui, Renrong Liang, Jing Wang, Jun Xu
  • Patent number: 8846461
    Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Hsin Lin, Weng Chang, Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Ming-Hua Yu
  • Publication number: 20140273369
    Abstract: In one example, the method disclosed herein includes forming at least one fin for a FinFET device in a semiconducting substrate, performing at least one process operation to form a region in the at least one fin that contains a metal diffusion inhibiting material, depositing a layer of metal on the region in the at least one fin and forming a metal silicide region on the at least one fin.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Andy C. Wei, Shao Ming Koh
  • Publication number: 20140273370
    Abstract: When forming semiconductor devices including transistors with different threshold voltages, the different threshold voltages of transistors of the same conductivity type are substantially defined by performing different halo implantations. As the other implantations performed typically in the same manufacturing step, such as pre-amorphization, source and drain extension implantation and extra diffusion engineering implantations, may be identical for different threshold voltages, these implantations, in addition to a common halo base implantation, may be performed for all transistors of the same conductivity type in a common implantation sequence. Higher threshold voltages of specific transistors may be subsequently achieved by an additional low-dose halo implantation while the other transistors are covered by a resist mask. Thus, the amount of atoms of the implant species in the required resist masks is reduced so that removal of the resist masks is facilitated.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: GLOBAL FOUNDRIES INC.
    Inventors: Martin Gerhardt, Stefan Flachowsky, Matthias Kessler
  • Patent number: 8835270
    Abstract: In an embodiment of the invention, a method of forming an NMOS (n-type metal-oxide semiconductor) transistor is disclosed. A dual mask pattern is used to ion-implant source/drain regions of the NMOS transistor. The first mask allows first doses of As (arsenic), P (phosphorous) and N (Nitrogen) to be ion-implanted. After these doses are ion-implanted, a high temperature (900-1050 C) spike anneal is performed to activate the formed source/drains. A second mask allows a second dose of phosphorus to be implanted in the source/drain regions. The second dose of the phosphorus is typically higher than the first dose of phosphorus. The second dose of phosphorus lowers the Rsd (resistance of the source and drain regions) and dopes n-type poly-silicon blocks.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: September 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Mahalingam Nandakumar
  • Patent number: 8829615
    Abstract: A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: September 9, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Chien-Chung Chen, Ming-Tung Lee, Shih-Chin Lien, Shyi-Yuan Wu
  • Patent number: 8828834
    Abstract: One illustrative method disclosed herein includes forming a plurality of layers of material above a semiconducting substrate, wherein the plurality of layers of material will comprise a gate structure for a transistor, performing a fluorine ion implantation process to implant fluorine ions into at least one of the plurality of layers of material, performing at least one ion implantation process to implant one of a P-type dopant material or an N-type dopant material into the substrate to form source/drain regions for the transistor, and performing an anneal process after the fluorine ion implantation process and the at least one ion implantation process have been performed.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: September 9, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shesh Mani Pandey, Shiang Yang Ong, Jan Hoentschel
  • Patent number: 8809955
    Abstract: Semiconductor structures and methods for manufacturing the same are disclosed. The semiconductor structure comprises: a gate stack formed on a semiconductor substrate; a super-steep retrograde island embedded in said semiconductor substrate and self-aligned with said gate stack; and a counter doped region embedded in said super-steep retrograde island, wherein said counter doped region has a doping type opposite to a doping type of said super-steep retrograde island. The semiconductor structures and the methods for manufacturing the same facilitate alleviating short channel effects.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: August 19, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Binneng Wu, Weiping Xiao, Hao Wu, Qingqing Liang
  • Patent number: 8796123
    Abstract: An impurity of a first conductivity type is implanted onto a silicon carbide substrate through an opening in a mask layer. First and second films made of first and second materials respectively are formed. It is sensed that etching of the first material is performed during anisotropic etching, and then anisotropic etching is stopped. An impurity of a second conductivity type is implanted onto the silicon carbide substrate through the opening narrowed by the first and second films. Thus, the impurity regions can be formed in an accurately self-aligned manner.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 5, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shunsuke Yamada, Takeyoshi Masuda
  • Patent number: 8785287
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: July 22, 2014
    Assignee: Globalfoundries Singapore Pte, Ltd.
    Inventors: Chunshan Yin, Guangyu Huang, Elgin Quek, Jae Gon Lee, Kian Ming Tan