Abstract: A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 ?m or less, a p?type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p?type semiconductor region is formed under a n+type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.

Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer; and forming a fin field-effect transistor (FinFET) including implanting the semiconductor wafer using a hot-implantation to form an implanted region in the FinFET. The implanted region comprises a region selected from the group consisting essentially of a lightly doped source and drain region, a pocket region, and a deep source drain region.

Abstract: Embodiments of the invention generally provide methods for end point detection at predetermined dopant concentrations during plasma doping processes. In one embodiment, a method includes positioning a substrate within a process chamber, generating a plasma above the substrate and transmitting a light generated by the plasma through the substrate, wherein the light enters the topside and exits the backside of the substrate, and receiving the light by a sensor positioned below the substrate. The method further provides generating a signal proportional to the light received by the sensor, implanting the substrate with a dopant during a doping process, generating multiple light signals proportional to a decreasing amount of the light received by the sensor during the doping process, generating an end point signal proportional to the light received by the sensor once the substrate has a final dopant concentration, and ceasing the doping process.

Abstract: By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.

Abstract: A semiconductor device having a DRAM region and a logic region embedded together therein, including a first transistor formed in a DRAM region, and having a first source/drain region containing at least a first impurity, and a second transistor formed in a logic region, and having a second source/drain region containing at least a second impurity, wherein each of the first source/drain region and the second source/drain region has a silicide layer respectively formed in the surficial portion thereof, and the first source/drain region has a junction depth which is determined by an impurity and is deeper than the junction depth of the second source/drain region.

Abstract: A method of fabricating a transistor (10) comprises forming source and drain regions (46) and (47) using a first sidewall (42) and (43) as a mask and forming a deep blanket source and drain regions (54) and (56) using a second sidewall (50) and (51) as a mask, the second sidewall (50) and (51) comprising at least part of the first sidewall (42) and (43).

Abstract: A method of plasma immersion ion implantation of a workpiece having a photoresist mask on its top surface prevents photoresist failure from carbonization of the photoresist. The method includes performing successive ion implantation sub-steps, each of the ion implantation sub-steps having a time duration over which only a fractional top portion of the photoresist layer is damaged by ion implantation. After each one of the successive ion implantation sub-steps, the fractional top portion of the photoresist is removed while leaving the remaining portion of the photoresist layer in place by performing an ashing sub-step. The number of the successive ion implantation sub-steps is sufficient to reach a predetermined ion implantation dose in the workpiece.

Abstract: The method includes the steps of forming a gate insulating film over a first conductivity-type layer surface of a semiconductor substrate, implanting a second conductivity-type impurity into the first conductivity-type layer located on both sides adjacent to a conductive layer forming predetermined region, forming a conductive layer over the gate insulating film surface located to cover the first conductivity-type layer surface with no impurity implanted therein and the partial regions surface of the pair of low-concentration diffusion layers adjacent to the first conductivity-type layer, implanting a second conductivity-type impurity into regions uncovered with the conductive layer, of the pair of low-concentration diffusion layers to contact source and drain electrodes, and forming slits to divide regions lying on the sides of the high-concentration diffusion layers, each of which is provided to contact at least the drain electrode of the conductive layer located over the low-concentration diffusion layers,

Abstract: A device isolation film is formed in a semiconductor substrate at a border portion between a first region and a second region for defining a first active region in the first region and a second active region in the second region. A gate insulating film and a gate electrode is formed over the semiconductor substrate in the first region. A first photoresist film covering the second region and having an opening exposing the first active region and having an edge on the border portion of the opening positioned nearer the second active region than a middle of the device isolation film is formed over the semiconductor substrate with the gate electrode. Impurity ions are implanted from a direction tilted from a normal direction of the semiconductor substrate with the first photoresist film and the gate electrode as a mask to form pocket regions in the semiconductor substrate on both sides of the gate electrodes.

Abstract: A power device with improved reliability and a method for producing the same is disclosed. One embodiment provides an active area having an electrical power dissipation characteristic, a metallization layer portion configured with respect to the active area so that the dissipation characteristic of the active area results in heating the metallization layer portion, the metallization layer portion being formed as a connected region. The metallization layer portion has at least one hole, fully extending through the metal layer and having a dielectric. The at least one hole is arranged so that each location of the metal layer portion is connected electrically to each other location via the metallization material of the metal layer portion.

Abstract: An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate stack formed in or on the surface including a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region are on opposing sides of the gate stack. An In region having a retrograde profile is under at least a portion of the channel region. The retrograde profile includes (i) a surface In concentration at a semiconductor surface interface with the gate dielectric of less than 5×1016 cm?3, (ii) a peak In concentration at least 20 nm from the semiconductor surface below the gate dielectric, and wherein (iii) the peak In concentration is at least two (2) orders of magnitude higher than the In concentration at the semiconductor surface interface.

Abstract: A semiconductor device includes a structure in which a difference in height between a cell region and a peripheral region are formed so that a buried gate structure of the cell region is substantially equal in height to the gate of the peripheral region, whereby a bit line and a storage node contact can be more easily formed in the cell region and parasitic capacitance can be decreased decreased. The semiconductor device includes a cell region including a gate buried in a substrate, and a peripheral region adjacent to the cell region, where a step height between a surface of the cell and a surface of the peripheral region is generated.

Abstract: A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are implanted into the substrate adjacent the dummy gate. Dummy spacers are formed along dummy gate sidewalls and over a portion of the source-drain extensions. Source-drain regions are implanted. Insulating spacers are formed on dummy oxide spacer sidewalls. A conductive layer is formed over the source-drain regions. The conductive layer is annealed to form contacts to the source-drain regions. The dummy gate and the dummy oxide spacers are removed to form a gate opening. A passivation layer is in-situ deposited in the gate opening. The surface of the passivation layer is oxidized to create an oxide layer. A dielectric layer is ex-situ deposited over the oxide layer. A gate metal is deposited over the dielectric layer to form a gate stack in the gate opening.

Abstract: The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on a p-type substrate, and an asymmetric conductive spacer which acts as its gate. The LDMOS transistor also includes a source and a drain region on either side of the asymmetric conductive spacer, and a channel region formed by ion-implantation on the asymmetric conductive spacer. The height of the asymmetric conductive spacer increases from the source region to the drain region. The channel region is essentially completely under the asymmetric conductive spacer and has smaller length than that of the channel region of the prior art LDMOS transistors. The LDMOS transistor of the present invention also includes a field oxide layer surrounding the active region of the transistor, and a thin dielectric layer isolating the asymmetric conductive spacer from the n-type epitaxial layer.

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.

Abstract: The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

Abstract: A manufacturing method of a NOR flash memory with phosphorous and arsenic ion implantations mainly implants both phosphorous and arsenic ions on a drain area of a transistor memory unit, and controls specific energy and dosage for the implantation to reduce the defects of a memory device and improve the yield rate of the NOR flash memory.

Abstract: A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.

Abstract: Circuits and methods for providing a dual gate oxide (DGO) embedded SRAM with additional logic portions, where the logic and the embedded SRAM have NMOS transistors having a common gate dielectric thickness but have different lightly doped drain (LDD) implantations formed using different LDD masks to provide optimum transistor operation. In an embodiment, a first embedded SRAM is a single port device and a second embedded SRAM is a dual port device having a separate read port. In certain embodiments, the second SRAM includes NMOS transistors having LDD implants formed using the logic portion LDD mask. Transistors formed with the logic portion LDD mask are faster and have lower Vt than transistors formed using a SRAM LDD mask. Dual core devices having multiple embedded SRAM arrays are disclosed. Methods for making the embedded SRAM are also disclosed.

Abstract: A semiconductor device having a DRAM region and a logic region embedded together therein, including a first transistor formed in a DRAM region, and having a first source/drain region containing arsenic and phosphorus as impurities; and a second transistor formed in a logic region, and having a second source/drain region containing at least arsenic as an impurity, wherein each of the first source/drain region and the second source/drain region has a silicide layer respectively formed in the surficial portion thereof, and the first source/drain region has a junction depth which is determined by phosphorus and is deeper than the junction depth of the second source/drain region.

Abstract: An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region is opposing sides of the gate stack. At least one compressive strain inducing region including at least one specie selected from Ge, Sn and Pb is located in at least a portion of the source and drain regions of the PMOS transistors, wherein the strain inducing region provides ?1010 dislocation lines/cm2 and an active concentration of the compressive strain inducing specie that is above a solid solubility limit for the compressive strain inducing specie in the compressive strain inducing region.

Abstract: A method of manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate having a wide band gap superficial semiconductor layer, including the steps of forming a screening structure on the superficial semiconductor layer that leaves a plurality of areas of the superficial semiconductor layer exposed, carrying out at least a first ion implantation of a first type of dopant in the superficial semiconductor layer for forming at least one deep implanted region, carrying out at least a second ion implantation of the first type of dopant in the superficial semiconductor layer for forming at least one implanted body region of the MOS transistor aligned with the deep implanted region, carrying out at least one ion implantation of a second type of dopant in the superficial semiconductor layer for forming at least an implanted source region of the MOS transistor inside the at least one implanted body region, and a low budget activation thermal process of the first and second dopant types sui

Abstract: According to an aspect of an embodiment, a semiconductor device has a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode formed on the gate insulating film, an impurity diffusion region formed in an area of the semiconductor substrate adjacent to the gate electrode to a first depth to the semiconductor substrate, the impurity diffusion region containing impurity, an inert substance containing region formed in the area of the semiconductor substrate to a second depth deeper than the first depth, the inert substance containing region containing an inert substance, and a diffusion suppressing region formed in the area of the semiconductor substrate to a third depth deeper than the second depth, the diffusion suppressing region containing a diffusion suppressing substance suppressing diffusion of the impurity.

Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.

Abstract: A method of monolithically fabricating an LDMOS transistor with a fabrication process that is compatible with a sub-micron CMOS fabrication process. The specification further describes an LDMOS transistor. The LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The method includes forming a gate layer on a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; forming a second oxide layer on the first oxide layer; exposing the first oxide layer by removing the second oxide layer other than on side surfaces of the gate layer by etching using a photoresist as a mask; and forming junctions in source/drain regions by implanting a high concentration of N-type ions and/or a high concentration of P-type ions using the second oxide layer as a sidewall mask.

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.

Abstract: A non-volatile memory is described, which includes gate structures, doped regions, second spacers and contact plugs. The gate structures are disposed on the substrate, each of which includes a control gate and a gate dielectric layer. The control gates are disposed on the substrate, and two first spacers are deployed at both sides of each control gate. The gate dielectric layers are disposed between the control gates and the substrate, respectively. Each of the doped regions is formed in the substrate between two adjacent gate structures. The second spacers are disposed on the sidewalls of the gate structures. The contact plugs are formed between two adjacent second spacers, respectively.

Abstract: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.

Abstract: A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel.

Abstract: An FET and method of fabricating an FET. The method includes forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of the gate dielectric layer; forming a source and a drain in the silicon region and separated by a channel region under the gate electrode, the source having a source extension extending under the gate electrode and the drain having a drain extension extending under the gate electrode, the source, source extension, drain and drain extension doped a first type; and forming a source delta region contained entirely within the source and forming a drain delta region contained entirely within the drain, the delta source region and the delta drain region doped a second dopant type, the second dopant type opposite from the first dopant type.

Abstract: A fabrication method of a semiconductor device includes: forming a gate insulating film and a gate electrode on an N type well; forming first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger than silicon and exhibiting P type conductivity; forming second source/drain regions by implanting a second element in the regions of the N type well on the both sides of the gate electrode, the second element being smaller than silicon and exhibiting P type conductivity; and forming a metal silicide layer on the source/drain regions.

Abstract: A drift of a high voltage transistor formed using an STI (shallow trench isolation).

Abstract: A semiconductor device having an EDMOS transistor and a method for forming the same are provided. The semiconductor device includes source and drain regions formed separately in a semiconductor substrate, a first gate insulating layer filling a trench formed in the substrate between the source and drain regions, the first gate insulating layer being adjacent to the drain region and separated from the source region, a second gate insulating layer formed over the substrate between the first gate insulating layer and the source region, the second gate insulating layer being thinner than the first gate insulating layer, a gate electrode formed over the first and second gate insulating layers, and a doped drift region formed in the substrate under the first gate insulating layer, the doped drift region being in contact with the drain region. This reduces the planar area of the EDMOS transistor, thereby achieving highly integrated semiconductor devices.

Abstract: Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped regions of a first conductivity type in the substrate on drain sides of the stacked gate structures. The source implantations create higher doped regions of the first conductivity type in the substrate on source sides of the stacked gate structures.

Abstract: A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide are formed in the recess and lightly doped source and drain extension regions contiguous with the laterally spaced source and drain regions are optionally formed adjacent the recess. Programming of the recessed dielectric antifuse is performed by application of power to the gate and at least one of the source region and the drain region to breakdown the dielectric, which minimizes resistance between the gate and the channel.

Abstract: A process of fabricating a transistor employs a relatively thicker sacrificial nitride layer that reduces the time and cost associated with chemical-mechanical polish (CMP) processes by reducing the topography associated with the transistor. The process includes forming the gate oxide region and a field oxide region on a substrate. A polysilicon layer is formed on the gate oxide region and the field oxide region. A sacrificial nitride layer is formed on the polysilicon layer, wherein the sacrificial nitride layer has a thickness approximately equal to or greater than a thickness of the gate oxide region. A polysilicon gate is formed by selectively removing portions of the polysilicon layer and the sacrificial layer to expose a portion of the gate oxide region adjacent to the polysilicon gate. Source/drain regions are formed adjacent to the polysilicon gate using lightly-doped drain (LDD) implantation. A spacer layer is formed over the polysilicon gate and source/drain regions.

Abstract: Insulated-gate field-effect transistors (“IGFETs”), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET (100, 102, 112, 114, 124, or 126) has a pair of source/drain zones laterally separated by a channel zone of body material of the empty well (180, 182, 192, 194, 204, or 206). A gate electrode overlies a gate dielectric layer above the channel zone. Each source/drain zone (240, 242, 280, 282, 520, 522, 550, 552, 720, 722, 752, or 752) has a main portion (240M, 242M, 280M, 282M, 520M, 522M, 550M, 552M, 720M, 722M, 752M, or 752M) and a more lightly doped lateral extension (240E, 242E, 280E, 282E, 520E, 522E, 550E, 552E, 720E, 722E, 752E, or 752E).

Abstract: An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.

Abstract: An extended-drain insulated-gate field-effect transistor (104 or 106) contains first and second source/drain zones 324 and 184B or 364 and 186B) laterally separated by a channel (322 or 362) zone constituted by part of a first well region (184A or 186A). A gate dielectric layer (344 or 384) overlies the channel zone. A gate electrode (346 or 386) overlies the gate dielectric layer above the channel zone. The first source/drain zone is normally the source. The second S/D zone, normally the drain, is constituted with a second well region (184B or 186B). A well-separating portion 186A or 186B/212U) of the semiconductor body extends between the well regions and is more lightly doped than each well region. The configuration of the well regions cause the maximum electric field in the IGFET's portion of the semiconductor body to occur well below the upper semiconductor surface, typically at or close to where the well regions are closest to each other.

Abstract: A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.

Abstract: An insulated-gate field-effect transistor (100W) has a source (980) and a drain (242) laterally separated by a channel zone (244) of body material (180) of a semiconductor body. A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. A more heavily doped pocket portion (250) of the body material normally extends largely along only the source so that the IGFET is an asymmetric device. The source has a main source portion (980M) and a more lightly doped lateral source extension (980E). The semiconductor dopant which defines the source reaches multiple local concentration maxima in defining the source extension. The procedure involved in defining the source extension with semiconductor dopant that reaches two such local concentration maxima enables source/drain extensions of mutually different characteristics for three insulated-gate field-effect transistors to be defined in only two source/drain-extension doping operations.

Abstract: Methods of fabricating a semiconductor device are provided, the methods include forming a gate stack on a substrate, forming an insulation layer on the substrate to cover the gate stack, forming a spacer at both side walls of the gate stack by etching the insulation layer, and ion implanting impurities in the spacer or the insulation layer.

Abstract: A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.

Abstract: An apparatus and method for manufacturing rotated field effect transistors. The method comprises providing a substrate including a first gate structure and a second gate structure, which are not parallel to each other. The method further includes performing a first ion implant substantially orthogonal to an edge of the first gate structure to form a first impurity region and performing a second ion implant at a direction different than that of the first ion implant and substantially orthogonal to an edge of the second gate structure to form a second impurity region under the edge of the second gate structure.

Abstract: An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type.

Abstract: An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.

Abstract: A first resist mask and a second resist mask used for forming a gate electrode for a p-channel TFT and a gate electrode for an n-channel TFT are left, and a third resist mask is formed afterwards over a first area where one of the p-channel TFT and the n-channel TFT is to be formed; thus, a source region and a drain region are formed in a semiconductor film of the other one of the p-channel TFT and the n-channel TFT by adding first impurity ions using the second resist mask and the third resist mask. After that, the first resist mask, the second resist mask, and the third resist mask are removed, and a source region and a drain region are formed in a semiconductor film of the one of the p-channel TFT and the n-channel TFT by adding second impurity ions using a fourth resist mask.