Abstract: A semiconductor device includes a semiconductor substrate, an element isolation insulating film dividing an upper portion of the substrate into a plurality of first active regions, a source layer and a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The source layer and the drain layer are formed in spaced to each other in an upper portion of each of the first active regions. The first punch-through stopper layer is formed in a region of the first active region directly below the source layer and the second punch-through stopper layer is formed in a region of the first active region directly below the drain layer. The first punch-through stopper layer and the second punch-through stopper layer each has an effective impurity concentration higher than the semiconductor substrate. The first punch-through stopper layer and the source layer are separated in the channel region.

Abstract: In one example, a method disclosed herein includes reducing a temperature of at least an implant surface of a semiconducting substrate to a temperature less than ?50° C. and after reducing the temperature of the implant surface, performing at least one ion implantation process to implant ions into the substrate with the implant surface at a temperature less than ?50° C.

Abstract: A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.

Abstract: When MOS transistors having a plurality of threshold voltages in which a source and a drain form a symmetrical structure are mounted on the same substrate, electrically-symmetrical characteristics is provided with respect to an exchange of the source and the drain in each MOS transistor. A MOS transistor having a large threshold voltage is provided with a halo diffusion region, and halo implantation is not performed on a MOS transistor having a small threshold voltage.

Abstract: Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.

Abstract: According to an embodiment, a method for manufacturing a semiconductor device includes a step of forming an impurity layer on a semiconductor layer, the impurity layer including an impurity element to be doped to the semiconductor layer, and a step of applying a first gas in a plasma state including a first noble gas atom and a second gas in a plasma state including a second noble gas atom or hydrogen (H) toward the impurity layer, the second noble gas atom having a smaller atomic mass than the first noble gas atom.

Abstract: A process of integrated circuit manufacturing includes providing (32, 33) a spacer on a gate stack to provide a horizontal offset over the channel region for otherwise-direct application (34) of a PLDD implant dose in semiconductor, additionally depositing (35) a seal substance to provide a screen thickness vertically while thereby augmenting the spacer on the gate stack to provide an increased offset horizontally from the gate stack and form a horizontal screen free of etch, and subsequently providing (36) an NLDD implant dose for NLDD formation. Various integrated circuit structures, devices, and other processes of manufacture, and processes of testing are also disclosed.

Abstract: To provide a semiconductor device with a TFT, capable of reducing the electric resistance of a power supply wiring without increasing the off-current. The semiconductor device includes an insulating film with a surface; a semiconductor layer which is formed over the surface of the insulating film and which includes a channel region and a pair of source/drain regions and sandwiching the channel region; and a power supply wiring for supplying power to the source region. A concave portion is formed in the surface of the insulating film. The power supply wiring includes a layer formed from the same layer as the semiconductor layer, and has a first portion formed over the surface of the insulating film and a second portion formed in the concave portion. The bottom of the second portion is covered with an insulator.

Abstract: A method of manufacturing a power semiconductor device is provided. A first oxide layer is produced on a first main side of a substrate of a first conductivity type. A structured gate electrode layer with at least one opening is then formed on the first main side on top of the first oxide layer. A first dopant of the first conductivity type is implanted into the substrate on the first main side using the structured gate electrode layer as a mask, and the first dopant is diffused into the substrate. A second dopant of a second conductivity type is then implanted into the substrate on the first main side, and the second dopant is diffused into the substrate. After diffusing the first dopant into the substrate and before implanting the second dopant into the substrate, the first oxide layer is partially removed. The structured gate electrode layer can be used as a mask for implanting the second dopant.

Abstract: A method of manufacturing a semiconductor device comprises placing a semiconductor substrate in an ashing chamber, the semiconductor substrate having a gate, a silicon nitride gate sidewall offset spacer or a silicon nitride gate sidewall pacer formed thereon, and a photo resist residue remaining on the semiconductor substrate, introducing a gas mixture including D2 or T2 into the ashing chamber, and ashing the photo resist residue using a plasma that is formed from the gas mixture. The gas mixture can include a deuterium gas or a tritium gas having a volume ratio ranging between about 1% and about 20%. Embodiments can reduce Si recess and the loss of silicon nitride thin film during ashing.

Abstract: An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type.

Abstract: A method of manufacturing a semiconductor device, includes forming a gate insulating film and a gate electrode on a semiconductor substrate of a first conductivity type; forming a first drain region by implanting at a first predetermined dosage a first impurity of a second conductivity type corresponding to an opposite conductivity type with respect to the first conductivity type at a region of the semiconductor substrate in the vicinity of an end portion of the gate electrode; forming a second drain region substantially within the first drain region by implanting a second impurity of the second conductivity type at a second dosage that is greater than the first dosage; and forming a drain contact region within the second drain region by implanting a third impurity of the second conductivity type at a third dosage that is greater than the second dosage.

Abstract: An electronic device can include a drain region of a transistor, wherein the drain region has a first conductivity type. The electronic device can also include a channel region of the transistor, wherein the channel region has a second conductivity type opposite the first conductivity type. The electronic device can further include a first doped region having the first conductivity type, wherein the first doped region extends from the drain region towards the channel region. The electronic device can still further include a second doped region having the first conductivity type, wherein the second doped region is disposed between the first doped region and the channel region.

Abstract: A device having a self-aligned body on a first side of a gate is disclosed. The self-aligned body helps to achieve very low channel length for low Rdson. The self-aligned body is isolated, enabling to bias the body at different bias potentials. The device may be configured into a finger architecture having a plurality of transistors with commonly coupled, sources, commonly coupled gates, and commonly coupled drains to achieve high drive current outputs.

Abstract: A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from FinFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.

Abstract: Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction. In some embodiments, the microwave radiation has a frequency of about 5.8 gigahertz, and a temperature of the semiconductor construction does not exceed about 500° C. during the exposure to the microwave radiation.

Abstract: A method for integration is disclosed herein. The method includes forming an N-type double drain (NDD) layer, and fabricating at least one transistor from a controller circuitry and a transistor switch on a single chip. The controller circuitry is operable for controlling the transistor switch.

Abstract: A semiconductor device according to one embodiment includes: a first transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the substrate under the first film, and first epitaxial crystal layers formed on both sides of the first channel region in the substrate, the first layers comprising a first crystal; and a second transistor comprising a second gate electrode formed on the substrate via a second gate insulating film, a second channel region formed in the substrate under the second film, second epitaxial crystal layers formed on both sides of the second channel region in the substrate, and third epitaxial crystal layers formed on the second layers, the second layers comprising a second crystal, the third layers comprising the first crystal, the second transistor having a conductivity type different from that of the first transistor.

Abstract: Provided is a semiconductor device formed with a trench portion for providing a concave portion having a continually varying depth in a gate width direction and with a gate electrode provided within the trench portion and on a top surface thereof via a gate insulating film. Before the formation of the gate electrode, an impurity is added to at least a part of the source region and the drain region by ion implantation from an inner wall of the trench portion, and then heat treatment is performed for diffusion and activation to form a diffusion region from the surface of the trench portion down to a bottom portion thereof. Current flowing through a top surface of the concave portion of the gate electrode at high concentration can flow uniformly through the entire trench portion.

Abstract: A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor.

Abstract: The present invention provides a semiconductor device and a method for fabricating the same, wherein the method comprises: providing a germanium-based semiconductor substrate having a plurality of active regions and device isolation regions between the plurality of the active regions, wherein a gate dielectric layer and a gate over the gate dielectric layer are provided on the active regions, and the active regions include source and drain extension regions and deep source and drain regions; performing a first ion implantation process with respect to the source and drain extension regions, wherein the ions implanted in the first ion implantation process include silicon or carbon; performing a second ion implantation process with respect to the source and drain extension regions; performing a third ion implantation process with respect to the deep source and drain regions; performing an annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion impla

Abstract: A method of forming a semiconductor device comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate, forming a first region of the first conductivity type in the semiconductor layer, and forming a control region over the semiconductor layer and over part of the first region. A mask layer is formed over the semiconductor layer and outlines a first portion of a surface of the semiconductor layer over part of the first region. Semiconductor material of a second conductivity type is provided to the outlined first portion to provide a second region in the semiconductor layer.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a lightly doped source and drain (LDD) region that acts as an etch stop. The LDD region may act as an etch stop during an etching process implemented to form a recess in the substrate that defines a source and drain region of the device.

Abstract: An extended drain transistor (100) comprising a substrate (101), a gate (103) formed on the substrate (100), the gate (103) having a first side wall (104) and a second side wall (105) opposing the first side wall (104), an extended drain (106) implanted in a surface portion of the substrate (101) adjacent the second side wall (105) of the gate (103), a spacer (107) on the second side wall (105) of the gate (103), a source (108) implanted in a surface portion of the substrate (101) adjacent the first side wall (104) of the gate (103), and a drain (109) implanted in a surface portion of the substrate (101) adjacent the spacer (107) in such a manner that the extended drain (106) is arranged between the gate (103) and the drain (109).

Abstract: A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.

Abstract: The present invention discloses an electrostatic discharge protection device and a manufacturing method thereof. The electrostatic discharge protection device includes: a substrate, a gate, two N type lightly doped drains, an N type source, an N type drain, and two N type doped regions extending downward beneath and in contact with the source and drain respectively, such that when the source and drain are conducted with each other, at least part of the current flows through the two downwardly extending doped regions to increase the electrostatic discharge protection voltage of the electrostatic discharge protection device.

Abstract: The present invention discloses an electrostatic discharge protection device and a manufacturing method thereof. The electrostatic discharge protection device includes: a substrate, a gate, two N type lightly doped drains, an N type source, an N type drain, and two N type doped regions extending downward beneath and in contact with the source and drain respectively, such that when the source and drain are conducted with each other, at least part of the current flows through the two downwardly extending doped regions to increase the electrostatic discharge protection voltage of the electrostatic discharge protection device.

Abstract: Lateral DMOS devices having improved drain contact structures and methods for making the devices are disclosed. A semiconductor device comprises a semiconductor substrate; an epitaxial layer on top of the substrate; a drift region at a top surface of the epitaxial layer; a source region at a top surface of the epitaxial layer; a channel region between the source and drift regions; a gate positioned over a gate dielectric on top of the channel region; and a drain contact trench that electrically connects the drift layer and substrate. The contact trench includes a trench formed vertically from the drift region, through the epitaxial layer to the substrate and filled with an electrically conductive drain plug; electrically insulating spacers along sidewalls of the trench; and an electrically conductive drain strap on top of the drain contact trench that electrically connects the drain contact trench to the drift region.

Abstract: Provided is that the method of manufacturing the semiconductor device including a first process of implanting a first impurity of a first conductivity type in a source and drain region having an elevated structure, with a concentration equal to or less than 1E14 atoms/cm2, on the conditions that the concentration peak thereof is located more deeply than the interface between silicide and a semiconductor substrate, a second process of implanting a second impurity of a first conductivity type having a smaller mass than that of the first impurity in the source and drain region on the conditions that the peak thereof is located more shallowly than the concentration peak of the first impurity, and a third process of applying high-temperature millisecond annealing to the semiconductor substrate after the first and second processes.

Abstract: A method of forming a semiconductor device includes forming a transistor gate stack over a substrate having an active area and a shallow trench isolation (STI) region. First sidewall spacers are formed on the transistor gate stack, and an isotropic etch process is applied to isotropically remove an excess portion of a metal layer included within the transistor gate stack, the excess portion left unprotected by the first sidewall spacers. Second sidewall spacers are formed on the transistor gate stack, the second sidewall spacers completely encapsulating the metal layer of the transistor gate stack.

Abstract: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

Abstract: Punch-through in a transistor device is reduced by forming a well layer in an implant region, forming a stop layer in the well layer of lesser depth than the well layer, and forming a doped layer in the stop layer of lesser depth than the stop layer. The stop layer has a lower concentration of impurities than the doped layer in order to prevent punch-through without increasing junction leakage.

Abstract: Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.

Abstract: After a fin-semiconductor region (13) is formed on a substrate (11), impurity-containing gas and oxygen-containing gas are used to perform plasma doping on the fin-semiconductor region (13). This forms impurity-doped region (17) in at least side portions of the fin-semiconductor region (13).

Abstract: A DMOS-transistor having enhanced dielectric strength includes a first well region. A highly doped source region is located in the first well region and is complementarily doped thereto. A highly doped bulk connection region is located in the first well region and has the same type of doping as the first well region. A gate electrode and a gate insulation layer for forming a transistor channel are included on a surface of the first well region. The DMOS-transistor further comprises an isolation structure, a highly doped drain doping region, and a second well complementarily doped to the first well region. The second well accommodates the first well region and the drain doping region. A highly doped region is formed at least adjacent to the second well and has the same type of doping as the second well for enhancing the dielectric strength of the highly doped source region.

Abstract: A method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface and forming a first gate region and a second gate region on the surface.

Abstract: A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electrode. After impurities are implanted, the mask member is removed. Source and drain regions are formed by implanting impurities into the surface layer of the semiconductor substrate on both sides of the gate electrode. It is possible to reduce variations of cross sectional shape of gate electrodes and set an impurity concentration of the gate electrode independently from an impurity concentration of the source and drain regions.

Abstract: An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.

Abstract: A body contact structure which reduce parasitic capacitance and improves body resistance of a device and methods of manufacture. The method includes forming a gate insulator material and gate electrode material on a substrate. The method further includes patterning the gate insulator material and the gate electrode material to form a gate structure having a shape with a first portion isolated from a second portion. The method further includes forming source and drain regions on sides of the first portion and a body contact at a side and under an area of the second portion, and forming an interlevel dielectric within a space that isolates the first portion from the second portion of the gate structure, and over the gate structure, source and drain regions and the body contact.

Abstract: An embodiment of the disclosure includes doping a FinFET. A dopant-rich layer comprising an dopant is formed on a top surface and sidewalls of a semiconductor fin of a substrate. A cap layer is formed to cover the dopant-rich layer. The substrate is annealed to drives the dopant from the dopant-rich layer into the semiconductor fin.

Abstract: Methods for manufacturing a semiconductor device include forming a seed layer containing a silicon material on a substrate. An amorphous silicon layer containing amorphous silicon material is formed on the seed layer. The amorphous silicon layer is doped with an impurity. A laser beam is irradiated onto the amorphous silicon layer to produce a phase change of the amorphous silicon layer and change the amorphous silicon layer into a single-crystal silicon layer based on the seed layer.

Abstract: Methods of manufacturing a semiconductor device include forming a gate electrode on a semiconductor substrate, forming spacers on side walls of the gate electrode, and doping impurities into the semiconductor substrate on both sides of the spacers to form highly doped impurity regions. The spacers are selectively etched to expose portions of the semiconductor substrate, and more lightly doped impurity regions are formed in the semiconductor substrate between the highly doped impurity regions and the gate electrode.

Abstract: A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type formed on the first semiconductor layer; a first buried layer of the first conductivity type selectively formed in the second semiconductor layer and having a first peak impurity concentration at a first depth; a second buried layer of a second conductivity type selectively formed in the second semiconductor layer and having a second peak impurity concentration at a second depth; a base layer of the second conductivity type selectively formed in the second semiconductor layer and overlapping with an upper portion of the second buried layer; a source layer of the first conductivity type selectively formed in the base layer; and a gate electrode formed on the base layer and on the second semiconductor layer above the first buried layer with a gate insulating film being interposed therebetween.

Abstract: A manufacturing method of a NOR flash memory with phosphorous and arsenic ion implantations mainly implants both phosphorous and arsenic ions on a drain area of a transistor memory unit, and controls specific energy and dosage for the implantation to reduce the defects of a memory device and improve the yield rate of the NOR flash memory.

Abstract: A method of forming MOS transistor includes the steps of performing a pocket implantation process on a substrate having a gate stack, performing a co-implanted ion implantation process on the substrate at a temperature less than room temperature, performing a lightly doped source/drain implantation process on the substrate, and forming source and drain regions in the substrate, adjacent the gate stack.

Abstract: A method of forming a dopant implant region in a MOS transistor device having a dopant profile having a target dopant concentration includes implanting a first concentration of dopants into a region of a substrate, where the first concentration of dopants is less than the target dopant concentration, and without annealing the substrate after the implanting step, performing at least one second implanting step to implant at least one second concentration of dopants into the region of the substrate to bring the dopant concentration in the region to the target dopant concentration.

Abstract: By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.

Abstract: Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction. In some embodiments, the microwave radiation has a frequency of about 5.8 gigahertz, and a temperature of the semiconductor construction does not exceed about 500° C. during the exposure to the microwave radiation.

Abstract: A thermal process is disclosed. The thermal process preferably includes the steps of: providing a semiconductor substrate ready to be heated; and utilizing at least a first heating beam and a second heating beam with different energy density to heat the semiconductor substrate simultaneously. Accordingly, the present invention no only eliminates the need of switching between two different thermal processing equipments and shortens the overall fabrication cycle time, but also improves the pattern effect caused by the conventional front side heating.