Having Substrate Registration Feature (e.g., Alignment Mark) Patents (Class 438/401)
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Patent number: 8053910Abstract: To provide a semiconductor substrate whose columnar member for alignment is difficult to fall off and a manufacturing method thereof. An alignment mark 24 (columnar member for alignment) and protection posts 26 surrounding the alignment mark 24 to protect the alignment mark are disposed in an alignment mark forming region 14 of a semiconductor wafer 101 (semiconductor substrate). Each of the protection posts has a diameter (maximum diameter) of, for example, 0.6 ?m. The protection posts 26 are arranged such that the diameter of each of the columnar protection posts 26 is greater than a diameter (for example, 0.2 ?m) of the alignment mark 24. That is, the protection posts 26 are arranged such that the contact area between each of the protection posts 26 and an underlayer thereof (dummy wire layer 22) is greater than the contact area between the alignment mark 24 and an underlayer thereof (dummy wire layer 22).Type: GrantFiled: June 4, 2009Date of Patent: November 8, 2011Assignee: Oki Semiconductor Co., Ltd.Inventors: Tomoyuki Terashima, Hirokazu Uchida
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Patent number: 8049345Abstract: An overlay mark is used in pattern registration on a semiconductor wafer with an oxide layer. Four sets of two trenches each are formed in the oxide layer. Each trench in a set is parallel to the other trench of the same set. The trenches are configured such that each set forms one side of a box shape.Type: GrantFiled: March 21, 2011Date of Patent: November 1, 2011Assignee: MACRONIX International Co., Ltd.Inventors: Chin-Cheng Yang, Chih-Hao Huang
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Patent number: 8043927Abstract: In a method of manufacturing a complementary metal-oxide semiconductor (CMOS) image sensor (CIS), an epitaxial layer may be formed on a first substrate including a chip area and a scribe lane area. A first impurity layer may be formed adjacent to the first substrate by implanting first impurities into the epitaxial layer. A photodiode may be formed in the epitaxial layer on the chip area. A circuit element electrically connected to the photodiode may be formed on the epitaxial layer. A protective layer protecting the circuit element may be formed on the epitaxial layer. A second substrate may be attached onto the protective layer. The first substrate may be removed to expose the epitaxial layer. A color filter layer may be formed on the exposed epitaxial layer using the first impurity layer as an alignment key. A microlens may be formed over the color filter layer.Type: GrantFiled: June 22, 2009Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Jun Park, Tae-Hun Lee, Seung-Hun Shin
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Patent number: 8043928Abstract: A semiconductor wafer includes multi chip areas each including two or more device chip areas and arranged in an X-axis direction and a Y-axis direction, a plurality of scribe lines formed parallel to the X axis and the Y axis such as to separate the device chip areas from each other, and one or more alignment marks formed in each of the multi chip areas on the scribe lines between adjacent ones of the device chip areas included in one multi chip area, the one or more alignment marks being fewer than the device chip areas in each of the multi chip areas and used for positioning of the semiconductor wafer.Type: GrantFiled: February 10, 2010Date of Patent: October 25, 2011Assignee: Ricoh Company, Ltd.Inventor: Koichi Sogawa
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Patent number: 8043933Abstract: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to apparatus and methods for forming shallow trench isolations having recesses with rounded bottoms. One embodiment of the present invention comprises forming a recess in a filled trench structure by removing a portion of a material from the filled trench structure and rounding bottom corners of the recess. Rounding bottom corners is performed by depositing a conformal layer of the same material filled in the trench structure over the substrate and removing the conformal layer of the material from sidewalls of the recess.Type: GrantFiled: November 18, 2009Date of Patent: October 25, 2011Assignee: Applied Materials, Inc.Inventors: Chien-Teh Kao, Xinliang Lu, Zhenbin Ge, Mei Chang, Hoiman Raymond Hung, Nitin Ingle
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Patent number: 8039356Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate and lines the first opening with a protective liner. The method deposits a material into the first opening and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. The method removes the material from the first opening through the second opening in the protective material. The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.Type: GrantFiled: January 20, 2010Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Russell T. Herrin, Peter J. Lindgren, Edmund J. Sprogis, Anthony K. Stamper
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Publication number: 20110250732Abstract: The invention is based on a method for aligning an electronic CMOS structure with respect to a buried structure in the case of a bonded and thinned back stack of semiconductor wafers. The method is intended to avoid “front side to rear side” alignments. The proposed method for aligning the electronic CMOS structure uses the formation of alignment marks (7; 7a, 7b) in the process of fabricating the structure to be buried on a front side, which is used for bonding of the semiconductor wafer (1), which includes the structure (2) to be buried. The alignment marks (7) are formed on the edge of the semiconductor wafer. A cover wafer (5) is provided with first thinned portions (10a; 10b) of the wafer thickness provided from the bonding side at positions corresponding to positions of the alignment marks (7). A plan view of the alignment marks (7) is obtained after wafer bonding.Type: ApplicationFiled: July 27, 2009Publication date: October 13, 2011Inventors: Holger Klingner, Jens Ungelenk
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Publication number: 20110241119Abstract: The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a substrate having a device region and an alignment region; a first shallow trench isolation (STI) feature in the alignment region and having a first depth D1; a second STI feature in the device region and having a second depth D2; an alignment mark with patterned features overlying the first STI in the alignment region; and a gate stack formed on an active region in the device region.Type: ApplicationFiled: July 13, 2010Publication date: October 6, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuei Shun Chen, Meng-Wei Chen, George Liu, Jiann Yuan Huang, Chia-Ching Lin
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Publication number: 20110244647Abstract: A method for forming a mark structure on a substrate comprising a plurality of lines. The lines extend parallel to each other in a first direction and are arranged with a pitch between each pair of lines that is directed in a second direction perpendicular to the first direction. The pitch between each pair of selected lines differs from the pitch between each other pair of selected lines.Type: ApplicationFiled: June 15, 2011Publication date: October 6, 2011Applicant: ASML Netherlands B.V.Inventor: Patrick WARNAAR
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Patent number: 8030222Abstract: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.Type: GrantFiled: July 31, 2006Date of Patent: October 4, 2011Assignee: Round Rock Research, LLCInventors: Luan Tran, Bill Stanton
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Patent number: 8026149Abstract: To provide a laser irradiation apparatus which performs alignment of an irradiated object and emits a laser beam precisely, a laser irradiation method, and a manufacturing method of a TFT with high reliability with the use of a method for precisely targeting a desired irradiation position of the laser beam. A substrate with marker is mounted on a stage formed using a material which transmits infrared light; a marker, which is provided in the substrate with marker mounted on the stage, is detected using a camera capable of sensing infrared light, and a position of the stage is controlled; a laser beam is emitted from a laser oscillator; the laser beam emitted from the laser oscillator is processed into a linear shape by an optical system, and the substrate with marker mounted on the stage is irradiated with the laser beam.Type: GrantFiled: November 19, 2007Date of Patent: September 27, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koichiro Tanaka, Takatsugu Omata
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Patent number: 8027528Abstract: A method is for calculating a height of a chuck top. A height of the top surface of the chuck top which corresponds to an arbitrary position specified on the XY coordinate plane by a computer is calculated in each of the four quadrants based on a coordinate transformation formulas. The method includes setting, by using the computer, a conical model in which two adjacent points other than the center point of the chuck top which correspond to the specified coordinates in a predetermined quadrant of the XY coordinate plane are obtained on a circumference having the center point of the chuck top as the origin and specifying an arbitrary point in the predetermined quadrant by using the computer and calculating a height of the arbitrary point of the chuck top based on the conical model, the coordinate transformation formulas and the specified coordinates.Type: GrantFiled: February 20, 2008Date of Patent: September 27, 2011Assignee: Tokyo Electron LimitedInventors: Kazunari Ishii, Masaru Suzuki
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Publication number: 20110227188Abstract: An integrated circuit includes a core area. The core area has at least one edge region and a plurality of transistors disposed in the edge region. A plurality of dummy structures are disposed outside the core area and adjacent to the at least one edge region. Each channel of the transistors in a channel width direction faces at least one of the dummy structures.Type: ApplicationFiled: March 17, 2010Publication date: September 22, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Hsun WANG, Chih-Sheng CHANG, Hsien-Hui MENG
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Patent number: 8022559Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.Type: GrantFiled: September 15, 2006Date of Patent: September 20, 2011Assignee: Sharp Kabushiki KaishaInventors: Tomoki Noda, Masanori Takeuchi, Kenji Enda
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Patent number: 8017426Abstract: A backside illuminated image sensor includes a sensor layer comprising photosensitive elements of the pixel array, an epitaxial layer formed on a frontside surface of the sensor layer, and a color filter array formed on a backside surface of the sensor layer. The epitaxial layer comprises polysilicon color filter array alignment marks formed in locations corresponding to respective color filter array alignment mark openings in the frontside surface of the sensor layer. The color filter array is aligned to the color filter array alignment marks of the epitaxial layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.Type: GrantFiled: July 9, 2008Date of Patent: September 13, 2011Assignee: Omnivision Technologies, Inc.Inventor: Frederick T. Brady
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Patent number: 8008789Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.Type: GrantFiled: December 30, 2010Date of Patent: August 30, 2011Assignee: Sharp Kabushiki KaishaInventors: Tomoki Noda, Masanori Takeuchi, Kenji Enda
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Patent number: 8003482Abstract: A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features.Type: GrantFiled: November 19, 2009Date of Patent: August 23, 2011Assignee: Micron Technology, Inc.Inventors: William R. Brown, David Kewley, Adam Olson
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Patent number: 8003412Abstract: A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction mirror arrays on the substrate, each diffraction mirror array of the set of at least three diffraction minor arrays comprising a single row of mirrors, all mirrors in any particular diffraction mirror array spaced apart a same distance, mirrors in different diffraction mirror arrays spaced apart different distances; measuring an intensity of light diffracted from the set of at least three diffraction mirror arrays onto an array of photo detectors; and adjusting a temperature of the photomask or photomask and lens based on the measured intensity of light.Type: GrantFiled: September 23, 2010Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Axel A. Granados, Benjamin A. Fox, Nathaniel J. Gibbs, Andrew B. Maki, Trevor J. Timpane
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Patent number: 7999400Abstract: A semiconductor device and a method for manufacturing such semiconductor device are provided. Specifically, in the semiconductor manufacture, a recessed alignment mark is formed on a front plane of a high distortion point glass substrate as a target for alignment for bonding, and the recessed alignment mark is permitted to have a shape which extends to an external side of the semiconductor device. Thus, excellent bonding between the high distortion point glass substrate and the semiconductor device can be provided, and at the same time, since the recessed alignment mark is not sealed, the bonding state can be maintained even when the high distortion point glass substrate is exposed under the high temperature condition after bonding the semiconductor device.Type: GrantFiled: January 30, 2006Date of Patent: August 16, 2011Assignee: Sharp Kabushiki KaishaInventors: Takashi Itoga, Yasuyuki Ogawa
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Patent number: 7998826Abstract: A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps.Type: GrantFiled: September 7, 2007Date of Patent: August 16, 2011Assignee: MACRONIX International Co., Ltd.Inventor: Chin-Cheng Yang
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Patent number: 7998827Abstract: A method of manufacturing a semiconductor device, includes forming a structure wherein a first alignment mark is provided in a first alignment-mark arrangement area of a first layer, a second alignment mark is provided in a second alignment-mark arrangement area of a second layer, a dummy pattern is provided above the first alignment-mark arrangement area, and substantially no dummy pattern is provided above the second alignment-mark arrangement area, and aligning a third layer provided above the structure by using the second alignment mark.Type: GrantFiled: July 17, 2008Date of Patent: August 16, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Masaaki Hatano
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Publication number: 20110195539Abstract: A method for manufacturing a light emitting device according to an embodiment of the present invention includes preparing a growth substrate; selectively forming a projection pattern on the growth substrate; forming a first conductive type semiconductor layer on the growth substrate and the projection pattern; forming an active layer on the first conductive type semiconductor layer; forming a second conductive type semiconductor layer on the active layer; and executing an isolation etching for selectively removing the first conductive type semiconductor layer, the active layer, and the second conductive type semiconductor layer including the projection pattern.Type: ApplicationFiled: November 17, 2010Publication date: August 11, 2011Inventors: Dae Sung Kang, Sang Hoon Han
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Publication number: 20110194112Abstract: Semiconductor wafer alignment markers and associated systems and methods are disclosed. A wafer in accordance with a particular embodiment includes a wafer substrate having an alignment marker that includes a first structure and a second structure, each having a pitch, with first features and second features positioned within the pitch. The first features are positioned to generate first phase portions of an interference pattern, with at least one of the first features having a width different than another of the first features in the pitch, and with the second features positioned to generate second phase portions of the interference pattern, with the second phase portions having a second phase opposite the first phase, and with at least one of the second features having a width different than that of another of the second features in the pitch. The pitch for the first structure is different than the pitch for the second structure.Type: ApplicationFiled: February 8, 2010Publication date: August 11, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Jianming Zhou, Craig A. Hickman, Yuan He
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Patent number: 7989966Abstract: A mark structure includes on a substrate, at least four lines. The lines extend parallel to each other in a first direction and are arranged with a pitch between each pair of lines that is directed in a second direction perpendicular to the first direction. The pitch between each pair of selected lines differs from the pitch between each other pair of selected lines.Type: GrantFiled: February 17, 2009Date of Patent: August 2, 2011Assignee: ASML Netherlands B.V.Inventor: Patrick Warnaar
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Patent number: 7989967Abstract: As part of a first configured laser operation, a smooth, more reflective marking area is formed at a surface of a substrate (e.g., integral heat spreader, or IHS). In a second configured laser operation, a mark is formed at the surface of the substrate within the marking area. The mark contrasts strongly with the reflective surface of the substrate in the marking area. As a result, the mark may be read with an optoelectronic imaging system with a higher rate of reliability than marks disposed at a substrate surface having a microtopographical profile with greater variation from a nominal surface plane. An IHS with a mark so disposed provides benefits when include as a portion of an integrated circuit package, which in turn provides benefits when included as a portion of an electronic system.Type: GrantFiled: July 9, 2009Date of Patent: August 2, 2011Assignee: Intel CorporationInventor: Lee Kim Loon
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Patent number: 7989303Abstract: In an embodiment, a method of creating an alignment mark on a substrate includes forming a plurality of lines segmented into electrically conducting line segments and space segments, thereby forming spaces between the lines to form a macroscopic structure in a first layer of the substrate, creating a plurality of electrically conducting trenches in a second layer of the substrate, and arranging the plurality of trenches to be in electrical contact with the line segments and overlapping the space segments at least partially.Type: GrantFiled: December 29, 2008Date of Patent: August 2, 2011Assignee: ASML Netherlands B.V.Inventor: Richard Johannes Franciscus Van Haren
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Publication number: 20110177670Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate and lines the first opening with a protective liner. The method deposits a material into the first opening and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. The method removes the material from the first opening through the second opening in the protective material. The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.Type: ApplicationFiled: January 20, 2010Publication date: July 21, 2011Applicant: International Business Machines CorporatonInventors: Russell T. Herrin, Peter J. Lindgren, Edmund J. Sprogis, Anthony K. Stamper
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Patent number: 7981762Abstract: A method of forming a pre-metal dielectric (PMD) layer of a semiconductor device using a chemical mechanical polishing (CMP) process which can be suitable for easily recognizing an alignment key. Such a method can reduce or otherwise eliminate alignment key erosion due to CMP by previously forming an alignment key pattern of polysilicon in an active region of a semiconductor scribe lane.Type: GrantFiled: November 29, 2007Date of Patent: July 19, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Sang-Tae Moon
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Patent number: 7977141Abstract: A method of manufacturing a solid-state image pickup device according to an embodiment includes forming first and second holes in a semiconductor substrate, forming insulating films on surfaces of the first and second holes, forming a contact and an alignment mark by embedding a conducting material in the first and second holes, forming a photodiode in the semiconductor substrate, forming a wiring layer including a connecting part for connecting to the contact and a wiring for connecting to the connecting part, bonding a supporting substrate on the wiring layer, exposing the contact and the alignment mark on the surface of the semiconductor substrate by reducing the semiconductor substrate in thickness, and forming a filter and a lens on the photodiode based on the alignment mark.Type: GrantFiled: August 31, 2009Date of Patent: July 12, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tsubasa Harada, Atsushi Murakoshi
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Publication number: 20110164808Abstract: A semiconductor die includes a group of spacer cells within the semiconductor die. The spacer cells include fiducial markings therein. The fiducial markings can be located within a metal layer, a diffusion layer, a polysilicon layer, and/or a Shallow Trench Isolation (STI) structure.Type: ApplicationFiled: July 7, 2010Publication date: July 7, 2011Applicant: QUALCOMM INCORPORATEDInventors: Michael Laisne, Xiangdong Pan, Foua Vang, Prayag B. Patel, Donald D. Lyons, Martin Villafana
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Patent number: 7972932Abstract: A mark forming method includes forming a first mask layer on a semiconductor substrate; forming at least three first patterns having periodicity on the first mask layer; forming a second mask layer on the first mask layer having the first patterns formed thereon; and forming an opening in the second mask layer to cover at least two patterns on ends of the at least three first patterns, thereby forming a mark composed of exposed ones of the first patterns.Type: GrantFiled: March 20, 2009Date of Patent: July 5, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Sato, Hiroko Nakamura, Masaru Suzuki, Ryoichi Inanami
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Patent number: 7972904Abstract: A wafer level packaging method is revealed. Firstly, a wafer with a plurality of bumps disposed on a surface is provided. Placing a dielectric tape on a mold plate is followed. Then, the wafer is laminated with the mold plate to make the dielectric tape be compliantly bonded to the surface of the wafer and to make the bumps be embedded in the dielectric tape. After removing the mold plate, flattening the dielectric tape to form a plurality of exposed surfaces of the bumps wherein the exposed surfaces and the flattened surface of the dielectric tape are coplanar. Therefore, the exposed surfaces of the bumps can be regarded as effective alignment points for easy pattern recognition of the wafer level packaged wafers during singulation process.Type: GrantFiled: April 14, 2009Date of Patent: July 5, 2011Assignee: Powertech Technology Inc.Inventor: Wen-Jeng Fan
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Patent number: 7973419Abstract: According to an aspect of the invention, there is provided a semiconductor device including a semiconductor substrate, a p-type impurity diffusion layer formed on the semiconductor substrate, and Ni silicide formed on the diffusion layer, wherein an alignment mark for lithography is formed on the Ni silicide.Type: GrantFiled: October 18, 2006Date of Patent: July 5, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tomoyasu Kudo, Kazutaka Ishigo
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Publication number: 20110159631Abstract: A method for fabricating a backside illuminated image sensor is provided. An exemplary method can include providing a substrate having a front surface and a back surface; forming an alignment mark at the front surface of the substrate, wherein the alignment mark is detectable for alignment from the back surface; and processing the substrate from the back surface by performing registration from the back surface and using the alignment mark as a reference.Type: ApplicationFiled: March 9, 2011Publication date: June 30, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chu Fu, Gwo-Yuh Shiau, Liang-Lung Yao, Yuan-Chih Hsieh, Feng-Jia Shiu
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Publication number: 20110156286Abstract: A semiconductor device includes an alignment mark formed over a semiconductor substrate and an inhibition pattern arranged over the alignment mark with a pattern edge of the inhibition pattern located in a mark functional region of the alignment mark in order to inhibit the alignment mark being recognized as such by an image detector of an exposure device.Type: ApplicationFiled: December 22, 2010Publication date: June 30, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Fumio Ushida, Shigeki Yoshida
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Publication number: 20110151641Abstract: A method of forming a semiconductor device includes the following processes. A first groove is formed in a semiconductor substrate. An insulating film is formed in the first groove. An interlayer insulating film is formed over the semiconductor substrate. A removing process is performed to remove a part of the interlayer insulating film and a part of the insulating film to form an alignment mark in the first groove.Type: ApplicationFiled: December 16, 2010Publication date: June 23, 2011Applicant: ELPIDA MEMORY, INC.Inventor: Yohei OTA
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Patent number: 7964472Abstract: A semiconductor device is manufactured by forming a mask having a first opening and a second opening wider than the first opening on a principal surface of a first conductivity type semiconductor substrate, etching semiconductor portions of the first conductivity type semiconductor substrate exposed in the first and second openings to thereby form a first trench in the first opening and form a second trench deeper than the first trench in the second opening, and filling the first and second trenches with a second conductivity type semiconductor to concurrently form an alignment marker for device production and a junction structure of alternate arrangement of the first conductivity type semiconductor and the second conductivity type semiconductor. In this manner, it is possible to provide a semiconductor device in which a parallel pn structure and an alignment marker can be formed concurrently to improve the efficiency of a manufacturing process.Type: GrantFiled: June 2, 2009Date of Patent: June 21, 2011Assignee: Fuji Electric Systems Co., Ltd.Inventor: Ayako Yajima
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Patent number: 7960242Abstract: A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.Type: GrantFiled: July 30, 2010Date of Patent: June 14, 2011Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar
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Patent number: 7955946Abstract: The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined.Type: GrantFiled: May 22, 2006Date of Patent: June 7, 2011Assignee: Micron Technology, Inc.Inventors: Dave Pratt, Kyle Kirby, Steve Oliver, Mark Hiatt
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Publication number: 20110127645Abstract: A wafer and a method for forming the same are disclosed. The wafer forming method can separate respective chips from others by performing a Deep Reactive Ion Etching (DRIE) process on a wafer including a plurality of chips. The wafer includes a plurality of chips configured to be arranged in row and column directions on the wafer, a scribe line configured to be formed among the plurality of chips so as to separate each chip, and an align key line configured to be formed in one side of the wafer so as to form an align key pattern.Type: ApplicationFiled: June 2, 2010Publication date: June 2, 2011Applicant: Hynix Semiconductor Inc.Inventors: Hee Bok KANG, Young Wug Kim
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Publication number: 20110127644Abstract: A wafer and a method for forming the same are disclosed. The wafer forming method can separate respective chips from others by performing a Deep Reactive Ion Etching (DRIE) process on a wafer including a plurality of chips. The wafer includes a plurality of chips configured to be arranged in row and column directions on the wafer, a scribe region configured to be formed among the plurality of chips so as to separate each chip, and an alignment key pattern configured to be arranged on the plurality of chips.Type: ApplicationFiled: June 2, 2010Publication date: June 2, 2011Applicant: Hynix Semiconductor Inc.Inventors: Hee Bok Kang, Young Wug Kim, Si Choon Yeom
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Patent number: 7947563Abstract: A chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying their positions. In the chip forming position specifying method, different marks are formed for every chip in a transfer mask (hereinafter called “mark forming mask”) used to form a wiring layer, in addition to normal functional wirings. The positions of the chips on the wafer are respectively specified according to combinations of the marks of a plurality of the mark forming masks, which have been transferred onto the wafer.Type: GrantFiled: February 9, 2007Date of Patent: May 24, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Shigenari Aoki
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Publication number: 20110115057Abstract: A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region.Type: ApplicationFiled: November 16, 2009Publication date: May 19, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chyi Harn, Sophia Wang, Chun-Hung Lin, Hsien-Wei Chen, Ming-Yen Chiu
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Publication number: 20110117719Abstract: A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features.Type: ApplicationFiled: November 19, 2009Publication date: May 19, 2011Inventors: William R. Brown, David Kewley, Adam Olson
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Patent number: 7943478Abstract: In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer.Type: GrantFiled: August 14, 2009Date of Patent: May 17, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Haruhiko Koyama, Mitsuhiro Noguchi, Minori Kajimoto
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Patent number: 7944063Abstract: Alignment marks for use on substrates. In one example, the alignment marks consist of periodic 2-dimensional arrays of structures, the spacing of the structures being smaller than an alignment beam but larger than an exposure beam.Type: GrantFiled: June 1, 2006Date of Patent: May 17, 2011Assignee: ASML Netherlands B.V.Inventors: Richard Johannes Franciscus Van Haren, Sami Musa
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Patent number: 7944064Abstract: A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an alignment post electrode which is formed in the alignment mark formation region and smaller in number than the post electrodes formed in each semiconductor device formation region.Type: GrantFiled: January 22, 2007Date of Patent: May 17, 2011Assignee: Casio Computer Co., Ltd.Inventors: Shinji Wakisaka, Tomohiro Ito, Shigeru Yokoyama, Osamu Kuwabara, Norihiko Kaneko, Syouichi Kotani
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Patent number: 7939822Abstract: The present invention provides a manufacturing process using a droplet-discharging method that is suitable for manufacturing a large substrate in mass production. A photosensitive material solution of a conductive film is selectively discharged by a droplet-discharging method, selectively exposed to laser light, and developed or etched, thereby allowing only the region exposed to laser light to be left and realizing a source wiring and a drain wiring having a more microscopic pattern than the pattern itself formed by discharging. One feature of the source wiring and the drain wiring is that the source wiring and the drain wiring cross an island-like semiconductor layer and overlap it.Type: GrantFiled: December 30, 2008Date of Patent: May 10, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinji Maekawa, Hideaki Kuwabara
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Patent number: 7935893Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.Type: GrantFiled: January 12, 2009Date of Patent: May 3, 2011Assignee: Ibiden Co., Ltd.Inventors: Hironori Tanaka, Kazuhiro Yoshikawa, Naoaki Fujii, Atsunari Yamashita
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Patent number: 7932157Abstract: Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent levels are patterned. The manner of using the mask also allows different types of test structures having different features to be formed. The different types of test structures can provide insight into performance characteristics of different types of devices.Type: GrantFiled: June 30, 2007Date of Patent: April 26, 2011Assignee: SanDisk CorporationInventors: Calvin K. Li, Yung-Tin Chen, En-Hsing Chen, Paul Wai Kie Poon